CN112992781A - Chip and chip separation method - Google Patents

Chip and chip separation method Download PDF

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Publication number
CN112992781A
CN112992781A CN201911288565.3A CN201911288565A CN112992781A CN 112992781 A CN112992781 A CN 112992781A CN 201911288565 A CN201911288565 A CN 201911288565A CN 112992781 A CN112992781 A CN 112992781A
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chip
chips
grooves
separation
groove
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杨华
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Dicing (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The invention discloses a chip and a chip separation method, which comprises the following steps: arranging a plurality of test and monitor pattern structures at positions on the wafer such that the width of the separation grooves between the chips is less than 20 microns in at least one direction; forming a separation groove etching mask plate, and etching the dielectric film or the dielectric film and the metal film of the separation groove and the substrate below the separation groove by using the separation groove etching mask plate; back side thinning is performed and the chip and chip are separated by applying pressure. The invention can reduce the width of the separation groove between the chips, and improve the stability of the division and the reliability of the chips.

Description

Chip and chip separation method
Technical Field
The present invention relates to a semiconductor integrated circuit manufacturing process, and more particularly, to a chip and a chip separation method.
Background
Fig. 1 is a schematic diagram illustrating the distribution of chips on a wafer in the prior art. Forming a plurality of chips 2 and a plurality of test and monitor pattern structures 3A and 3B on a wafer, with a separation groove formed between the chips; wherein the test and monitoring pattern structure 3A is parallel to the Y-axis and the test and monitoring pattern structure 3B is parallel to the X-axis. The chip 2 and the test and monitor pattern structures 3A and 3B are formed by multiple exposures, each exposure field 1 including a plurality of the chips 2 and a plurality of the test and monitor pattern structures 3A and 3B. The test and monitor pattern structures 3A are placed in the separation grooves 4B parallel to the Y-axis in the exposure field 1, and the test and monitor pattern structures 3B are placed in the separation grooves 4A parallel to the X-axis in the exposure field 1. No test and monitor pattern structure is placed in the separation grooves 4C parallel to the Y axis and the separation grooves 4D parallel to the X axis between the exposure fields 1.
The previous production processes required to form the chips on the wafer are the formation of active devices, passive devices, metal interconnects, surface passivation, and wire ports. After the front end of the production process, the wafer is typically thinned to a desired thickness, for example, 150 to 300 microns, by grinding the back side of the wafer; and then, cutting the separation groove between the chip and the chip by using a scribing knife so as to realize the separation between the chip and the chip. And packaging and testing the separated chips to obtain the final product.
The widths of the separating grooves 4a4, B4, C and 4D in the prior art are generally 60 to 100 micrometers, and in the case of a large chip area, for example, more than 100 square millimeters, the influence of the widths of the separating grooves on the total number of chips per unit wafer is negligible. On one hand, as the integration level of the chip is continuously improved, the size of the chip is continuously and rapidly reduced; on the other hand, in some applications, the chip area is very small, i.e., less than 1 mm square, and the width of the separation groove has a very large influence on the total number of chips per wafer. For example, for chips having a size of 1 mm x 1 mm, there may be an increase of more than 8% in the total number of chips per unit wafer of 200 mm size when the size of the separation grooves is reduced from 60 microns to 10 microns.
In the prior art, the width of the separation groove is mainly determined by two factors, namely the width of the dicing blade and the corresponding dicing technology, and when the separation groove is smaller than a certain width, for example, 60 micrometers, a special blade and technology are required, in which the edge of the chip after dicing is rough, and in some cases, even a tiny crack affects the quality of the chip. Another factor is the required width of the test and monitor pattern structures placed in the separator tank, where the test structures include critical dimension test patterns, film thickness test patterns, trench depth test patterns, process control monitoring test structures (PCM), wafer level reliability test structures, etc.; monitoring pattern structures, namely alignment patterns, alignment marks used by a photoetching machine, a test structure of alignment precision and the like; when the width of the separation groove needs to be reduced, the related technical problems of the above two factors need to be solved at the same time.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a chip and a chip separation method, which can reduce the width of a separation groove between the chips to be less than 20 microns and improve the separation stability and the chip reliability.
In order to solve the above technical problems, the chip and the chip separation method provided by the invention comprise the following steps:
step one, forming a plurality of chips and a plurality of test and monitor pattern structures on a wafer, wherein a separation groove is formed between the chips, the chips are mutually isolated through the separation groove, and the width of the separation groove between each chip and the adjacent chip is smaller than 20 microns at least in one direction.
And step two, forming a separation groove etching mask plate for forming groove patterns in the separation grooves among the chips, wherein the pattern structure of the separation groove etching mask plate meets the condition that the formed groove patterns are the same as the pattern structure of the separation grooves among the chips, and the width of each groove pattern is smaller than the width of the corresponding separation groove.
And thirdly, forming a photoetching pattern on the wafer by using the separation groove etching mask plate, wherein the photoetching pattern is composed of photoresist grooves etched by photoresist, the photoresist grooves are formed above the separation grooves, and the outer areas of the photoresist grooves are covered and protected by the photoresist.
And step four, etching the dielectric film or the dielectric film and the metal film below the photoresist groove by using the photoresist as a mask and adopting a dry etching process or a wet etching process.
And fifthly, etching part of the thickness of the substrate of the wafer by using the photoresist as a mask and using a dry etching process or a wet and dry etching process, and finally forming the groove pattern on the wafer below the photoresist groove.
And sixthly, protecting the front side of the wafer, and thinning the wafer to a required thickness by grinding the back side of the wafer, wherein the thickness ensures that all grooves of the groove pattern formed on the front side of the wafer are not exposed and the chips are not separated.
And step seven, applying pressure to the wafer by using a roller which rotates uniformly to separate the chips from each other.
In a further improvement, the region of the test and monitor pattern structure in step one is a region having a length and width equal to one or more chip areas; the forming method comprises the following steps: when the mask is designed, the test and monitoring graph structure area is separated from the chip area on the mask through a shading band; in the exposure, the chip area and the test and monitoring graph structure area are respectively exposed to realize the exposure; the width of the separation grooves between all chips is 2-20 microns. Or, the test and monitor pattern structure in the step one is placed in the separation grooves between part of the chips and the chips in the same exposure field, and the widths of the other separation grooves in which the test and monitor pattern structure is not placed are 2-20 micrometers. Or, the test and monitor pattern structure in the step one is placed outside the outermost chip of the same exposure field or outside the outermost chip of the adjacent exposure field, and the width of the other separation grooves in which the test and monitor pattern structure is not placed is 2-20 micrometers. Or, the test and monitor pattern structure in the first step is placed in the same exposure field in the area equal to the area of one or more chips, and the width of the separation grooves between all chips is 2-20 microns.
In a further improvement, the width of each photoresist trench in the third step is 1 to 10 microns.
In a further improvement, the dielectric film in the fourth step is an oxide film, a combination of an oxide film and a nitride film, a combination of an oxide film and an oxynitride film, or a combination of an oxide film, an oxynitride film and a nitride film.
The further improvement is that the etched thickness of the substrate of the wafer in the fifth step is 20-200 microns.
The further improvement is that the thickness of the substrate of the wafer ground in the sixth step is 50-300 microns.
The further improvement is that the pattern structure of the separation groove etching mask plate in the second step meets the condition that the grooves between each chip and the adjacent chip of the formed groove pattern are completely connected together or a partition area without the grooves, with the length of 1-10 microns, is formed between each chip and the adjacent chip.
The invention can reduce the width of the separation groove between the chips and reduce the width of the separation groove between the chips to be less than 20 microns by arranging the positions of the plurality of test and monitoring pattern structures formed on the wafer. According to the invention, the mask is etched by adopting the separation groove, a groove pattern can be formed in the separation groove, and the chip can be separated by an etching method, so that the problem that the product quality is influenced because a scribing technology of a blade is adopted in the prior art is solved, and the cutting stability and the chip reliability can be improved.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIG. 1 is a schematic diagram of a prior art distribution of chips on a wafer;
FIG. 2 is a flow chart of an embodiment of the present invention;
FIG. 3 is a schematic diagram of a first distribution of chips on a wafer according to an embodiment of the present invention;
FIG. 4 is a schematic view of a second distribution of chips on a wafer according to an embodiment of the present invention;
FIG. 5 is a third schematic view of a wafer across which embodiments of the present invention are distributed;
FIG. 6 is a fourth exemplary distribution on a wafer according to an embodiment of the present invention;
FIGS. 7A-7D are cross-sectional views of a wafer during detachment according to an embodiment of the present invention;
FIG. 8A is a schematic diagram of a first structure of a separation trench etching mask according to an embodiment of the present invention;
fig. 8B is a schematic diagram of a second structure of the separation trench etching mask according to the embodiment of the present invention.
Detailed Description
As shown in fig. 2, the chip and the chip separation method according to the embodiment of the present invention include the following steps:
step one, forming a plurality of chips 2 and a plurality of test and monitor pattern structures 3A on a wafer, wherein separation grooves are formed among the chips 2, the chips 2 are mutually isolated through the separation grooves, and the width of the separation grooves between each chip 2 and the adjacent chip 2 is smaller than 20 microns in at least one direction.
The formation positions of the plurality of test and monitor pattern structures 3A on the wafer include the following structures:
as shown in fig. 3, the region of the test and monitor pattern structure 3A is a region having a length and a width equal to one or more chip areas; the forming method comprises the following steps: when the mask is designed, the area of the test and monitoring graph structure 3A is separated from the area of the chip 2 on the mask through a shading band; in the exposure, the chip 2 area and the test and monitoring graph structure 3A area are respectively exposed to realize the exposure; the width of the separation grooves 4A, 4B, 4C, and 4D between all chips is 1 to 20 micrometers.
As shown in fig. 4, the test and monitor pattern structure 3A is placed in the separation grooves 4B1 between a part of the chip 2 and the chip 2 in the same exposure field 1, and the widths of the other separation grooves 4A, 4B, 4C, and 4D in which the test and monitor pattern structure 3A is not placed are 1 to 20 μm. The width of the separation groove 4B1 is larger than the test and monitor pattern structure 3A and is determined by the width of the test and monitor pattern structure 3A. The direction of the separation grooves 4B1 in which the test and monitor pattern structure 3A is placed is one direction and along the Y-axis, the separation grooves 4B1 may also be one direction and along the X-axis, and the number of the separation grooves 4B1 in the direction thereof is 1 or as many as possible; the number of the separation grooves 4B1 may be plural along the direction parallel to the X axis and also parallel to the Y axis, and the number of the separation grooves 4B1 in each direction is 1 or as few as possible.
As shown in fig. 5, the test and monitor pattern structure 3A is placed in the separation grooves 4C1 outside the outermost chip 2 of the same exposure field 1 or in the separation grooves 4C1 outside the outermost chip 2 of the adjacent exposure field 1, and the widths of the other separation grooves 4A, 4B4, C, and 4D in which the test and monitor pattern structure 3A is not placed are 1 to 20 micrometers. The width of the separation groove 4C1 is larger than the test and monitor pattern structure 3A and is determined by the width of the test and monitor pattern structure 3A. In fig. 5, the direction of the separation groove 4C1 is one direction and is along the Y axis, the direction of the separation groove 4C1 is also one direction and is along the X axis, and the number of the separation grooves 4C1 in the direction thereof is 1 or 2; the separation grooves 4C1 may be a plurality of separation grooves 4C1 in each direction, which are parallel to the X axis and the Y axis, respectively, and the number of the separation grooves 4C1 is 1 or 2.
As shown in fig. 6, the test and monitor pattern structure 3A is placed in the same exposure field 1 in an area equal to the area of one or more of the chips 2, and the width of the separation grooves 4A, 4B, 4C, and 4D between all the chips 2 and the chips 2 is 1 to 20 μm.
As shown in fig. 7A, a cross-sectional view of the wafer after the chip 2 and the test and monitor pattern structure 3A and the separation grooves are formed according to the embodiment of the present invention. A well is formed on the P-type substrate of the wafer, active devices are formed in the well, the active devices are MOS tubes and comprise a grid electrode 721 and a source drain region, and the active devices are isolated by field oxide 723. Passive devices such as resistors, capacitors, inductors, and the like (not shown) are formed on the substrate; shield rings 731A, 731B are provided on the outermost periphery of the chip 2. Multiple metal layers, such as a first metal layer 724 and a topmost metal layer 727, are formed on the device; and multiple dielectric layers, such as dielectric layer 722 between the device and the first metal layer 724, dielectric layer 725 between the metal layers, and dielectric layers 728 and 729 on the topmost metal 727, wherein the dielectric layer 728 is HDP-SiO2 or PECVDSiO2, and the dielectric layer 729 is P-SiON or SiN.
And step two, forming a separation groove etching mask plate for forming groove patterns in the separation grooves among the chips, wherein the pattern structure of the separation groove etching mask plate meets the condition that the formed groove patterns are the same as the pattern structure of the separation grooves among the chips, and the width of each groove pattern is smaller than the width of the corresponding separation groove. As shown in fig. 8A, the pattern structure of the separation groove etching mask is such that the trenches between each chip and the adjacent chip of the trench pattern formed are completely connected, i.e. the pattern grooves 841 and 842 of the pattern structure of the separation groove etching mask are connected or connected together; or, as shown in fig. 8B, the pattern structure of the separation groove etching mask is such that a partition region with a length of 1 micron to 10 microns is formed between each chip of the formed groove pattern and the groove between adjacent chips, that is, the pattern grooves 841 and 842 of the pattern structure of the separation groove etching mask are not connected, and two ends of the pattern grooves 841 and 842 between adjacent chips are provided with partition regions 843 with a length of 1 micron to 10 microns.
And step three, as shown in fig. 7A, forming a photoetching pattern on the wafer by using the separation groove etching mask plate, wherein the photoetching pattern is composed of photoresist grooves etched by photoresist 740, the photoresist grooves are formed above the separation grooves, and the width of each photoresist groove is 1-10 micrometers. The outer regions of the photoresist trenches are covered and protected by photoresist 740.
And step four, as shown in fig. 7B, the photoresist 740 is used as a mask, and a dry etching process or a wet etching process is adopted to etch away the dielectric film or the dielectric film and the metal film below the photoresist trench. The dielectric film is an oxide film, a combination of an oxide film and a nitride film, a combination of an oxide film and an oxynitride film, or a combination of an oxide film, an oxynitride film and a nitride film.
Step five, as shown in fig. 7C, the photoresist 740 is used as a mask, a dry etching process or a wet and dry etching process is used to etch the substrate of the wafer to a thickness of 20 to 200 micrometers, and finally the trench pattern is formed on the wafer below the photoresist trench. Corresponding to the separation groove etching mask shown in fig. 8A and 8B, the grooves of the groove patterns are respectively communicated or isolated regions without grooves, which are 1 to 10 micrometers long, are formed between the grooves of adjacent chips.
And sixthly, as shown in FIG. 7D, protecting the front side of the wafer, and thinning the wafer to the thickness of 50-300 microns by grinding the back side of the wafer. This thickness ensures that the grooves of the groove pattern formed on the front surface of the wafer are not exposed and that there is no separation between the chips 2.
And step seven, applying pressure to the wafer by using a roller which rotates uniformly to separate the chips 2 from each other.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.

Claims (10)

1. A chip and chip separation method is characterized by comprising the following steps:
forming a plurality of chips and a plurality of test and monitor pattern structures on a wafer, wherein a separation groove is formed between the chips, the chips are mutually isolated through the separation groove, and the width of the separation groove between each chip and an adjacent chip is smaller than 20 microns in at least one direction;
step two, forming a separation groove etching mask plate for forming groove patterns in the separation grooves among the chips, wherein the pattern structure of the separation groove etching mask plate meets the condition that the formed groove patterns are the same as the pattern structure of the separation grooves among the chips, and the width of each groove pattern is smaller than the width of the corresponding separation groove;
forming a photoetching pattern on the wafer by using the separating groove etching mask plate, wherein the photoetching pattern is composed of photoresist grooves etched by photoresist, the photoresist grooves are formed above the separating grooves, and the outer areas of the photoresist grooves are covered and protected by the photoresist;
etching the dielectric film or the dielectric film and the metal film below the photoresist groove by using the photoresist as a mask and adopting a dry etching process or a wet etching process;
etching part of the thickness of the substrate of the wafer by using the photoresist as a mask and using a dry etching process or a wet and dry etching process, and finally forming a groove pattern on the wafer below the photoresist groove;
sixthly, protecting the front side of the wafer, and thinning the wafer to a required thickness by grinding the back side of the wafer, wherein the thickness ensures that all grooves of the groove pattern formed on the front side of the wafer are not exposed and the chips are not separated;
and step seven, applying pressure to the wafer by using a roller which rotates uniformly to separate the chips from each other.
2. The chip and the method for separating chips according to claim 1, wherein: the area of the test and monitor graph structure in the first step is an area with the length and the width equal to the area of one or more chips; the forming method comprises the following steps: when the mask is designed, the test and monitoring graph structure area is separated from the chip area on the mask through a shading band; in the exposure, the chip area and the test and monitoring graph structure area are respectively exposed to realize the exposure; the width of the separation grooves between all chips is 2-20 microns.
3. The chip and the method for separating chips according to claim 1, wherein: the test and monitoring graph structure in the step one is placed in the separation grooves between partial chips in the same exposure field, and the widths of other separation grooves in which the test and monitoring graph structure is not placed are 2-20 micrometers.
4. The chip and the method for separating chips according to claim 1, wherein: the test and monitoring graph structure in the step one is placed in the separation groove outside the outermost chip of the same exposure field or the separation groove outside the outermost chip of the adjacent exposure field, and the widths of the other separation grooves not provided with the test and monitoring graph structure are 2-20 micrometers.
5. The chip and the method for separating chips according to claim 1, wherein: the test and monitoring graph structure in the step one is placed in the region, with the same area as one or more chips, of the same exposure field, and the width of the separation grooves between all the chips is 2-20 micrometers.
6. The chip and the method for separating chips according to claim 1, wherein: and in the third step, the width of each photoresist groove is 1-10 micrometers.
The chip and the method for separating chips according to claim 1, wherein: the dielectric film in the fourth step is an oxide film, a combination of an oxide film and a nitride film, a combination of an oxide film and an oxynitride film, or a combination of an oxide film, an oxynitride film, and a nitride film.
7. The chip and the method for separating chips according to claim 1, wherein: and the etched thickness of the substrate of the wafer in the step five is 20-200 microns.
8. The chip and the method for separating chips according to claim 1, wherein: and the thickness of the substrate of the wafer ground in the sixth step is 50-300 microns.
9. The chip and the method for separating chips according to claim 1, wherein: in the second step, the pattern structure of the separation groove etching mask meets the condition that the grooves between each chip and the adjacent chips of the formed groove pattern are completely connected together, or a partition area without the grooves with the length of 1-10 microns is formed between each chip and the grooves between the adjacent chips. The chip and the method for separating chips according to claim 1, wherein: and the etched thickness of the substrate of the wafer in the step five is 20-200 microns.
10. The chip and the method for separating chips according to claim 1, wherein: and the thickness of the substrate of the wafer ground in the sixth step is 50-300 microns.
The chip and the method for separating chips according to claim 1, wherein: in the second step, the pattern structure of the separation groove etching mask meets the condition that the grooves between each chip and the adjacent chips of the formed groove pattern are completely connected together, or a partition area without the grooves with the length of 1-10 microns is formed between each chip and the grooves between the adjacent chips.
CN201911288565.3A 2019-12-12 2019-12-12 Chip and chip separation method Withdrawn CN112992781A (en)

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CN201911288565.3A CN112992781A (en) 2019-12-12 2019-12-12 Chip and chip separation method

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Application Number Priority Date Filing Date Title
CN201911288565.3A CN112992781A (en) 2019-12-12 2019-12-12 Chip and chip separation method

Publications (1)

Publication Number Publication Date
CN112992781A true CN112992781A (en) 2021-06-18

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