CN112992696A - Packaging method and packaging structure of stacked chips - Google Patents

Packaging method and packaging structure of stacked chips Download PDF

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Publication number
CN112992696A
CN112992696A CN202110489628.2A CN202110489628A CN112992696A CN 112992696 A CN112992696 A CN 112992696A CN 202110489628 A CN202110489628 A CN 202110489628A CN 112992696 A CN112992696 A CN 112992696A
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chip
layer
dielectric layer
functional surface
conductive
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蔡钟贤
吴品忠
朱锴越
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Nantong Fujitsu Microelectronics Co Ltd
Tongfu Microelectronics Co Ltd
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Nantong Fujitsu Microelectronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H01L2224/214—Connecting portions
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting

Abstract

The application discloses a packaging method and a packaging structure of stacked chips, wherein the packaging method comprises the following steps: sticking the functional surface of at least one first chip to the carrier plate provided with the adhesive layer; respectively pasting part of functional surfaces of at least one second chip on the non-functional surfaces of at least one first chip, wherein the second chip comprises an end part of the first chip exceeding the corresponding position, a conductive column is arranged on the functional surface of the end part, and the conductive column is inserted into the adhesive layer; forming a plastic packaging layer on one side of the adhesive layer, which is provided with the first chip and the second chip; and removing the adhesive layer and the carrier plate, wherein the functional surface of the first chip and the conductive column are exposed out of the plastic packaging layer. Through the mode, the height of the packaging structure of the stacked chips can be reduced.

Description

Packaging method and packaging structure of stacked chips
Technical Field
The application belongs to the technical field of semiconductors, and particularly relates to a packaging method and a packaging structure of stacked chips.
Background
The trend of consumer electronics (e.g., mobile phones, tablet computers, etc.) is to be thinner and lighter, which has led to the trend of semiconductor devices in consumer electronics to be thinner and lighter. In handheld electronic products, especially mobile phones, a PoP (package on package) structure is the mainstream package format. In PoP, the bottom layer is the processor package and the upper layer is the memory package. At present, the capacity of electronic products for storage is more and more required, and the capacity of mobile phone DRAM (dynamic random access memory) application reaches 12GB at most. Due to the limited capacity of a single chip, a multi-chip stack package is required for large-capacity storage.
Referring to fig. 1, fig. 1 is a schematic structural diagram of an embodiment of a package structure of stacked chips in the prior art, in which a non-functional surface 110 of a first chip 11 is adhered to a substrate 16 through a film 13, and a functional surface 112 of the first chip 11 and a non-functional surface 120 of a second chip 12 are adhered and fixed together through the film 13. The pads on the functional surface 112 of the first chip 11 and the functional surface 122 of the second chip 12 are electrically connected to the substrate 16 by gold wires. The first chip 11, the second chip 12 and the gold wires are protected by a molding layer 17. The entire package structure is connected to the outside by solder balls 18 on the substrate 16.
In the current package structure, due to the height limitation of gold wire molding and the limitation of the protection distance from the plastic package layer to the gold wire, the height from the plastic package layer to the surface of the second chip is strictly limited, and the height cannot be continuously reduced. Meanwhile, due to the limitation of materials and the limitation of substrate strength in the substrate process, the production difficulty of the ultrathin substrate is very high, and the application of the traditional packaging structure in the ultrathin storage laminated packaging is limited.
Disclosure of Invention
The application provides a packaging method and a packaging structure of stacked chips, which aim to solve the technical problem that the height of the packaging structure of the stacked chips cannot be further reduced.
In order to solve the technical problem, the application adopts a technical scheme that: a packaging method of stacked chips is provided, which comprises the following steps: sticking the functional surface of at least one first chip to the carrier plate provided with the adhesive layer; respectively pasting part of functional surfaces of at least one second chip on the non-functional surfaces of at least one first chip, wherein the second chip comprises an end part of the first chip exceeding the corresponding position, a conductive column is arranged on the functional surface of the end part, and the conductive column is inserted into the adhesive layer; forming a plastic packaging layer on one side of the adhesive layer, which is provided with the first chip and the second chip; and removing the adhesive layer and the carrier plate, wherein the functional surface of the first chip and the conductive column are exposed out of the plastic packaging layer.
Wherein the conductive posts are inserted 5-10 microns into the glue layer.
Wherein, after removing glue film and carrier plate, still include: forming a first dielectric layer on one side of the functional surface of the first chip, wherein the first dielectric layer covers all the functional surfaces of the first chip and all the conductive columns; removing part of the first dielectric layer to expose the pads on the functional surface of the first chip and all the conductive posts from the first dielectric layer; and forming at least one re-wiring layer on the first dielectric layer, wherein the re-wiring layer is electrically connected with the bonding pad of the first chip at the corresponding position and the conductive column.
Wherein the step of removing a portion of the first dielectric layer to expose the pads on the functional surface of the first chip and all the conductive pillars from the first dielectric layer includes: grinding the first dielectric layer until the conductive posts are flush with the first dielectric layer, wherein the conductive posts are exposed out of the first dielectric layer; and forming a first opening at the position of the first dielectric layer corresponding to the bonding pad of the first chip, so that the bonding pad of the first chip is exposed out of the first opening.
Wherein the step of forming at least one re-wiring layer on the first dielectric layer comprises: forming a first redistribution layer on the first dielectric layer, the first redistribution layer being electrically connected to the pads of the first chip and the conductive pillars at corresponding locations; forming a second dielectric layer on the first rewiring layer, wherein a second opening is formed in the second dielectric layer at a position corresponding to the first rewiring layer; and forming a second rewiring layer on the second dielectric layer, wherein the second rewiring layer is electrically connected with the first rewiring layer through the second opening.
Wherein, after the step of forming at least one re-wiring layer on the first dielectric layer, the method further comprises: forming a third dielectric layer on the at least one rewiring layer, wherein a third opening is formed in the third dielectric layer at a position which is farthest away from the rewiring layer of the first chip; and arranging a solder ball in the third opening.
Wherein, the number of the first chips is a plurality, and after the step of arranging the solder balls in the third opening, the method further comprises the following steps: and cutting off the plastic packaging layer and all the dielectric layers between the adjacent first chips to obtain the packaging structure containing the single first chip.
In order to solve the above technical problem, another technical solution adopted by the present application is: there is provided a stacked chip package structure formed by the packaging method described in any of the above embodiments, including: the chip comprises a first chip and a second chip which are stacked, wherein part of functional surfaces of the second chip and non-functional surfaces of the first chip are adhered and fixed with each other, the second chip comprises an end part which exceeds the first chip, a conductive column is arranged on the functional surface of the end part, and the conductive column extends towards the direction of the first chip and exceeds the functional surface of the first chip; and the plastic packaging layer covers the first chip and the second chip, and the first surface of the plastic packaging layer, which is close to the functional surface of the first chip, is flush with the functional surface of the first chip.
Wherein, the conductive column exceeds the plastic packaging layer by 5-10 microns.
Wherein, still include: the first dielectric layer covers the first surface and part of the functional surface of the first chip, and the bonding pads and the conductive columns on the functional surface of the first chip are exposed out of the first dielectric layer; and the at least one rewiring layer is positioned on the first dielectric layer and is electrically connected with the bonding pad and the conductive post at the corresponding position.
Being different from the prior art situation, the beneficial effect of this application is: according to the packaging method, the first chip and the second chip which are stacked mutually are arranged in a staggered mode, the bonding pad on the functional surface of the first chip below and the conductive post on the functional surface of the second chip above are exposed out of the plastic package layer, and signal leading-out of the bonding pad of the first chip and the conductive post of the second chip is facilitated subsequently; the packaging method provided by the application cancels the mode of utilizing a gold wire to lead out signals, can reduce the thickness of the plastic packaging layer and further achieves the purpose of reducing the thickness of the packaging structure of the stacked chips.
In addition, the substrate is omitted in the method, and the subsequent rewiring fan-out process is directly carried out on the surfaces of the exposed conductive columns and the exposed bonding pads, so that the thickness of the packaging structure of the stacked chip can be further reduced, the use of a TSV (through silicon Via) technology is avoided, and the cost is reduced.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without inventive efforts, wherein:
FIG. 1 is a diagram illustrating a package structure of stacked chips according to an embodiment of the prior art;
FIG. 2 is a flowchart illustrating an embodiment of a method for packaging stacked chips according to the present disclosure;
FIG. 3a is a schematic structural diagram of an embodiment corresponding to step S101 in FIG. 2;
FIG. 3b is a schematic structural diagram of an embodiment corresponding to step S102 in FIG. 2;
FIG. 3c is a schematic structural diagram of an embodiment corresponding to step S103 in FIG. 2;
FIG. 3d is a schematic structural diagram of an embodiment corresponding to step S104 in FIG. 2;
FIG. 4 is a flowchart illustrating an embodiment of a method for packaging stacked chips after step S104 in FIG. 2;
FIG. 5a is a schematic structural diagram of an embodiment corresponding to step S105 in FIG. 4;
FIG. 5b is a schematic structural diagram of an embodiment corresponding to step S106 in FIG. 4;
FIG. 5c is a schematic structural diagram of an embodiment corresponding to step S107 in FIG. 4;
FIG. 6 is a schematic structural diagram of an embodiment after step S107 in FIG. 4;
fig. 7 is a schematic structural diagram of an embodiment of a package structure for stacked chips according to the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 2, fig. 2 is a schematic flow chart illustrating an embodiment of a packaging method for stacked chips according to the present application, the packaging method specifically includes:
s101: the functional surface 200 of at least one first chip 20 is attached to the carrier 24 provided with the adhesive layer 22.
Specifically, please refer to fig. 3a, wherein fig. 3a is a schematic structural diagram of an embodiment corresponding to step S101 in fig. 2. In this embodiment, the material of the carrier 24 may be glass, silicon, or metal. The glue layer 22 provided on the carrier plate 24 may be a temporary bonding glue, which may be subsequently removed in some manner. The first chip 20 may include a functional side 200 and a non-functional side 202 opposite to each other, and a plurality of bonding pads (not shown) are disposed on the functional side 200 of the first chip 20.
S102: the partial functional surfaces 260 of the at least one second chip 26 are respectively adhered to the non-functional surface 202 of the at least one first chip 20, and the second chip 26 includes end portions 264 of the first chip 20 beyond the corresponding positions, the functional surfaces 260 of the end portions 264 are provided with conductive pillars 266, and the conductive pillars 266 are inserted into the adhesive layer 22.
Specifically, please refer to fig. 3b, wherein fig. 3b is a schematic structural diagram of an embodiment corresponding to step S102 in fig. 2. In the present embodiment, the second chip 26 is similar to the first chip 20, the second chip 26 includes a functional surface 260 and a non-functional surface 262, which are opposite to each other, and a plurality of bonding pads (not shown) are disposed on the functional surface 260 of the second chip 26. By pre-design, the plurality of pads of the second chip 26 may be arranged at only one of the end portions 264; before the step S102, the method may further include: conductive posts 266 are formed on the pads of the end portion 264 of the second chip 26 by electroplating, and the conductive posts 266 may be made of copper or the like and have a height greater than that of the first chip 20. Subsequently, in step S102, the functional surface 260 of the second chip 26 may be disposed toward the first chip 20, and the second chip 26 and the first chip 20 are stacked with a mutual offset therebetween, so that the first chip 20 avoids the conductive posts 266. Further, the conductive posts 266 may be inserted into the adhesive layer 22 at corresponding positions, but not in contact with the carrier plate 24; and the conductive posts 266 extend a depth D in the glue layer 22 of 5-10 microns; e.g., 6 microns, 8 microns, etc. This design allows the conductive post 266 to be easily exposed from the first dielectric layer for subsequent electrical connection.
In addition, the second chip 26 and the first chip 20 can be bonded and fixed by a bonding film 28; to simplify the process, the adhesive film 28 may be disposed on the non-functional surface 202 of the first chip 20, and then the functional surface 260 of the second chip 26 is adhered to the adhesive film 28.
S103: the molding layer 21 is formed on the side of the adhesive layer 22 where the first chip 20 and the second chip 26 are disposed.
Specifically, please refer to fig. 3c, wherein fig. 3c is a schematic structural diagram of an embodiment corresponding to step S103 in fig. 2. In this embodiment, the molding compound layer 21 may be made of epoxy resin or the like, and one side surface thereof is flush with the adhesive layer 22, and the molding compound layer 21 may cover the first chip 20 and the second chip 26. When the plurality of first chips 20 are disposed on the carrier 24, the molding compound layer 21 may continuously cover the plurality of first chips 20 and the plurality of second chips 26, and a side surface of the molding compound layer 21 facing away from the adhesive layer 22 is flush.
S104: the adhesive layer 22 and the carrier board 24 are removed, and the functional surface 200 of the first chip 20 and the conductive posts 266 are exposed from the molding layer 21.
Specifically, please refer to fig. 3d, where fig. 3d is a schematic structural diagram of an embodiment corresponding to step S104 in fig. 2. In this embodiment, the adhesive layer 22 and the carrier plate 24 in fig. 3c may be removed by thermal separation, laser separation, ultraviolet light separation, mechanical separation, or the like. After the adhesive layer 22 and the carrier board 24 are removed, it can be seen that a side surface of the molding compound layer 21 close to the functional surface 200 of the first chip 20 is flush with the functional surface 200 of the first chip 20, and the conductive pillars 266 exceed the functional surface 200 of the first chip 20 by a distance D equal to the depth D that the conductive pillars 266 extend in the adhesive layer 22 in step S102.
In the above design manner, in the packaging method provided by the present application, the first chip 20 and the second chip 26 stacked on each other are disposed in a staggered manner, and the pads on the functional surface 200 of the first chip 20 located below and the conductive posts 266 on the functional surface 260 of the second chip 26 located above are both exposed from the mold layer 21, so that signal extraction can be performed on the pads of the first chip 20 and the conductive posts 266 of the second chip 26 in the following process; the packaging method provided by the application cancels the signal extraction mode by using a gold wire, can reduce the thickness of the plastic packaging layer 21, and further achieves the purpose of reducing the thickness of the packaging structure of the stacked chips.
Of course, in other embodiments, a subsequent packaging process may be further performed after the step S104; for example, referring to fig. 4, fig. 4 is a flowchart illustrating an embodiment of a packaging method for stacked chips after step S104 in fig. 2, where step S104 further includes:
s105: the first dielectric layer 23 is formed on the functional surface 200 side of the first chip 20, and the first dielectric layer 23 covers all the functional surfaces 200 of the first chip 20 and all the conductive posts 266.
Specifically, referring to fig. 5a, fig. 5a is a schematic structural diagram of an embodiment corresponding to step S105 in fig. 4.
S106: a portion of the first dielectric layer 23 is removed so that the pads on the functional side 200 of the first chip 20 and all the conductive posts 266 are exposed from the first dielectric layer 23.
Specifically, please refer to fig. 5b, wherein fig. 5b is a schematic structural diagram of an embodiment corresponding to step S106 in fig. 4. In this embodiment, as shown in fig. 5b, the implementation process of the step S106 may be: grinding the first dielectric layer 23 until the conductive posts 266 are flush with the first dielectric layer 23, the conductive posts 266 being exposed from the first dielectric layer 23; forming a first opening 230 at a position of the ground first dielectric layer 23 corresponding to a pad (not shown) on the functional surface 200 of the first chip 20, so that the pad of the first chip 20 is exposed from the first opening 230; the process of forming the first opening 230 may be photolithography etching or the like. The implementation process of step S106 is simple, and the thickness of the first dielectric layer 23 can be well controlled, and the thickness of the first dielectric layer 23 is low.
Of course, in other embodiments, the manner of implementing the step S106 may be other, for example, the first dielectric layer 23 is not ground, and openings are directly formed at positions of the first dielectric layer 23 corresponding to the conductive posts 266 and the pads of the first chip 20, respectively. It is foreseen that this implementation will eventually result in a first dielectric layer 23 having a greater thickness than the former and is therefore more preferred.
S107: at least one re-wiring layer 25 is formed on the first dielectric layer 23, and the re-wiring layer 25 is electrically connected to the pads of the first chip 20 and the conductive posts 266 at the corresponding positions.
Specifically, please refer to fig. 5c, wherein fig. 5c is a schematic structural diagram of an embodiment corresponding to step S107 in fig. 4. When the redistribution layer 25 includes two layers, the specific implementation process of step S107 may be: forming a first redistribution layer 250 on the first dielectric layer 23, the first redistribution layer 250 being electrically connected to the pads (not shown) of the first chip 20 and the conductive pillars 266 at corresponding positions; forming a second dielectric layer 27 on the first redistribution layer 250, wherein a second opening (not shown) is formed in a position of the second dielectric layer 27 corresponding to the first redistribution layer 250; a second re-wiring layer 252 is formed on the second dielectric layer 27, and the second re-wiring layer 252 is electrically connected to the first re-wiring layer 250 through the second opening. Of course, in other embodiments, the redistribution layer 25 may also include one or more layers, which is not limited in this application.
In the above design manner, in comparison with the prior art, the substrate is omitted, and the rewiring fan-out process is directly performed on the exposed surfaces of the conductive posts 266 and the bonding pads, so that the thickness of the package structure of the stacked chip can be further reduced, the use of a TSV (through silicon via) technology is avoided, and the cost is reduced.
In addition, in other embodiments, please refer to fig. 6, and fig. 6 is a schematic structural diagram of an embodiment after step S107 in fig. 4. The step S107 may further include: forming a third dielectric layer 29 on the at least one redistribution layer 25, wherein a third opening (not shown) is formed in a position of the third dielectric layer 29, which is farthest from the redistribution layer 25 of the first chip 20; a solder ball 30 is disposed in the third opening. The package structure can be electrically connected to other external devices through the solder balls 30.
Optionally, referring to fig. 6 and 7 together, fig. 7 is a schematic structural diagram of an embodiment of a package structure of stacked chips according to the present application. When the number of the first chips 20 is plural, after the step of disposing the solder balls 30 in the third openings, the method further includes: the molding layer 21 and all dielectric layers between adjacent first chips 20 are cut off to obtain a package structure containing a single first chip 20.
The package structure of stacked chips formed by the above-mentioned packaging method is further explained from the structural point of view. Referring to fig. 7 again, the package structure of stacked chips provided in the present application specifically includes: the first chip 20 and the second chip 26 are stacked, and a part of the functional surface 260 of the second chip 26 and the non-functional surface 202 of the first chip 20 are adhered and fixed to each other, the second chip 26 includes an end portion 264 beyond the first chip 20, a pad is disposed on the functional surface 260 of the end portion 264, and a conductive pillar 266 is disposed at a position corresponding to each pad, and the conductive pillar 266 extends toward the first chip 20 and beyond the functional surface 200 of the first chip 20.
The molding compound layer 21 covers the first chip 20 and the second chip 26, and the first surface 210 of the molding compound layer close to the functional surface 200 of the first chip 20 is flush with the functional surface 200 of the first chip 20. The conductive posts 266 can be said to extend beyond the first surface 210 of the molding layer 21, and optionally extend a distance of 5-10 microns.
In addition, with reference to fig. 7, the package structure of stacked chips provided by the present application further includes a first dielectric layer 23 and at least one redistribution layer 25. The first dielectric layer 23 covers the first surface 210 of the molding compound layer 21 and a part of the functional surface 200 of the first chip 20, and the pads and the conductive posts 266 on the functional surface 200 of the first chip 20 are exposed from the first dielectric layer 23. At least one re-routing layer 25 is located on the first dielectric layer 23 and electrically connected to the pads and conductive posts 266 at corresponding locations.
Optionally, in this embodiment, two redistribution layers 25 may be disposed on the first dielectric layer 23, specifically: the first redistribution layer 250 is located on the first dielectric layer 23 and electrically connected to the pads and the conductive pillars 266 at corresponding positions; the second dielectric layer 27 covers the first redistribution layer 250, and a second opening is formed at a position corresponding to the first redistribution layer 250; the second redistribution layer 252 is disposed on the second dielectric layer 27 and electrically connected to the first redistribution layer 250 at the corresponding position through the second opening.
In addition, with reference to fig. 7, the package structure of stacked chips provided by the present application may further include: a third dielectric layer 29 on the second redistribution layer 252, and a third opening (not shown) is formed at a position corresponding to the second redistribution layer 252; and the solder ball 30 is positioned in the third opening.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings, or which are directly or indirectly applied to other related technical fields, are intended to be included within the scope of the present application.

Claims (8)

1. A method of packaging stacked chips, comprising:
sticking the functional surface of at least one first chip to the carrier plate provided with the adhesive layer;
respectively pasting part of functional surfaces of at least one second chip on the non-functional surfaces of at least one first chip, wherein the second chip comprises end parts of the first chip exceeding corresponding positions, conductive columns are arranged on the functional surfaces of the end parts, and the conductive columns are inserted into the adhesive layers by 5-10 microns;
forming a plastic packaging layer on one side of the adhesive layer, which is provided with the first chip and the second chip;
and removing the adhesive layer and the carrier plate, wherein the functional surface of the first chip and the conductive column are exposed out of the plastic packaging layer.
2. The method for encapsulating according to claim 1, wherein after the removing the glue layer and the carrier, further comprising:
forming a first dielectric layer on one side of the functional surface of the first chip, wherein the first dielectric layer covers all the functional surfaces of the first chip and all the conductive columns;
removing part of the first dielectric layer to expose the pads on the functional surface of the first chip and all the conductive posts from the first dielectric layer;
and forming at least one re-wiring layer on the first dielectric layer, wherein the re-wiring layer is electrically connected with the bonding pad of the first chip at the corresponding position and the conductive column.
3. The packaging method according to claim 2, wherein the step of removing a portion of the first dielectric layer to expose the pads on the functional surface of the first chip and all the conductive pillars from the first dielectric layer comprises:
grinding the first dielectric layer until the conductive posts are flush with the first dielectric layer, wherein the conductive posts are exposed out of the first dielectric layer;
and forming a first opening at the position of the first dielectric layer corresponding to the bonding pad of the first chip, so that the bonding pad of the first chip is exposed out of the first opening.
4. The packaging method of claim 2, wherein the step of forming at least one re-routing layer on the first dielectric layer comprises:
forming a first redistribution layer on the first dielectric layer, the first redistribution layer being electrically connected to the pads of the first chip and the conductive pillars at corresponding locations;
forming a second dielectric layer on the first rewiring layer, wherein a second opening is formed in the second dielectric layer at a position corresponding to the first rewiring layer;
and forming a second rewiring layer on the second dielectric layer, wherein the second rewiring layer is electrically connected with the first rewiring layer through the second opening.
5. The method of packaging of claim 2, wherein the step of forming at least one rewiring layer on the first dielectric layer further comprises:
forming a third dielectric layer on the at least one rewiring layer, wherein a third opening is formed in the third dielectric layer at a position which is farthest away from the rewiring layer of the first chip;
and arranging a solder ball in the third opening.
6. The method of claim 5, wherein the number of the first chips is plural, and the step of disposing the solder balls in the third openings further comprises:
and cutting off the plastic packaging layer and all the dielectric layers between the adjacent first chips to obtain the packaging structure containing the single first chip.
7. A stacked chip package structure formed by the packaging method of any one of claims 1 to 6, comprising:
the chip comprises a first chip and a second chip which are stacked, wherein part of functional surfaces of the second chip and non-functional surfaces of the first chip are adhered and fixed with each other, the second chip comprises an end part which exceeds the first chip, a conductive column is arranged on the functional surface of the end part, and the conductive column extends towards the direction of the first chip and exceeds the functional surface of the first chip;
the plastic packaging layer covers the first chip and the second chip, and a first surface, close to the functional surface of the first chip, of the plastic packaging layer is flush with the functional surface of the first chip; the conductive posts exceed the plastic packaging layer by 5-10 microns.
8. The package structure of claim 7, further comprising:
the first dielectric layer covers the first surface and part of the functional surface of the first chip, and the bonding pads and the conductive columns on the functional surface of the first chip are exposed out of the first dielectric layer;
and the at least one rewiring layer is positioned on the first dielectric layer and is electrically connected with the bonding pad and the conductive post at the corresponding position.
CN202110489628.2A 2021-05-06 2021-05-06 Packaging method and packaging structure of stacked chips Pending CN112992696A (en)

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Application publication date: 20210618