CN112953673A - Frequency scale signal remote recovery method and device and frequency scale signal remote transmission method - Google Patents

Abstract

The application relates to a method and a device for remotely recovering a frequency scale signal and a method for remotely transmitting the frequency scale signal. The frequency scale signal remote recovery method comprises the following steps: PTP synchronization is carried out with the frequency scale signal transmission equipment, and a clock control signal is output to a clock of the equipment based on the result of the PTP synchronization; the clock control signal is used for taming the clock of the equipment until the taming local clock signal and the main clock signal of the frequency standard signal transmission equipment have the same frequency and phase; acquiring a digital frequency scale signal and acquiring an initial frequency scale signal; the initial frequency scale signal is obtained by performing digital-to-analog conversion on a digital frequency scale signal by using a domesticated local clock signal; and acquiring data delay time of the digital frequency scale signal, and adjusting the phase of the initial frequency scale signal based on the data delay time to obtain a target frequency scale signal. According to the method and the device, a large amount of resources can be saved, frequency sharing is achieved, and the target frequency standard signal obtained through recovery can remotely follow the standard frequency standard signal of the frequency standard signal transmission equipment.

Description

Frequency scale signal remote recovery method and device and frequency scale signal remote transmission method

Technical Field

The present invention relates to the field of frequency synchronization technologies, and in particular, to a method and an apparatus for remotely recovering a frequency scale signal, and a method for remotely transmitting a frequency scale signal.

Background

The frequency signal is typically dominated by an analog signal, and the standard frequency signal is often dominated by a 10MHz/5MHz sine wave as a frequency scale signal, which may be, for example, an atomic clock output signal. Other time frequency signals are generated by taking the time frequency signals as a source, and in order to reduce the set number of atomic clocks and reduce the generation cost of frequency signals, frequency scale signals need to be transmitted so as to provide the frequency scale signals for each device.

For short-distance transmission, the conventional Time-frequency signal transmission is mainly realized by 1PPS (second signal) and TOD (Time of Day, Time information), wherein the rising edge of the 1PPS signal represents the precise Time of a second pulse, and the TOD signal represents the Time, minute and second information of a whole second or a year, month, Day and minute, and the two signals are combined to obtain a standard Time and Time signal.

In the long-distance transmission, since the analog signal is not suitable for the long-distance transmission, the analog signal needs to be converted into a digital signal before the long-distance transmission. The transmission of the digital signal has a delay, and the clock of the source end is inconsistent with that of the recovery end, which easily results in poor synchronization of the two ends. At present, a long-distance Time synchronization technology mainly depends on NTP (Network Time Protocol) and PTP (Precision Time Protocol) technologies, the technologies only achieve alignment of a local clock, and meanwhile, when Network delay is large, uncertain delay is also large due to the NTP or PTP technologies, so that errors are increased, and long-distance transmission standard frequency standard signals cannot be recovered.

Disclosure of Invention

In view of the foregoing, it is desirable to provide a method and an apparatus for remotely recovering a frequency standard signal, and a method for remotely transmitting a frequency standard signal, which can accurately recover a remotely transmitted frequency standard signal to achieve synchronization of the frequency standard signals at the transmitting and receiving ends.

In order to achieve the above object, an embodiment of the present application provides a method for remotely recovering a frequency scale signal, which uses a control unit of a device for remotely recovering a frequency scale signal as an execution main body, and includes the steps of:

PTP synchronization is carried out with the frequency scale signal transmission equipment, and a clock control signal is output to a clock of the equipment based on the result of the PTP synchronization; the clock control signal is used for taming the clock of the equipment until the taming local clock signal and the main clock signal of the frequency standard signal transmission equipment have the same frequency and phase;

acquiring a digital frequency scale signal and acquiring an initial frequency scale signal; the initial frequency scale signal is obtained by performing digital-to-analog conversion on a digital frequency scale signal by using a domesticated local clock signal;

and acquiring data delay time of the digital frequency scale signal, and adjusting the phase of the initial frequency scale signal based on the data delay time to obtain a target frequency scale signal.

In one embodiment, the step of adjusting the phase of the initial frequency scale signal based on the data delay time to obtain the target frequency scale signal includes:

measuring the period of an initial frequency scale signal, and obtaining data delay time through a domesticated local clock signal;

and calculating a phase delay amount according to the period and the data delay time, and adjusting the phase of the initial frequency scale signal according to the phase delay amount to obtain a target frequency scale signal.

In one embodiment, the step of calculating the phase delay amount based on the period and the data delay time comprises: and acquiring the ratio of the data delay time to the period, and determining the product of the ratio and the period angle as the phase delay amount.

In one embodiment, the step of outputting a clock control signal to a clock of the present device based on a result of the PTP synchronization includes:

respectively determining a main clock count value and a local device clock count value of the current synchronization period according to a PTP synchronization result, and processing the main clock count value and the local device clock count value to obtain a frequency division coefficient of the current synchronization period;

multiplying the frequency division coefficient of the current synchronization period by the frequency compensation value of the previous synchronization period, and confirming the multiplication result as the frequency compensation value of the current synchronization period;

and outputting a clock control signal corresponding to the current synchronization period to the clock of the equipment based on the frequency compensation value of the current synchronization period.

In one embodiment, the step of processing the master clock count value and the device clock count value to obtain the frequency division coefficient of the current synchronization period includes:

confirming the difference value between the main clock count value and the clock count value of the equipment as clock deviation;

and filtering the clock deviation by adopting a one-dimensional Kalman filtering algorithm to obtain the filtered clock deviation, acquiring a sum of the filtered clock deviation and a main clock counting value, and determining a quotient of the sum and the main clock counting value as a frequency division coefficient of a synchronization period.

In one embodiment, the step of outputting the clock control signal corresponding to the current synchronization period to the clock of the present device based on the frequency compensation value of the current synchronization period includes:

and processing the frequency compensation value of the current synchronization period by adopting a PID algorithm to obtain and output a clock control signal corresponding to the current synchronization period.

In one embodiment, the data delay time is an average path delay between the frequency scale signal transmission device and the local device; the digital frequency scale signal is received by the equipment through the gigabit network.

The embodiment of the application provides a frequency scale signal remote transmission method taking a frequency scale signal remote transmission system as an execution main body, which comprises the following steps:

the frequency standard signal transmission equipment performs analog-to-digital conversion on the target frequency standard signal to obtain a digital frequency standard signal and transmits the digital frequency standard signal;

the frequency standard signal recovery device processes the digital frequency standard signal by adopting any frequency standard signal remote recovery method taking the frequency standard signal recovery device as an execution main body to obtain a target frequency standard signal.

The embodiment of the application provides a frequency scale signal remote recovery device implemented from the angle of a control unit of frequency scale signal remote recovery equipment, which comprises:

the clock taming module is used for carrying out PTP synchronization with the frequency scale signal transmission equipment and outputting a clock control signal to the clock of the equipment based on the result of the PTP synchronization; the clock control signal is used for taming the clock of the equipment until the taming local clock signal and the main clock signal of the frequency standard signal transmission equipment have the same frequency and phase;

the initial frequency standard signal acquisition module is used for acquiring a digital frequency standard signal and acquiring an initial frequency standard signal; the initial frequency scale signal is obtained by performing digital-to-analog conversion on the digital frequency scale signal by using the domesticated local clock signal;

and the target frequency scale signal acquisition module is used for acquiring the data delay time of the digital frequency scale signal and adjusting the phase of the initial frequency scale signal based on the data delay time to obtain the target frequency scale signal.

The embodiment of the application provides an FPGA, which comprises a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to realize the steps of any frequency scale signal remote recovery method taking the frequency scale signal recovery equipment as an execution main body.

The embodiment of the application provides a frequency scale signal remote recovery device, which comprises a clock, a digital-to-analog converter and the FPGA; the FPGA is respectively connected with a clock and a digital-to-analog converter.

Embodiments of the present application provide a computer-readable storage medium, on which a computer program is stored, and the computer program, when executed by a processor, implements the steps of the above-mentioned method.

In the frequency standard signal remote recovery method, the frequency standard signal remote recovery device and the frequency standard signal remote transmission method, when a frequency standard signal is recovered, the device adjusts a local clock signal to be in frequency and phase with a main clock signal through a PTP technology, performs digital-to-analog conversion on a received digital frequency standard signal by using the synchronized local clock signal, so that the amplitude and frequency characteristics of an initial frequency standard signal obtained by conversion and a target frequency standard signal are the same, adjusts the phase of the initial frequency standard signal by using the data delay time of the digital frequency standard signal, so that the target frequency standard signal can be obtained, and the frequency standard signal and a standard frequency standard signal sent by a source end are in frequency and phase, so that the remote recovery of the frequency standard signal is realized, a large amount of resources can be saved, and the frequency sharing is realized. According to the method and the device, through two clock recovery mechanisms of the digital frequency standard signal and the PTP signal of remote transmission, the clock signal of the frequency standard signal transmission equipment can be recovered at the device, the accumulated error between the local clock and the clock of the frequency standard signal transmission equipment can be eliminated, a good clock recovery effect is achieved, and the target frequency standard signal obtained through recovery can remotely follow the standard frequency standard signal of the frequency standard signal transmission equipment.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the descriptions of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following descriptions are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a diagram illustrating an exemplary embodiment of a method for remote recovery of a frequency scale signal;

FIG. 2 is a flow chart illustrating a method for remotely recovering a frequency scale signal according to an embodiment;

FIG. 3 is a flowchart illustrating steps of obtaining a target frequency scale signal according to one embodiment;

FIG. 4 is a data transmission diagram illustrating the steps of obtaining data delay time in one embodiment;

FIG. 5 is a flowchart illustrating steps of outputting clock control signals according to one embodiment;

FIG. 6 is a flowchart illustrating the steps of obtaining division factors in one embodiment;

FIG. 7 is a flow chart illustrating a method for remote transmission of frequency scale signals according to one embodiment;

FIG. 8 is a signal waveform diagram of a source terminal and a recovery terminal in one embodiment;

FIG. 9 is a block diagram of an embodiment of a remote frequency scale signal recovery apparatus;

fig. 10 is a block diagram showing the structure of a remote frequency scale signal recovery apparatus according to an embodiment.

Detailed Description

To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Embodiments of the present application are set forth in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Also, as used in this specification, the term "and/or" includes any and all combinations of the associated listed items.

As background, the conventional technology cannot realize the remote transmission of the standard frequency standard signal, and the recovery end is difficult to recover the standard frequency standard signal from the received data. The inventor researches and finds that transmission of remote frequency signals mainly has two key problems, the first key problem is that network transmission can only transmit digital signals, and therefore analog signals are required to be converted into digital signals for transmission, but clocks of a source end and a recovery end are not the same clock signal, and a thunder accumulation error exists between the two clock signals, so that the two clock signals are difficult to achieve the consistent effect when AD (analog-digital)/DA (digital-analog) conversion is carried out. A second key problem is that there is a delay in the network transmission making it difficult to align the phases of the two signals being transmitted and received.

Therefore, in the prior art, if a frequency signal with the same performance as that of the remote frequency standard signal is to be generated, an atomic clock with approximately the same performance needs to be additionally arranged at the recovery end, and the purpose of synchronizing the local frequency standard and the remote frequency standard is achieved by combining the timing correction technology, but the arrangement mode greatly increases the cost and has the problem of resource waste.

In view of the above, it is necessary to provide a frequency standard signal remote recovery method, device and frequency standard signal remote transmission method, which can recover a standard frequency standard signal from a remote transmission signal and make the standard frequency standard signal at a recovery end and the standard frequency standard signal at a source end synchronized.

The method for remotely recovering the frequency scale signal can be applied to a frequency scale signal remote transmission system shown in fig. 1. Wherein, a standard frequency scale signal generating device, such as an atomic clock, etc., may be disposed at the frequency scale signal transmission device (i.e., the source end). After the generating equipment generates the standard frequency standard signal, the standard frequency standard signal is converted and sent through the frequency standard signal transmission equipment. The converted signal is transmitted remotely and received by a frequency scale signal recovery device (i.e., a recovery side).

The frequency scale signal transmission device and the frequency scale signal recovery device may include a control unit, an AD/DA conversion module, a clock, and a transmission interface, the control unit is a circuit or a device having a PTP synchronization function and a data packet interaction function, and further, the control unit may be implemented based on a single chip microcomputer or an FPGA (Field Programmable Gate Array).

In one embodiment, as shown in fig. 2, a method for remotely recovering a frequency scale signal is provided, which is exemplified by applying the method to a control unit (e.g., FPGA) of the frequency scale signal recovery apparatus in fig. 1. In this embodiment, the method includes the steps of:

step 210, performing PTP synchronization with a frequency scale signal transmission device, and outputting a clock control signal to a clock of the device based on a result of the PTP synchronization; the clock control signal is used for disciplining the clock of the equipment until the disciplined local clock signal and the main clock signal of the frequency standard signal transmission equipment have the same frequency and the same phase.

The frequency scale signal transmission device, i.e. the source end, includes a device of a master clock in the PTP time protocol. The PTP time protocol defines a master-slave concept, which specifies that only one master clock and a plurality of slave clocks are arranged in a local area network, the master clock is selected during PTP operation and determined by the PTP, calculation can be carried out according to an optimal master clock algorithm, and each slave clock in the local area network takes the master clock as a reference to carry out clock synchronization. The device can be a frequency scale signal recovery device, namely a recovery end, to which the control unit belongs. The local clock signal can be a system clock signal of the device, and the main clock signal is a system clock signal of the frequency scale signal transmission device.

The control unit of the device performs PTP synchronization with the master clock device, and obtains a clock deviation between the clock of the device and the master clock, that is, a difference between the time of the clock of the device and the time of the master clock. And performing clock discipline on the clock of the equipment based on the acquired clock deviation so as to calibrate the clock of the equipment until the clock of the equipment is synchronous with the main clock, namely, the clock is in the same frequency and phase with the main clock. Specifically, the control unit of the present device may output a clock control signal to the clock of the present device, and tame the clock of the present device by the clock control signal, and further, may tame the clock of the present device by using the principle of the generalized phase-locked loop. Therefore, through PTP synchronization and clock discipline, the clock signal of the source end can be recovered at the recovery end, the accumulated error between the local clock and the clock of the source end can be eliminated, and a good clock recovery effect is achieved.

Step 220, acquiring a digital frequency scale signal and acquiring an initial frequency scale signal; the initial frequency scale signal is obtained by performing digital-to-analog conversion on the digital frequency scale signal by using the domesticated local clock signal.

The digital frequency standard signal is obtained by performing analog-to-digital conversion on a standard frequency standard signal, and can be received through a remote transmission network (such as a gigabit network). The initial frequency scale signal is a signal obtained by performing digital-to-analog conversion on the digital frequency scale signal by using the domesticated local clock as a working clock for digital-to-analog conversion.

Specifically, the control unit of the apparatus may obtain a digital frequency scale signal, further receive the digital frequency scale signal after the remote transmission, and output the digital frequency scale signal and the tamed local clock signal to the digital-to-analog converter, where a working clock of the digital-to-analog converter is generated according to the tamed local clock, and the digital-to-analog converter performs digital-to-analog conversion on the digital frequency scale signal to obtain an initial frequency scale signal. The control unit of the device can receive the initial frequency scale signal output by the digital-to-analog converter. The master clock signal is a system working clock of a source end and is used for generating a working clock for analog-to-digital conversion processing of the standard frequency scale signal, the local clock signal is used as a system working clock of the equipment and is used for generating a working clock for digital-to-analog processing of the digital frequency scale signal, and the local clock signal is synchronous with the master clock signal, so that an initial frequency scale signal with the same frequency as the standard frequency scale signal can be obtained after digital-to-analog conversion.

Step 230, obtaining the data delay time of the digital frequency scale signal, and adjusting the phase of the initial frequency scale signal based on the data delay time to obtain the target frequency scale signal.

The data delay time is a network delay between the source end and the recovery end, that is, a time interval between the source end sending the digital frequency scale signal and the recovery end receiving the digital frequency scale signal. The target frequency scale signal is a signal with the same frequency and phase as the standard frequency scale signal of the source end.

Specifically, the phase of the initial frequency standard signal is delayed from the phase of the standard frequency standard signal, the phase difference between the initial frequency standard signal and the standard frequency standard signal can be determined by acquiring the data delay time of the digital frequency standard signal, and the phase of the initial frequency standard signal is adjusted according to the phase difference to obtain the target frequency standard signal.

In the frequency standard signal remote recovery method, when a recovery end recovers a frequency standard signal, a local clock signal is adjusted to be in frequency and phase with a main clock signal through a PTP technology, digital-to-analog conversion is carried out on the received digital frequency standard signal by using the synchronized local clock signal, so that the amplitude and frequency characteristics of the converted initial frequency standard signal and a target frequency standard signal are the same, and then the phase of the initial frequency standard signal is adjusted by using the data delay time of the digital frequency standard signal, so that the target frequency standard signal can be obtained, the target frequency standard signal is in frequency and phase with a standard frequency standard signal sent by a source end, the remote recovery of the frequency standard signal is realized, a large number of resources can be saved, and the frequency sharing is realized. According to the method and the device, through two clock recovery mechanisms of the digital frequency standard signal and the PTP signal of remote transmission, the clock signal of the frequency standard signal transmission equipment can be recovered at the recovery end, the accumulated error between the local clock and the source end clock can be eliminated, a good clock recovery effect is achieved, and the target frequency standard signal obtained through recovery can remotely follow the standard frequency standard signal of the source end.

In one embodiment, as shown in fig. 3, the step of adjusting the phase of the initial frequency scale signal based on the data delay time to obtain the target frequency scale signal includes:

step 310, measuring the period of the initial frequency scale signal, and obtaining data delay time through the domesticated local clock signal;

and step 320, calculating a phase delay amount according to the period and the data delay time, and adjusting the phase of the initial frequency standard signal according to the phase delay amount to obtain a target frequency standard signal.

Specifically, in the step of adjusting the phase of the initial frequency scale signal, the network delay between the source end and the recovery end can be obtained through two parts of delay measurement and delay compensation, and phase compensation calculation is performed according to the measurement result. In the delay measurement, the data delay time can be obtained through the local clock signal after taming. Because the system clock signal of the source end and the system clock signal of the recovery end are clock signals with the same frequency, the high-order counters are respectively designed at the source end and the recovery end, so that the local clock can be timed. The recovery end sends the data packet containing the local counter value to the source end, and the source end adds the self counter value into the data packet and sends the updated data packet to the recovery end. Thus, the recovery side can determine 2 transmission times and 2 reception times when receiving the data packet. Referring to fig. 4, the 4 times are a packet transmission time t1 at the recovery end, a packet reception time t2 at the source end, a packet transmission time t3 at the source end, and a packet reception time t4 at the recovery end, respectively. In fig. 4, the solid line indicates the actual transmission/reception time interval, and the dotted line indicates the theoretical transmission/reception time interval.

Further, the data delay time is an average path delay between the frequency scale signal transmission device and the device, that is, the data delay time may be an average of the delay time from the recovery end to the source end (i.e., a difference of t2 minus t 1) and the delay time from the source end to the recovery end (i.e., a difference of t4 minus t 3).

When time delay compensation is carried out, the period of the initial frequency scale signal can be measured, furthermore, the FPGA can be used for measuring by adopting an equal-precision measuring method, the dynamic measuring threshold width is about 1 second, the frequency (period) measuring progress in the whole measuring range is close to TCLK (second)/1 (second), wherein TCLK is the working time of the FPGA and can reach nanosecond level. Thus, the periodic measurement accuracy can be 1E-8. After the period of the initial frequency standard signal is determined, the phase delay amount can be calculated according to the period and the data delay time, the phase of the initial frequency standard signal is adjusted according to the phase delay amount, and the phase delay amount of the initial frequency standard signal is supplemented to be an integral multiple of the period angle (namely 360 degrees), such as 1 time, 2 times or 5 times, so as to obtain the target frequency standard signal. Furthermore, the high-speed dual-port SRAM delay reading management can be used for realizing accurate delay control, so that the source end and the recovery end realize strict phase alignment.

For example, the product of the ratio of the data delay time to the period and the period angle may be determined as the phase delay amount. If the measured period is Ts and the data delay time is t5, the phase lag at the recovery end may be (t5/Ts) × 360 °.

Therefore, because the initial frequency standard signal and the target frequency standard signal are both periodic signals, when the phase delay amount of the initial frequency standard signal is an integral multiple of the period angle, the adjusted initial frequency standard signal is consistent with the target frequency standard signal of the source end in phase, so that the recovery end can obtain the target frequency standard signal with the same frequency and phase as the source end, and the remote recovery of the standard frequency standard signal is realized.

Furthermore, the network delay between the source end and the recovery end can be accurately measured through a delay measurement technology, and because the frequency signal is a periodic signal, the output of a memory in the frequency scale signal recovery equipment can be controlled through an address control technology to delay data so as to control the alignment of phases. Therefore, the phase is accurately aligned by adopting a digital technology, and the alignment accuracy can reach the clock period of the FPGA, namely nanosecond accuracy.

In one embodiment, as shown in fig. 5, the step of outputting a clock control signal to the clock of the present device based on the result of PTP synchronization includes:

step 510, respectively determining a master clock count value and a local device clock count value of the current synchronization period according to a PTP synchronization result, and processing the master clock count value and the local device clock count value to obtain a frequency division coefficient of the current synchronization period;

step 520, multiplying the frequency division coefficient of the current synchronization cycle by the frequency compensation value of the previous synchronization cycle, and determining the multiplication result as the frequency compensation value of the current synchronization cycle;

step 530, outputting a clock control signal corresponding to the current synchronization period to the clock of the device based on the frequency compensation value of the current synchronization period.

The main clock count value is the value of a clock counter in the frequency scale signal transmission equipment, and the clock count value of the equipment is the value of the clock counter in the equipment. When the device generates a system clock signal, it needs to count a signal output by a device clock (such as a crystal oscillator) through a clock counter, and when the count value is equal to or greater than a value corresponding to the system clock frequency, the device outputs the clock signal and continues to count or clear the counter to generate the system clock signal of the next period.

Specifically, in performing clock calibration, it is necessary to calculate the frequency offset from the synchronization message and update the addend register accordingly. Firstly, the clock of the device can be set by using the frequency compensation value in the addend register, and the frequency compensation value can be calculated by adopting the following formula:

Fre_c＝2^A/Fre_D

wherein Fre_cThe frequency compensation value can be stored in a register; a is the number of bits of the register, and the value of A can be 16, 32 or 64, etc.; fre_DFor the division factor, stored in a register. If 20 ns accuracy is required, the PTP master clock is 50 mhz, and if the local clock signal of the present device is 168 mhz, the initial frequency division coefficient may be determined based on the following equation:

Fre_D＝SYSCLK/PTPCLK

wherein Fre_DA frequency division coefficient; SYSCLK is the frequency value of the local clock signal; PTPCLK is the frequency value of the PTP master clock, i.e., the frequency value of the master clock signal.

Specifically, in the PTP synchronization process, for each synchronization period, the frequency scale signal transmission device sends a synchronization message to the frequency scale signal recovery device, and the synchronization message is received by the frequency scale signal recovery device after a certain network delay. The clock count value of the device is the value of the clock counter of the frequency scale signal transmission device when the synchronization information is received, and the main clock count value is the value of the clock counter of the frequency scale signal transmission device when the frequency scale signal recovery device receives the synchronization information.

And obtaining a frequency division coefficient of the current synchronization period according to the main clock count value and the clock count value of the equipment, multiplying the frequency division coefficient of the current period by the frequency compensation value of the previous synchronization period, and confirming the product obtained by the multiplication as the frequency compensation value of the current synchronization period. After obtaining the frequency compensation value, the difference between the frequency and the phase between the signal output by the clock of the device and the signal output by the clock of the source end can be confirmed, and the clock control signal corresponding to the current synchronization period is output to the clock of the device based on the frequency compensation value of the current synchronization period.

In one embodiment, as shown in fig. 6, the step of processing the master clock count value and the device clock count value to obtain the frequency division coefficient of the current synchronization cycle includes:

step 610, confirming the difference value between the main clock count value and the equipment clock count value as clock deviation;

and step 620, filtering the clock deviation by adopting a one-dimensional Kalman filtering algorithm to obtain the filtered clock deviation, acquiring a sum of the filtered clock deviation and a main clock counting value, and determining a quotient of the sum and the main clock counting value as a frequency division coefficient of a synchronization period.

Specifically, if the master-slave delay mastertoslavidedelay (i.e., the delay time for the source end to send data to the recovery end) is the same for the consecutive synchronization messages, the frequency division coefficient and the frequency compensation value of the current synchronization period may be calculated through the following processes. After a few synchronization cycles, the frequency will lock, and the clock of the device (i.e., the slave clock) can then determine the exact value of the mastertoslavededelay and resynchronize with the clock of the frequency scale signaling device (i.e., the master clock) using the updated mastertoslavededelay. Specifically, calculating the frequency division coefficient and the frequency compensation value of the current synchronization period may be:

(1) at mastersynctime (n), the master clock sends a synchronization message to the slave clock. The slave clock receives the synchronization message when the local clock is SlaveClockTime (n), and calculates MasterClockTime (n) by using the following formula:

MasterClockTime(n)＝MasterSyncTime(n)+MasterToSlaveDelay(n)

wherein n is the nth discretized digital time, namely the nth synchronization period; masterclocktime (n) is the corresponding master clock time when the slave clock time is slave clock time (n) in the current synchronization period.

(2) If the master-slave delay mastertoslavidedelay is the same for the nth sync period and the (n-1) th sync period, the master clock count value masterlockcount (n) of the current sync period is:

MasterClockCount(n)＝MasterClockTime(n)－MasterClockTime(n-1)

wherein, the MasterClockTime (n-1) is the main clock time corresponding to the n-1 th synchronization period.

(3) The clock count value slaveclockcount (n) of the present device in the current synchronization period is:

SlaveClockCount(n)＝SlaveClockTime(n)－SlaveClockTime(n-1)

wherein SlaveClockTime (n-1) is the time when the slave clock receives the synchronization message in the (n-1) th synchronization period.

(4) The difference between the master clock count and the slave clock count in the current synchronization period, clockdiffcount (n), i.e. the clock skew is: clockdiffcount (n) -masterclockcount (n) -slavicockcount (n).

(5) In the current synchronization period, the frequency division coefficient of the slave clock is as follows:

(6) frequency compensation value Fre of addend register in current synchronization period_c(n) is:

Fre_c(n)＝Fre_s(n)×Fre_c(n-1)

wherein Fre_cAnd (n-1) is the frequency compensation value of the (n-1) th synchronous period.

The obtained frequency compensation value is used as a reference input of the domesticated local clock and is used for generating a clock control signal, and the clock of the equipment is domesticated through the clock control signal. In theory, the algorithm of the present application can achieve locking within one synchronization period, but may require multiple periods given the network transmission delay and the constant variation of operating conditions. The algorithm of the application can carry out self calibration, and if the slave clock initially set by the master clock is incorrect due to some reasons, the calibration of the local clock can be realized through a large number of synchronous cycles.

In order to reduce the influence of second signal jitter and measured system error on clock discipline existing in the time frequency information of PTP recovery as much as possible, after remote time synchronization, filtering processing can be carried out on the measured clock deviation to eliminate the jitter, and the clock of the equipment can be disciplined according to the difference between the second pulse frequency phase of the clock output signal of the equipment and the second pulse frequency phase of the PTP output signal. Because the jitter between the PTP output second pulse and the standard time is a random service and obeys positive distribution, the influence of random jump of the PTP output second pulse can be eliminated by utilizing the arithmetic mean of a plurality of measured data, and because the average number of clock deviations is difficult to determine and real-time processing cannot be carried out, the clock deviations can be subjected to real-time filtering processing by adopting a one-dimensional Kalman algorithm. Therefore, the filtering result is ensured, the jitter is eliminated, and meanwhile, the storage capacity of data can be reduced.

In one embodiment, the step of outputting the clock control signal corresponding to the current synchronization period to the clock of the present device based on the frequency compensation value of the current synchronization period includes: and processing the frequency compensation value of the current synchronization period by adopting a PID algorithm to obtain and output a clock control signal corresponding to the current synchronization period.

Specifically, in order to eliminate the static error of the system, the frequency compensation value of the current synchronization period is processed through a classical PID algorithm to calculate a voltage value to be adjusted, namely a clock control signal. Further, smooth filtering can be added to make the voltage value of the output clock control signal smooth, so that the final deviation of the clock for controlling the device tends to zero. At this time, the PID algorithm may be used to implement a filtering function, and further, may be used to implement a low-pass filtering function.

In one embodiment, as shown in fig. 7, a method for remote transmission of a frequency scale signal is provided, which is exemplified by applying the method to the frequency scale signal remote transmission system in fig. 1. In this embodiment, the method includes the steps of:

step 710, the frequency standard signal transmission equipment performs analog-to-digital conversion on the target frequency standard signal to obtain a digital frequency standard signal and sends the digital frequency standard signal;

step 720, the frequency scale signal recovery device processes the digital frequency scale signal by using the frequency scale signal remote recovery method in any of the above embodiments to obtain a target frequency scale signal.

The target frequency scale signal is a standard frequency scale signal and is an analog signal.

Specifically, the frequency scale signal transmission device is a source end, and is configured to convert a target frequency scale signal from an analog signal to a digital signal, obtain a digital frequency scale signal, and transmit the digital frequency scale signal through a remote transmission network (e.g., a gigabit network). The frequency scale signal recovery device is a recovery end and is used for receiving the digital frequency scale signal through a remote transmission network and recovering the digital frequency scale signal to obtain a target frequency scale signal. In the process of recovering the target frequency standard signal, the frequency standard signal recovery device may first synchronize a system clock signal (i.e., a local clock signal) of the device with a system clock signal of the source end through a PTP technique, that is, the system clock signal of the recovery end and the system clock signal of the source end have the same frequency and the same phase, and perform digital-to-analog conversion on the received digital frequency standard signal by using the synchronized local clock signal to obtain an initial frequency standard signal. In this way, the initial frequency scale signal can be made identical to the target frequency scale signal in terms of amplitude and frequency characteristics.

The phase alignment may be performed by a phase synchronization technique for differences in phase between the initial frequency scale signal and the target frequency scale signal. Specifically, the network delay between the source end and the recovery end can be accurately measured through a delay measurement technology, and since the frequency signal is a periodic signal, the output of a memory in the frequency scale signal recovery equipment can be controlled through an address control technology to perform data delay so as to control the alignment of phases.

The remote transmission and recovery of frequency signals, frequency alignment, phase alignment and stricter synchronization of source signals and far-end signals are achieved. As shown in fig. 8, actually measured frequency stability and phase noise are substantially consistent, where a blue line is oscillation caused by measurement error due to network instability, so as to ensure stable transmission of the transmission network as much as possible, and avoid destroying frequency stability as much as possible when debugging the taming module, and the PID parameters are adaptively adjusted. Thus, referring to the results of the two remaining measurements in FIG. 8, it can be determined that the input and output signals have substantially matched.

In one example, after the delay is increased by 3 routers, and the two signal waveforms of the source end and the recovery end are basically overlapped without phase fluctuation after being observed by an oscilloscope. The data of the source end and the recovery end are basically as shown in table 1 and table 2:

TABLE 110 MHz frequency characteristics test record

Table 210 MHz frequency phase noise test record

It should be understood that although the various steps in the flowcharts of fig. 1-7 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least some of the steps in fig. 1-7 may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, which are not necessarily performed in sequence, but may be performed in turn or alternately with other steps or at least some of the other steps.

In one embodiment, as shown in fig. 9, there is provided a frequency scale signal remote recovery apparatus implemented from the perspective of a control unit of a frequency scale signal recovery device, including:

the clock taming module is used for carrying out PTP synchronization with the frequency scale signal transmission equipment and outputting a clock control signal to the clock of the equipment based on the result of the PTP synchronization; the clock control signal is used for taming the clock of the equipment until the taming local clock signal and the main clock signal of the frequency standard signal transmission equipment have the same frequency and phase;

the initial frequency standard signal acquisition module is used for acquiring a digital frequency standard signal and acquiring an initial frequency standard signal; the initial frequency scale signal is obtained by performing digital-to-analog conversion on a digital frequency scale signal by using a domesticated local clock signal;

and the target frequency scale signal acquisition module is used for acquiring the data delay time of the digital frequency scale signal and adjusting the phase of the initial frequency scale signal based on the data delay time to obtain the target frequency scale signal.

In one embodiment, the target frequency scale signal acquisition module comprises: the measuring unit is used for measuring the period of the initial frequency scale signal and obtaining data delay time through the domesticated local clock signal; and the adjusting unit is used for calculating the phase delay amount according to the period and the data delay time, and adjusting the phase of the initial frequency standard signal according to the phase delay amount to obtain the target frequency standard signal.

In one embodiment, the adjusting unit is further configured to obtain a ratio of the data delay time to the period, and determine a product of the ratio and the period angle as the phase delay amount.

In one embodiment, the clock disciplining module includes: the frequency division coefficient confirming unit is used for respectively determining a main clock count value and a local equipment clock count value of the current synchronization period according to the PTP synchronization result, and processing the main clock count value and the local equipment clock count value to obtain the frequency division coefficient of the current synchronization period; a frequency compensation value confirmation unit, configured to multiply the frequency division coefficient of the current synchronization cycle by the frequency compensation value of the previous synchronization cycle, and confirm a result of the multiplication as the frequency compensation value of the current synchronization cycle; and the signal output unit is used for outputting a clock control signal corresponding to the current synchronization period to the clock of the equipment based on the frequency compensation value of the current synchronization period.

In one embodiment, the frequency division coefficient confirming unit is further configured to confirm a difference between a master clock count value and a local device clock count value as a clock offset; and filtering the clock deviation by adopting a one-dimensional Kalman filtering algorithm to obtain the filtered clock deviation, acquiring a sum of the filtered clock deviation and a main clock counting value, and determining a quotient of the sum and the main clock counting value as a frequency division coefficient of a synchronization period.

In one embodiment, the clock disciplining module further comprises: and processing the frequency compensation value of the current synchronization period by adopting a PID algorithm to obtain and output a clock control signal corresponding to the current synchronization period.

In one embodiment, the data delay time is an average path delay between the frequency scale signal transmission device and the local device; the digital frequency scale signal is received by the equipment through the gigabit network.

For specific limitations of the frequency scale signal remote recovery apparatus, reference may be made to the above limitations of the frequency scale signal remote recovery method, and details are not described herein again. The modules in the above frequency scale signal remote recovery device can be wholly or partially implemented by software, hardware and a combination thereof. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules. It should be noted that, in the embodiment of the present application, the division of the module is schematic, and is only one logic function division, and there may be another division manner in actual implementation.

In one embodiment, there is provided an FPGA comprising a memory and a processor, the memory having a computer program stored therein, the processor when executing the computer program implementing the steps of:

PTP synchronization is carried out with the frequency scale signal transmission equipment, and a clock control signal is output to a clock of the equipment based on the result of the PTP synchronization; the clock control signal is used for taming the clock of the equipment until the taming local clock signal and the main clock signal of the frequency standard signal transmission equipment have the same frequency and phase;

acquiring a digital frequency scale signal and acquiring an initial frequency scale signal; the initial frequency scale signal is obtained by performing digital-to-analog conversion on a digital frequency scale signal by using a domesticated local clock signal;

and acquiring data delay time of the digital frequency scale signal, and adjusting the phase of the initial frequency scale signal based on the data delay time to obtain a target frequency scale signal.

In one embodiment, the processor, when executing the computer program, further performs the steps of: measuring the period of an initial frequency scale signal, and obtaining data delay time through a domesticated local clock signal; and calculating a phase delay amount according to the period and the data delay time, and adjusting the phase of the initial frequency scale signal according to the phase delay amount to obtain a target frequency scale signal.

In one embodiment, the processor, when executing the computer program, further performs the steps of: and acquiring the ratio of the data delay time to the period, and determining the product of the ratio and the period angle as the phase delay amount.

In one embodiment, the processor, when executing the computer program, further performs the steps of: respectively determining a main clock count value and a local device clock count value of the current synchronization period according to a PTP synchronization result, and processing the main clock count value and the local device clock count value to obtain a frequency division coefficient of the current synchronization period; multiplying the frequency division coefficient of the current synchronization period by the frequency compensation value of the previous synchronization period, and confirming the multiplication result as the frequency compensation value of the current synchronization period; and outputting a clock control signal corresponding to the current synchronization period to the clock of the equipment based on the frequency compensation value of the current synchronization period.

In one embodiment, the processor, when executing the computer program, further performs the steps of: confirming the difference value between the main clock count value and the clock count value of the equipment as clock deviation; and filtering the clock deviation by adopting a one-dimensional Kalman filtering algorithm to obtain the filtered clock deviation, acquiring a sum of the filtered clock deviation and a main clock counting value, and determining a quotient of the sum and the main clock counting value as a frequency division coefficient of a synchronization period.

In one embodiment, the processor, when executing the computer program, further performs the steps of: and processing the frequency compensation value of the current synchronization period by adopting a PID algorithm to obtain and output a clock control signal corresponding to the current synchronization period.

In one embodiment, the processor, when executing the computer program, further performs the steps of: the data delay time is the average path delay between the frequency standard signal transmission equipment and the equipment; the digital frequency scale signal is received by the equipment through the gigabit network.

In one embodiment, as shown in fig. 10, there is provided a frequency scale signal remote recovery apparatus, including a clock, a digital-to-analog converter and the FPGA of any of the above embodiments; the FPGA is respectively connected with a clock and a digital-to-analog converter.

Specifically, the FPGA and the frequency scale signal transmission equipment carry out PTP synchronization, and based on a PTP synchronization result, a clock control signal is output to a clock of the equipment; the clock control signal is used for disciplining the clock of the equipment until the disciplined local clock signal and the main clock signal of the frequency standard signal transmission equipment have the same frequency and the same phase. The FPGA acquires a digital frequency scale signal and outputs the digital signal and the tamed local clock signal to the digital-to-analog converter. And D/A conversion is carried out on the digital frequency scale signal by taking a signal based on the domesticated local clock signal as a working clock to obtain an initial frequency scale signal. And the FPGA acquires an initial frequency standard signal, and adjusts the phase of the initial frequency standard signal to obtain a target frequency standard signal.

In one embodiment, a computer-readable storage medium is provided, having a computer program stored thereon, which when executed by a processor, performs the steps of:

PTP synchronization is carried out with the frequency scale signal transmission equipment, and a clock control signal is output to a clock of the equipment based on the result of the PTP synchronization; the clock control signal is used for taming the clock of the equipment until the taming local clock signal and the main clock signal of the frequency standard signal transmission equipment have the same frequency and phase;

acquiring a digital frequency scale signal and acquiring an initial frequency scale signal; the initial frequency scale signal is obtained by performing digital-to-analog conversion on a digital frequency scale signal by using a domesticated local clock signal;

and acquiring data delay time of the digital frequency scale signal, and adjusting the phase of the initial frequency scale signal based on the data delay time to obtain a target frequency scale signal.

In one embodiment, the computer program when executed by the processor further performs the steps of: measuring the period of an initial frequency scale signal, and obtaining data delay time through a domesticated local clock signal; and calculating a phase delay amount according to the period and the data delay time, and adjusting the phase of the initial frequency scale signal according to the phase delay amount to obtain a target frequency scale signal.

In one embodiment, the computer program when executed by the processor further performs the steps of: and acquiring the ratio of the data delay time to the period, and determining the product of the ratio and the period angle as the phase delay amount.

In one embodiment, the computer program when executed by the processor further performs the steps of: respectively determining a main clock count value and a local device clock count value of the current synchronization period according to a PTP synchronization result, and processing the main clock count value and the local device clock count value to obtain a frequency division coefficient of the current synchronization period; multiplying the frequency division coefficient of the current synchronization period by the frequency compensation value of the previous synchronization period, and confirming the multiplication result as the frequency compensation value of the current synchronization period; and outputting a clock control signal corresponding to the current synchronization period to the clock of the equipment based on the frequency compensation value of the current synchronization period.

In one embodiment, the computer program when executed by the processor further performs the steps of: confirming the difference value between the main clock count value and the clock count value of the equipment as clock deviation; and filtering the clock deviation by adopting a one-dimensional Kalman filtering algorithm to obtain the filtered clock deviation, acquiring a sum of the filtered clock deviation and a main clock counting value, and determining a quotient of the sum and the main clock counting value as a frequency division coefficient of a synchronization period.

In one embodiment, the computer program when executed by the processor further performs the steps of: and processing the frequency compensation value of the current synchronization period by adopting a PID algorithm to obtain and output a clock control signal corresponding to the current synchronization period.

In one embodiment, the computer program when executed by the processor further performs the steps of: the data delay time is the average path delay between the frequency standard signal transmission equipment and the equipment; the digital frequency scale signal is received by the equipment through the gigabit network.

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database or other medium used in the embodiments provided herein can include at least one of non-volatile and volatile memory. Non-volatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical storage, or the like. Volatile Memory can include Random Access Memory (RAM) or external cache Memory. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM), among others.

In the description herein, references to the description of "some embodiments," "other embodiments," "desired embodiments," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, a schematic description of the above terminology may not necessarily refer to the same embodiment or example.

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (10)

1. A method for remotely recovering a frequency scale signal, comprising the steps of:

PTP synchronization is carried out with a frequency scale signal transmission device, and a clock control signal is output to a clock of the device based on the result of the PTP synchronization; the clock control signal is used for disciplining the clock of the equipment until the disciplined local clock signal and the main clock signal of the frequency standard signal transmission equipment have the same frequency and the same phase;

acquiring a digital frequency scale signal and acquiring an initial frequency scale signal; the initial frequency scale signal is obtained by performing digital-to-analog conversion on the digital frequency scale signal by using the domesticated local clock signal;

and acquiring data delay time of the digital frequency scale signal, and adjusting the phase of the initial frequency scale signal based on the data delay time to obtain a target frequency scale signal.

2. The method for remotely recovering a frequency scale signal according to claim 1, wherein the step of adjusting the phase of the initial frequency scale signal based on the data delay time to obtain a target frequency scale signal comprises:

measuring the period of the initial frequency scale signal, and obtaining the data delay time through the tamed local clock signal;

and calculating a phase delay amount according to the period and the data delay time, and adjusting the phase of the initial frequency standard signal according to the phase delay amount to obtain the target frequency standard signal.

3. The method for remotely recovering a frequency scale signal according to claim 2, wherein the step of calculating the phase delay amount based on the period and the data delay time comprises:

and acquiring the ratio of the data delay time to the period, and determining the product of the ratio and the period angle as the phase delay amount.

4. The method for remotely recovering a frequency scale signal according to claim 1, wherein the step of outputting a clock control signal to the clock of the own device based on the result of the PTP synchronization comprises:

respectively determining a main clock count value and a local equipment clock count value of the current synchronization period according to the PTP synchronization result, and processing the main clock count value and the local equipment clock count value to obtain a frequency division coefficient of the current synchronization period;

multiplying the frequency division coefficient of the current synchronization period by the frequency compensation value of the previous synchronization period, and confirming the result of the multiplication as the frequency compensation value of the current synchronization period;

and outputting a clock control signal corresponding to the current synchronization period to the clock of the equipment based on the frequency compensation value of the current synchronization period.

5. The method for remotely recovering a frequency scale signal according to claim 4, wherein the step of processing the master clock count value and the local device clock count value to obtain the frequency division coefficient of the current synchronization cycle comprises:

confirming the difference value between the main clock count value and the local device clock count value as clock deviation;

and filtering the clock deviation by adopting a one-dimensional Kalman filtering algorithm to obtain the filtered clock deviation, acquiring a sum of the filtered clock deviation and the main clock counting value, and determining the quotient of the sum and the equipment clock counting value as the frequency division coefficient of the synchronization period.

6. The method for remotely recovering a frequency scale signal according to claim 4 or 5, wherein the step of outputting the clock control signal corresponding to the current synchronization period to the clock of the device based on the frequency compensation value of the current synchronization period comprises:

and processing the frequency compensation value of the current synchronization period by adopting a PID algorithm to obtain and output a clock control signal corresponding to the current synchronization period.

7. The method for remotely restoring a frequency scale signal according to any one of claims 1 to 5, wherein the data delay time is an average path delay between the frequency scale signal transmission device and the device; the digital frequency scale signal is received by the equipment through a gigabit network.

8. A method for remote transmission of a frequency scale signal, comprising the steps of:

the frequency standard signal transmission equipment performs analog-to-digital conversion on the target frequency standard signal to obtain a digital frequency standard signal and transmits the digital frequency standard signal;

frequency scale signal recovery apparatus processes said digital frequency scale signal using a frequency scale signal remote recovery method according to any one of claims 1 to 7 to obtain said target frequency scale signal.

9. A device for remotely recovering a frequency scale signal, comprising:

the clock taming module is used for carrying out PTP synchronization with the frequency scale signal transmission equipment and outputting a clock control signal to the clock of the equipment based on the result of the PTP synchronization; the clock control signal is used for disciplining the clock of the equipment until the disciplined local clock signal and the main clock signal of the frequency standard signal transmission equipment have the same frequency and the same phase;

the initial frequency standard signal acquisition module is used for acquiring a digital frequency standard signal and acquiring an initial frequency standard signal; the initial frequency scale signal is obtained by performing digital-to-analog conversion on the digital frequency scale signal by using the domesticated local clock signal;

and the target frequency scale signal acquisition module is used for acquiring the data delay time of the digital frequency scale signal and adjusting the phase of the initial frequency scale signal based on the data delay time to obtain the target frequency scale signal.

10. An FPGA comprising a memory and a processor, the memory storing a computer program, wherein the processor when executing the computer program implements the steps of the method of any one of claims 1 to 7.

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