CN112952789A - High Latch up capability fail safe IO circuit - Google Patents
High Latch up capability fail safe IO circuit Download PDFInfo
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- CN112952789A CN112952789A CN202110346098.6A CN202110346098A CN112952789A CN 112952789 A CN112952789 A CN 112952789A CN 202110346098 A CN202110346098 A CN 202110346098A CN 112952789 A CN112952789 A CN 112952789A
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- 230000003071 parasitic effect Effects 0.000 claims abstract description 20
- 238000010586 diagram Methods 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 5
- 238000013461 design Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 208000033999 Device damage Diseases 0.000 description 1
- VMXJCRHCUWKQCB-UHFFFAOYSA-N NPNP Chemical group NPNP VMXJCRHCUWKQCB-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000013021 overheating Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
Abstract
The invention discloses a failure safety IO circuit with high Latch up capability, which comprises a failure safety IO basic circuit and a divider resistor R1; the basic fail safe IO circuit comprises a first control end input interface and a second control end input interface, wherein a first control signal and a second control signal are respectively input from the outside through the first control end input interface and the second control end input interface so as to control the work of the circuit; the failure safety IO basic circuit also comprises a PAD end, wherein the PAD end is a signal current channel; and the positive power supply terminal of the fail-safe IO basic circuit is connected to an external power supply through a resistor R1. When the circuit works normally, the voltage drop formed by the smaller driving current on the divider resistor is extremely small, and the normal work of the circuit is not influenced; when it is assumed that Latch up occurs, the voltage drop generated by the large Latch up holding current across the voltage dividing resistors causes the source terminal voltage of the parasitic SCR to be lower than the holding voltage of Latch up, thereby suppressing the occurrence of Latch up.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuits, in particular to a fail-safe IO circuit with high Latch up capability.
Background
As electronic technology develops and electronic circuits become more and more integrated, related voltage transients cause semiconductor device failure, i.e. latch-up. In cmos chips, Latch up is a low impedance path between power supply VDD and ground GND (vss) due to the interaction of parasitic PNP and NPN bipolar BJTs, the presence of which causes a large current to flow between VDD and GND. As shown in (a) and (b) of fig. 1, P (Source/Drain of PMOS) -N (nwell of PMOS) - — P (P sub); n (PMOS Nwell) -P (P sub) -N (NMOS Source/Drain) form two BJTs.
QPNP is a vertical PNP BJT, base is Nwell, and current gain β 1 from base to collector can be hundreds times; the QNPN is a lateral NPN BJT, the base is a P substrate, and the current gain beta 2 from the base to the collector (collector) can reach tens of times. Rwell is the parasitic resistance of Nwell, which can be as high as 20K Ω; rsub is the substrate resistance, which has values from hundreds to several ohms. The QPNP and QNPN form an NPNP structure to form a Silicon-controlled rectifier (SCR) circuit. When no external interference causes triggering, the two BJTs are in a cut-off state, collector current is formed by reverse leakage current of C-B, current gain is very small, and Latch up cannot be generated at the moment.
When the collector current of one BJT is suddenly increased to a certain value by external interference, the emitting junction of the BJT is positively biased, the current is fed back to the other BJT, and the current caused by the final feedback loop needs to be multiplied by gain beta 1 multiplied by beta 2, which is triggered by SCR. Therefore, two BJTs are turned on by triggering, and a low impedance path is formed between VDD and GND (VSS), so that Latch up is generated.
If β 1 × β 2 ≧ 1 is satisfied, the two BJTs will continue to produce high saturation current, even in the absence of a trigger condition.
From the semiconductor process level, if a strong electric field is applied to the oxide film in the device structure, the oxide film is damaged by dielectric breakdown. Very thin metallization traces can be damaged by high currents and can form open circuits due to overheating caused by surge currents. The device forms a short circuit between the power supply and ground in a state where latch-up occurs, resulting in large current, EOS, and device damage. The locking effect test provides an important technical basis for product reliability design, and different locking failure modes can reveal different design process defects.
As IC manufacturing processes have been developed, the packaging density and the integration degree have become higher and higher, and the possibility of generating Latch up has become higher and higher. The amount of excess current generated by Latch up, which is one of the most important measures in IC design, may cause permanent damage to the chip.
Latch up is most likely to occur at I/O circuits that are susceptible to external interference, and also occurs occasionally at internal circuits. In the fail-safe (fail-safe) IO application, as shown in fig. 2, since the signal current on the PAD cannot reach the power supply to cause leakage in case of power failure, the bulk terminal of the PMOS transistor of the output driver cannot be connected to the power supply, but a high voltage selection circuit is used to switch between the power supply voltage and the PAD power supply. This structure is very weak to the ability to control Latch up.
Fig. 3 is an equivalent circuit diagram of parasitic devices of the fail-safe (fail-safe) IO circuit shown in fig. 2. Rpwell is the equivalent resistance of the P-well. The equivalent resistance R0 of the high-voltage selection circuit is much larger than the equivalent resistance of the Nwell (N-well) of the PMOS transistor whose bulk terminal is directly connected to the power supply, so the structure shown in fig. 2 can be considered as an Nwell floating thyristor SCR. This configuration is very susceptible to failure when a negative current triggers Latch up.
Disclosure of Invention
The invention aims to provide a fail-safe IO circuit with high Latch up capability.
To solve the above problems, the present invention provides a fail-safe IO circuit with high Latch up capability, which comprises a fail-safe IO basic circuit and a resistor R1;
the basic fail safe IO circuit comprises a first control end input interface and a second control end input interface, wherein a first control signal and a second control signal are respectively input from the outside through the first control end input interface and the second control end input interface so as to control the work of the circuit;
the failure safety IO basic circuit also comprises a PAD end, wherein the PAD end is a signal current channel;
the failure safety IO basic circuit also comprises a power supply anode and a power supply cathode, wherein the power supply cathode is grounded;
the positive pole of the power supply is connected to an external power supply through a resistor R1.
Furthermore, the basic fail safe IO circuit is composed of an NMOS, a PMOS, and a high voltage selection circuit; the first control signal is connected with the grid electrode of the PMOS, the second control signal is connected with the grid electrode of the NMOS, the source electrode of the NMOS is the power supply cathode of the fail-safe IO basic circuit, and the fail-safe IO basic circuit is grounded through the power supply cathode;
the PMOS is connected with the NMOS in series, namely the drain terminal of the PMOS is connected with the drain terminal of the NMOS; the serial node of the PMOS and the NMOS is a PAD end;
the source end of the PMOS is connected with the first end of a resistor R1, and the second end of the resistor R1 is a connecting end of an external power supply; a high-voltage selection circuit is further connected between the drain terminal of the PMOS and the second terminal of the resistor R1, and the bulk terminal of the PMOS is connected to the high-voltage selection circuit; the high-voltage selection circuit realizes the switching between external power supply voltage and PAD of the bulk end of the PMOS;
when latch up occurs, the N trap of the PMOS is suspended, and the parasitic of the whole failure safety IO circuit is equivalent to an N trap suspended thyristor SCR.
Furthermore, the resistance value of the resistor R1 is 5-10 omega.
Further, in a normal operating state of the circuit, the operating voltage is VDDH, the driving current output by the PMOS transistor is Iout, and the resistance value of the resistor R1 is R, so that the voltage drop formed across the resistor R1 is VR1= Iout × R, and the source voltage VDDH' = VDDH-VR1 of the PMOS transistor; the resistance R of the resistor R1 is adjusted to ensure that the voltage drop of the resistor R1 is not higher than 5% of the working voltage VDDH, and the normal work of the whole circuit is not influenced;
when the circuit generates a Latch up, assuming that the holding voltage of the Latch up is Vh and the holding current is Ih; the holding current Ih is at least 20 times the driving current Iout when Latch up occurs; a voltage drop across the parasitic SCR of VDDH '= VDDH-VR' = VDDH-Ih × R; VDDH' is less than the hold voltage Vh required for Latch up, and assuming this is true, the circuit is able to suppress Latch up.
Further, the working voltage VDDH is 5.5V, and the driving current Iout is 10 mA.
Further, when Latch up occurs, the holding current Ih is at least 200mA, and when high, an ampere-level current is reached.
Further, Latch up does not occur when the voltage drop across the parasitic SCR is lower than the holding voltage or the externally supplied current is lower than the holding current.
According to the failure safety IO circuit with high Latch up capability, a divider resistor is connected in series between a parasitic SCR and a power supply based on the mechanism of Latch up generation, and when the circuit works normally, the voltage drop formed by a small driving current on the divider resistor is extremely small and can be ignored, and the normal work of the circuit is not influenced; when it is assumed that Latch up occurs, the voltage drop generated by the large Latch up holding current across the voltage dividing resistors causes the source terminal voltage of the parasitic SCR to be lower than the Latch up holding voltage, thereby suppressing the occurrence of Latch up.
Drawings
FIG. 1 is a schematic diagram of the occurrence of a latch up.
Fig. 2 is a schematic structural diagram of a conventional failsafe IO circuit.
Fig. 3 is an equivalent circuit diagram of the circuit configuration shown in fig. 1.
Fig. 4 is a schematic structural diagram of the failsafe IO circuit of the present invention.
Fig. 5 is an equivalent circuit diagram of the structure of the present invention.
Detailed Description
The technical solutions in the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity, and the same reference numerals denote the same elements throughout. When an element or layer is referred to as being "on …," "adjacent to …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on …," "directly adjacent to …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
The invention relates to a failure safety IO circuit with high Latch up capability, which is improved aiming at the existing failure safety IO circuit, and the invention adds a series resistor R1 between a power supply and a PMOS tube on a failure safety IO basic circuit, and concretely refers to FIG. 4: the basic fail safe IO circuit comprises a first control end input interface and a second control end input interface, wherein a first control signal and a second control signal are respectively input from the control circuit through the first control end input interface and the second control end input interface to control the work of the circuit, the first control end input interface and the second control end input interface are respectively a grid electrode of a PMOS (P-channel metal oxide semiconductor) tube and a grid electrode of an NMOS (N-channel metal oxide semiconductor), and the work states of the PMOS tube and the NMOS tube are respectively controlled through the control signals.
The failure safety IO basic circuit consists of an NMOS, a PMOS and a high-voltage selection circuit; the source electrode of the NMOS is the negative electrode of the power supply of the failure safety IO basic circuit, and the failure safety IO basic circuit is grounded through the negative electrode of the power supply.
The PMOS tube is connected with the NMOS tube in series, namely the drain end of the PMOS tube is connected with the drain end of the NMOS tube to form a series node; and a PAD end of the failure safety IO basic circuit is led out from a serial node of the PMOS and the NMOS to form a signal current channel of the failure safety IO circuit.
The source end of the PMOS is connected with the first end of a resistor R1, the node voltage is VDDH', and the second end of the resistor R1 is the connecting end of an external power supply VDDH; a high-voltage selection circuit is also connected between the drain terminal of the PMOS and an external power supply VDDH, and the bulk terminal of the PMOS is also connected to the high-voltage selection circuit; the high-voltage selection circuit realizes the switching of the bulk end of the PMOS between the external power supply voltage VDDH and the PAD end.
In the failure safety IO basic circuit, the source electrode of the NMOS tube is grounded after being in short circuit with the bulk end of the NMOS tube.
When latch up occurs, the N-well of the PMOS is floating, the whole fail-safe IO circuit parasitic is equivalent to a thyristor SCR with the N-well being floating, as shown in fig. 5, the equivalent circuit is formed by the parasitic structure of the device in the circuit structure shown in fig. 4, and similarly, R0 is the equivalent resistance of the high-voltage selection circuit. When Latch up occurs, current flows from the power supply through the parasitic SCR to ground through resistor R1, the specific path being shown by the dashed arrow path in fig. 4.
In the case where Latch up occurs, Latch up occurs due to the parasitic SCR, and a certain holding voltage Vh and holding current Ih are required. Latch up does not occur when the voltage drop across the parasitic SCR is lower than its required holding voltage Vh or the externally supplied current is lower than its required holding current Ih. In the circuit structure of the invention, the series resistor R1 is used for reducing the voltage drop at the two ends of the fail safe IO output tube, so that the voltage drop is lower than the holding voltage Vh required by the Latch up, thereby inhibiting the Latch up from occurring. The resistance value of the resistor R1 is generally 5-10 Ω, and the resistance value is usually determined according to the supply voltage VDDH and the holding voltage Vh and the holding current Ih required by the latch up of the parasitic SCR device.
In normal operation, in an embodiment, assuming that the operating voltage VDDH =5.5V, the driving current output by the MOS transistor is Iout =10mA, and R1 is 10 Ω, so that the voltage drop across the external resistor R1 is VR1=10mA × 10 Ω =0.1V, VDDH' = VDDH-VR 1=5.4V, and the voltage drop across R1 is only 2% of the entire operating voltage, so that there is substantially no influence on normal operation.
Assuming that Latch-up is to occur, a holding voltage Vh of 3.5V is generally required, and a holding current Ih of about 200mA, and some large currents, even of the order of amperes, are required. Assuming Ih =200mA, then the voltage drop VDDH '= VDDH-R1 × Ih = VDDH-10 Ω × 200mA = VDDH-2V across the parasitic SCR when Latch-up occurs, still assuming the operating voltage is VDDH =5.5V, if Latch-up occurs, the voltage VDDH' across the parasitic SCR will drop from 5.4V to 3.4V. Since 3.4V is smaller than the hold voltage Vh3.5V necessary for Latch up and Latch up cannot occur, the assumption that Latch up occurs is not satisfied. Therefore, the invention does not generate Latch up under the condition, and has good inhibition effect on the Latch up.
The above are merely preferred embodiments of the present invention, and are not intended to limit the present invention. Various modifications and alterations to this invention will become apparent to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (7)
1. A fail safe IO circuit of high Latch up ability which characterized in that: includes a fail safe IO base circuit and a resistor R1;
the basic fail safe IO circuit comprises a first control end input interface and a second control end input interface, wherein a first control signal and a second control signal are respectively input from the outside through the first control end input interface and the second control end input interface so as to control the work of the circuit;
the failure safety IO basic circuit also comprises a PAD end, wherein the PAD end is a signal current channel;
the failure safety IO basic circuit also comprises a power supply anode and a power supply cathode, wherein the power supply cathode is grounded;
the positive pole of the power supply is connected to an external power supply through a resistor R1.
2. The high Latch up capable failsafe IO circuit of claim 1, wherein: the failure safety IO basic circuit consists of an NMOS, a PMOS and a high-voltage selection circuit; the first control signal is connected with the grid electrode of the PMOS, the second control signal is connected with the grid electrode of the NMOS, the source electrode of the NMOS is the power supply cathode of the fail-safe IO basic circuit, and the fail-safe IO basic circuit is grounded through the power supply cathode;
the PMOS is connected with the NMOS in series, namely the drain terminal of the PMOS is connected with the drain terminal of the NMOS; the serial node of the PMOS and the NMOS is a PAD end;
the source end of the PMOS is connected with the first end of a resistor R1, and the second end of the resistor R1 is a connecting end of an external power supply; a high-voltage selection circuit is further connected between the drain terminal of the PMOS and the second terminal of the resistor R1, and the bulk terminal of the PMOS is connected to the high-voltage selection circuit; the high-voltage selection circuit realizes the switching between external power supply voltage and PAD of the bulk end of the PMOS;
when latch up occurs, the N trap of the PMOS is suspended, and the parasitic of the whole failure safety IO circuit is equivalent to an N trap suspended thyristor SCR.
3. The high Latch up capable failsafe IO circuit of claim 1, wherein: the resistance value of the resistor R1 is 5-10 omega.
4. The high Latch up capable failsafe IO circuit of claim 2, wherein: under the normal working state of the circuit, the working voltage is VDDH, the driving current output by the PMOS tube is Iout, and the resistance value of the resistor R1 is R, so that the voltage drop formed on the resistor R1 is VR1= Iout R, and the source voltage VDDH' = VDDH-VR1 of the PMOS tube; the resistance R of the resistor R1 is adjusted to ensure that the voltage drop of the resistor R1 is not higher than 5% of the working voltage VDDH, and the normal work of the whole circuit is not influenced;
when the circuit generates a Latch up, assuming that the holding voltage of the Latch up is Vh and the holding current is Ih; the holding current Ih is at least 20 times the driving current Iout when Latch up occurs; a voltage drop across the parasitic SCR of VDDH '= VDDH-VR' = VDDH-Ih × R; VDDH' is less than the hold voltage Vh required for Latch up, and assuming this is true, the circuit is able to suppress Latch up.
5. The high Latch up capable failsafe IO circuit of claim 4 wherein: the working voltage VDDH is 5.5V, and the driving current Iout is 10 mA.
6. The high Latch up capable failsafe IO circuit of claim 4 wherein: when Latch up occurs, the holding current Ih is at least 200mA, and when the holding current Ih is high, ampere-level current is achieved.
7. The high Latch up capable failsafe IO circuit of claim 4 wherein: latch up does not occur when the voltage drop across the parasitic SCR is lower than the holding voltage or the externally supplied current is lower than the holding current.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110346098.6A CN112952789A (en) | 2021-03-31 | 2021-03-31 | High Latch up capability fail safe IO circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110346098.6A CN112952789A (en) | 2021-03-31 | 2021-03-31 | High Latch up capability fail safe IO circuit |
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Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5159204A (en) * | 1987-11-18 | 1992-10-27 | Bernacchi Jerald R | Structure and method for preventing latch-up in integrated circuits |
| US20010015656A1 (en) * | 2000-02-22 | 2001-08-23 | Nobuaki Tsuji | Buffer circuit |
| TW506111B (en) * | 2001-07-25 | 2002-10-11 | United Microelectronics Corp | On-chip ESD protection circuits with substrate-triggered SCR device |
| CN1805142A (en) * | 2005-12-07 | 2006-07-19 | 威盛电子股份有限公司 | Electrostatic discharge protective circuit and relevant techniques |
| JP2008259420A (en) * | 1996-07-29 | 2008-10-23 | Hynix Semiconductor Inc | Charge pump for semiconductor substrate |
| US20100314709A1 (en) * | 2009-06-12 | 2010-12-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Latch-up prevention structure and method for ultra-small high voltage tolerant cell |
| CN102064815A (en) * | 2009-11-18 | 2011-05-18 | 上海宏力半导体制造有限公司 | Latch-up resistant circuit |
| JP2013131771A (en) * | 2013-02-11 | 2013-07-04 | Renesas Electronics Corp | Semiconductor integrated circuit |
| JP2014053497A (en) * | 2012-09-07 | 2014-03-20 | Toshiba Corp | Esd protection circuit |
| CN103839941A (en) * | 2012-11-20 | 2014-06-04 | 美国亚德诺半导体公司 | Junction-isolated blocking voltage devices with integrated protection structures and methods of forming same |
| US20150318692A1 (en) * | 2014-05-02 | 2015-11-05 | National Chiao Tung University | Active guard ring structure to improve latch-up immunity |
| CN105609541A (en) * | 2014-11-18 | 2016-05-25 | 美国亚德诺半导体公司 | Apparatus and methods for transceiver interface overvoltage clamping |
-
2021
- 2021-03-31 CN CN202110346098.6A patent/CN112952789A/en active Pending
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5159204A (en) * | 1987-11-18 | 1992-10-27 | Bernacchi Jerald R | Structure and method for preventing latch-up in integrated circuits |
| JP2008259420A (en) * | 1996-07-29 | 2008-10-23 | Hynix Semiconductor Inc | Charge pump for semiconductor substrate |
| US20010015656A1 (en) * | 2000-02-22 | 2001-08-23 | Nobuaki Tsuji | Buffer circuit |
| TW506111B (en) * | 2001-07-25 | 2002-10-11 | United Microelectronics Corp | On-chip ESD protection circuits with substrate-triggered SCR device |
| CN1805142A (en) * | 2005-12-07 | 2006-07-19 | 威盛电子股份有限公司 | Electrostatic discharge protective circuit and relevant techniques |
| US20100314709A1 (en) * | 2009-06-12 | 2010-12-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Latch-up prevention structure and method for ultra-small high voltage tolerant cell |
| CN102064815A (en) * | 2009-11-18 | 2011-05-18 | 上海宏力半导体制造有限公司 | Latch-up resistant circuit |
| JP2014053497A (en) * | 2012-09-07 | 2014-03-20 | Toshiba Corp | Esd protection circuit |
| CN103839941A (en) * | 2012-11-20 | 2014-06-04 | 美国亚德诺半导体公司 | Junction-isolated blocking voltage devices with integrated protection structures and methods of forming same |
| JP2013131771A (en) * | 2013-02-11 | 2013-07-04 | Renesas Electronics Corp | Semiconductor integrated circuit |
| US20150318692A1 (en) * | 2014-05-02 | 2015-11-05 | National Chiao Tung University | Active guard ring structure to improve latch-up immunity |
| CN105609541A (en) * | 2014-11-18 | 2016-05-25 | 美国亚德诺半导体公司 | Apparatus and methods for transceiver interface overvoltage clamping |
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