CN112951989A - Preparation method of memristor combined type cross array - Google Patents
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- 238000002360 preparation method Methods 0.000 title claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 238000000151 deposition Methods 0.000 claims abstract description 14
- 229910052751 metal Inorganic materials 0.000 claims abstract description 14
- 239000002184 metal Substances 0.000 claims abstract description 14
- 230000008859 change Effects 0.000 claims abstract description 11
- 238000005289 physical deposition Methods 0.000 claims abstract description 6
- 238000005234 chemical deposition Methods 0.000 claims abstract description 4
- 238000007781 pre-processing Methods 0.000 claims abstract description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 12
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 10
- 239000010936 titanium Substances 0.000 claims description 10
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 claims description 8
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 8
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 8
- 229910052719 titanium Inorganic materials 0.000 claims description 8
- 230000008021 deposition Effects 0.000 claims description 7
- 238000004140 cleaning Methods 0.000 claims description 6
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 claims description 4
- 239000008367 deionised water Substances 0.000 claims description 4
- 229910021641 deionized water Inorganic materials 0.000 claims description 4
- 229910052757 nitrogen Inorganic materials 0.000 claims description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 4
- 238000001035 drying Methods 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 claims 1
- 238000000059 patterning Methods 0.000 claims 1
- 238000004506 ultrasonic cleaning Methods 0.000 claims 1
- 238000001259 photo etching Methods 0.000 abstract description 8
- 238000005516 engineering process Methods 0.000 abstract description 5
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 238000004544 sputter deposition Methods 0.000 description 31
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 18
- 239000013077 target material Substances 0.000 description 12
- 229910052786 argon Inorganic materials 0.000 description 9
- 239000007789 gas Substances 0.000 description 7
- 230000000052 comparative effect Effects 0.000 description 6
- 238000005086 pumping Methods 0.000 description 6
- 230000003956 synaptic plasticity Effects 0.000 description 6
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 6
- 229910052697 platinum Inorganic materials 0.000 description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 210000000225 synapse Anatomy 0.000 description 4
- 229910052715 tantalum Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910003070 TaOx Inorganic materials 0.000 description 2
- 238000013528 artificial neural network Methods 0.000 description 2
- 210000004556 brain Anatomy 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 210000005036 nerve Anatomy 0.000 description 1
- 210000002569 neuron Anatomy 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention belongs to the field of semiconductor device preparation, and particularly relates to a preparation method of a memristor combined type cross array. The preparation method comprises the following steps: (1) sequentially depositing a bottom electrode, a resistance change layer and a top electrode on a substrate to obtain a plurality of single-device memristors; (2) performing electrical preprocessing on each single-device memristor; (3) and depositing metal on the substrate, and connecting the single-device memristors through the metal to obtain the memristor cross array. According to the preparation method, the memristors of a large number of crossed electrodes are firstly prepared by adopting a photoetching technology and a physical or chemical deposition technology, and each device is subjected to electrical pretreatment to obtain the stable state of a single device, so that the influence caused by large voltage of the electrical pretreatment is avoided, and the device is simple in structure, good in performance and stable.
Description
Technical Field
The invention belongs to the field of semiconductor device preparation, and particularly relates to a preparation method of a memristor combined type cross array.
Background
Since the first preparation of memristors in 2008 by Hewlett packard laboratory, memristors have become the field of information storage and brain-like computing in recent yearsIs a hot point of research. It is well known that the human brain is composed of about 1011One neuron passes through 1015The synapses are interconnected to form a complex neural network with information storage and computation functions. At present, a single memristor can replace a CMOS device formed by combining dozens of transistors and capacitors, and the functional simulation of the nerve synapse is realized. However, a single memristor is only limited to function simulation of a single synapse, and a corresponding memristor array is composed of more devices, so that the density of an artificial neural network can be improved, and more brain calculation functions can be operated.
In the conductive filament type memristor, the initial resistance value of the device is high, and the device needs to be electrically preprocessed to form a stable and adjustable conductive filament, so that a stable resistance change phenomenon is generated. Generally, the voltage of electrical pretreatment is large, so that unrecoverable damage is easily caused to devices, and the direct electrical pretreatment of the devices in the array can affect other parallel devices, so that the performance of the devices in the array is unstable. Compared with the method of directly preparing the memristor cross array and then performing electric pretreatment, the method of preparing the memristor cross array by firstly performing electric pretreatment on a single device to obtain a stable-performance device and then connecting the single device avoids the influence caused by large voltage of the electric pretreatment, and simultaneously can select the stable-performance device to perform electrode connection combination to realize the high-density memristor array. The method has great prospective significance in application of the technology to preparation and function development of memristor arrays.
Disclosure of Invention
The invention aims to provide a method for preparing a memristor cross array by first electrically pretreating a memristor and then connecting electrodes, so that the influence caused by large voltage of electrical pretreatment is avoided, and the device is simple in structure, good in performance and stable. The detailed technical scheme of the invention is as follows.
A preparation method of a memristor combined type cross array comprises the following steps:
(1) sequentially depositing a bottom electrode, a resistance change layer and a top electrode on a substrate to obtain a plurality of single-device memristors;
(2) performing electrical preprocessing on each single-device memristor;
(3) and depositing metal on the substrate, and connecting the single-device memristors through the metal to obtain the memristor cross array.
Preferably, the deposition in step (1) refers to physical deposition or chemical deposition, and the deposition refers to photolithography on the substrate and then deposition in the pattern area.
Preferably, the pattern is developed by a developer using a photolithographic technique.
Preferably, in step (1), projections of the top electrode and the bottom electrode on the substrate are perpendicular to each other, so as to form a single-device memristor with orthogonally crossed electrodes.
Preferably, the physical deposition method is magnetron sputtering.
Preferably, in the electrical pretreatment in step (2), a forward scan or pulse voltage is applied to the top electrode, and the bottom electrode is grounded, so that stable resistance change performance is obtained.
Preferably, the substrate is cleaned before deposition, wherein the cleaning is to sequentially put the substrate into acetone, alcohol and deionized water, respectively ultrasonically clean the substrate for 10-20 minutes, circulate the substrate for a plurality of times, and blow-dry the substrate with nitrogen for later use.
Preferably, the metal in the step (3) is one of titanium metal and platinum metal or a mixture of two metals.
The invention has the following beneficial effects:
(1) according to the preparation method of the memristor combined type cross array, the memristors of a large number of cross electrodes are firstly prepared by adopting a photoetching technology and a physical or chemical deposition technology, each device is subjected to electrical pretreatment, the stable state of a single device is obtained, the array with stable performance is manufactured, the influence caused by large voltage of the electrical pretreatment is avoided, and the device is simple in structure, good in performance and stable.
(2) The preparation method can expand the construction scheme of the memristor array, has a simple device structure and good and stable performance, and has a good application prospect in improving the performance stability and function development of the memristor array.
Drawings
FIG. 1 is a top plan view of a single device memristor in embodiment 1 of the present disclosure;
FIG. 2 is a top plan view of a memristor crossbar array after connecting electrodes in example 1 of the present disclosure;
FIG. 3 is a current-voltage (I-V) curve of a single device memristor electrical preconditioning in example 1 of the present disclosure;
FIG. 4 is a device simulated synaptic plasticity curve for a memristor crossbar array in example 1 of the present disclosure.
FIG. 5 is a device simulated synaptic plasticity curve for a memristor crossbar array in comparative example 1.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
Example 1
The preparation method of the memristor array comprises the following steps:
(1) substrate cleaning treatment: sequentially putting the silicon wafer into acetone, alcohol and deionized water, respectively ultrasonically cleaning for 10 minutes, circulating for 3 times, and drying by using nitrogen;
(2) preparing a bottom electrode: after photoetching a bottom electrode pattern on a substrate, placing the substrate on a tray of a magnetron sputtering cavity, respectively mounting a titanium target material and a platinum target material on a target source of the cavity, and pumping the background vacuum degree of the cavity to be less than 2 multiplied by 10- 6Torr, introducing argon with the purity of 99.999 percent as working gas, wherein the sputtering pressure is 3mTorr, the sputtering power of titanium metal is 90W, the sputtering time is 10 minutes, and the thickness is 5 nm; the sputtering power of the platinum metal is 45W, the sputtering time is 10 minutes, and the thickness is 15 nm;
(3) preparing a resistance change layer: lithography resist on a substrateAfter changing the layer pattern, the substrate is placed on a tray of a magnetron sputtering cavity, a tantalum target material is arranged on a target source of the cavity, and the background vacuum degree of the cavity is pumped to be less than 2 multiplied by 10-6Torr, introducing argon and oxygen as working gas, wherein the flow ratio of argon to oxygen is 12:2, the sputtering pressure is 10mTorr, the sputtering power is 140W, the sputtering time is 25 minutes, and the thickness is 20 nm;
(4) preparing a top electrode: after photoetching a top electrode pattern on a substrate, placing the substrate on a tray of a magnetron sputtering cavity, respectively mounting a tantalum target material and a platinum target material on a target source of the cavity, and pumping the background vacuum degree of the cavity to be less than 2 multiplied by 10- 6Torr, introducing argon with the purity of 99.999 percent as working gas, the sputtering pressure is 3mTorr, the sputtering power of tantalum metal is 80W, the sputtering time is 20 minutes, and the thickness is 40 nm; the sputtering power of the platinum metal is 45W, the sputtering time is 20 minutes, the thickness is 50nm, and a device with the structure of Ti/Pt/TaOx/Ta/Pt is prepared to obtain the single-device memristor.
(5) Single device memristor electrical preconditioning: forward scanning is applied to the top electrode by adopting a Gisley 4200 semiconductor tester, the bottom electrode is grounded, and each single-device memristor is subjected to electrical pretreatment to obtain stable resistance change performance;
(6) preparing a memristor cross array: photoetching a connecting electrode pattern on a substrate, placing the substrate on a tray of a magnetron sputtering cavity, respectively mounting a titanium target material and a platinum target material on a target source of the magnetron sputtering cavity, and pumping the background vacuum degree of the cavity to be less than 2 x 10-6Torr, introducing argon with the purity of 99.999 percent as working gas, wherein the sputtering pressure is 3mTorr, the sputtering power of titanium metal is 90W, the sputtering time is 35 minutes, and the thickness is 20 nm; the sputtering power of the platinum metal was 45W, the sputtering time was 15 minutes, and the thickness was 30 nm.
Comparative example 1
Comparative example 1 a crossbar array was obtained and then electrically pretreated, comprising the following steps:
(1) substrate cleaning treatment: sequentially putting the silicon wafer into acetone, alcohol and deionized water, respectively ultrasonically cleaning for 10 minutes, circulating for 3 times, and drying by using nitrogen;
(2) preparing a bottom electrode: after photoetching a bottom electrode pattern on a substrate, placing the substrate on a tray of a magnetron sputtering cavity, respectively mounting a titanium target material and a platinum target material on a target source of the cavity, and pumping the background vacuum degree of the cavity to be less than 2 multiplied by 10- 6Torr, introducing argon with the purity of 99.999 percent as working gas, wherein the sputtering pressure is 3mTorr, the sputtering power of titanium metal is 90W, the sputtering time is 10 minutes, and the thickness is 5 nm; the sputtering power of the platinum metal is 45W, the sputtering time is 10 minutes, and the thickness is 15 nm;
(3) preparing a resistance change layer: photoetching a resistance-change layer pattern on a substrate, placing the substrate on a tray of a magnetron sputtering cavity, mounting a tantalum target material on a target source of the cavity, and pumping the background vacuum degree of the cavity to be less than 2 multiplied by 10-6Torr, introducing argon and oxygen as working gas, wherein the flow ratio of argon to oxygen is 12:2, the sputtering pressure is 10mTorr, the sputtering power is 140W, the sputtering time is 25 minutes, and the thickness is 20 nm;
(4) preparing a top electrode: after photoetching a top electrode pattern on a substrate, placing the substrate on a tray of a magnetron sputtering cavity, respectively mounting a tantalum target material and a platinum target material on a target source of the cavity, and pumping the background vacuum degree of the cavity to be less than 2 multiplied by 10- 6Torr, introducing argon with the purity of 99.999 percent as working gas, the sputtering pressure is 3mTorr, the sputtering power of tantalum metal is 80W, the sputtering time is 20 minutes, and the thickness is 40 nm; the sputtering power of the platinum metal is 45W, the sputtering time is 20 minutes, the thickness is 50nm, a device with the structure of Ti/Pt/TaOx/Ta/Pt is prepared, and the memristor cross array is obtained.
(5) Memristor electrical preprocessing: and applying forward scanning on the top electrode by adopting a Gisley 4200 semiconductor tester, grounding the bottom electrode, and performing electrical pretreatment on each single-device memristor to obtain the resistance change performance.
Fig. 1 is a plan top view of a single device memristor in embodiment 1 of the present disclosure. TE is the top electrode and BE is the bottom electrode.
FIG. 2 is a top plan view of a memristor crossbar array after connecting electrodes in example 1 of the present disclosure. The top plan view of the memristor crossbar array prepared directly in the comparative example is identical to the top plan view of inventive example 1.
FIG. 3 is a current-voltage (I-V) curve of a single device memristor electrical preconditioning in example 1 of the present disclosure. In fig. 3, the forming is the electrical pretreatment, and 1st is the resistance change performance of the memristor in the first turn after the electrical pretreatment, so that it can be known that the single-device memristor with stable performance is obtained through the electrical pretreatment.
FIG. 4 is a device simulated synaptic plasticity curve for a memristor crossbar array in example 1 of the present disclosure.
The device simulates a synaptic plasticity curve by applying the pulse excitation parameters shown in the figure to the top electrode and grounding the bottom electrode. The device conductance value is read by a read pulse (0.2V,10 μ s) after each actuation. Location is the increase in conductance and suppression is the decrease in conductance.
It can be seen from fig. 4 that the devices in the prepared memristor crossbar array can well simulate some functions of synapses.
FIG. 5 is a device simulated synaptic plasticity curve for a memristor crossbar array in comparative example 1. As can be seen from FIG. 5, the conductance perturbation is severe and the randomness is too large to simulate synaptic plasticity. This is because the initial difference between devices is a common phenomenon in the preparation process of the memristor at present, and when one device in the array is electrically preprocessed, the large voltage damages the devices with large difference around.
The usable yield of the array prepared by the method is more than 90%, while the peripheral devices of the comparative example are easily influenced by large voltage of electric pretreatment, and the yield is lower and less than 20%.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (8)
1. A preparation method of a memristor combined type cross array is characterized by comprising the following steps:
(1) sequentially depositing a bottom electrode, a resistance change layer and a top electrode on a substrate to obtain a plurality of single-device memristors;
(2) performing electrical preprocessing on each single-device memristor;
(3) and depositing metal on the substrate, and connecting the single-device memristors through the metal to obtain the memristor cross array.
2. The method according to claim 1, wherein the deposition in step (1) is physical deposition or chemical deposition, and the deposition is performed by first patterning a substrate and then depositing in a pattern region.
3. A method of manufacturing as claimed in claim 2, wherein the pattern is produced by developing with a developer using a photolithographic technique.
4. The method for preparing the memory resistor, according to claim 2 or 3, wherein in the step (1), the projections of the top electrode and the bottom electrode on the substrate are mutually at right angles, so that the single-device memory resistor with orthogonal crossed electrodes is formed.
5. The method of claim 2, wherein the physical deposition method is magnetron sputtering.
6. The method according to claim 1 or 2, wherein the electrical pretreatment in step (2) is to apply a forward scan or pulse voltage to the top electrode and ground the bottom electrode to obtain stable resistance change performance.
7. The preparation method of claim 1, wherein the substrate is cleaned before deposition, and the cleaning is carried out by sequentially placing the substrate into acetone, alcohol and deionized water, respectively carrying out ultrasonic cleaning for 10-20 minutes, circulating for several times, and drying with nitrogen for standby.
8. The method according to claim 1, wherein the metal in step (3) is one or a mixture of two of titanium metal and platinum metal.
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| CN113793881A (en) * | 2021-09-16 | 2021-12-14 | 中国科学院半导体研究所 | Photoelectric synapse device array, preparation method thereof and image processing equipment |
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| CN105529399A (en) * | 2016-01-27 | 2016-04-27 | 电子科技大学 | Multielement metal oxide thin film based resistive random access memory and preparation method therefor |
| CN106098936A (en) * | 2016-07-26 | 2016-11-09 | 福州大学 | A kind of memristor and the method strengthening its electronic synapse function |
| CN106654009A (en) * | 2016-12-19 | 2017-05-10 | 中国科学院宁波材料技术与工程研究所 | Memristor and application thereof |
| CN110600498A (en) * | 2019-08-21 | 2019-12-20 | 复旦大学 | Preparation method of memristor cross array |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105529399A (en) * | 2016-01-27 | 2016-04-27 | 电子科技大学 | Multielement metal oxide thin film based resistive random access memory and preparation method therefor |
| CN106098936A (en) * | 2016-07-26 | 2016-11-09 | 福州大学 | A kind of memristor and the method strengthening its electronic synapse function |
| CN106654009A (en) * | 2016-12-19 | 2017-05-10 | 中国科学院宁波材料技术与工程研究所 | Memristor and application thereof |
| CN110600498A (en) * | 2019-08-21 | 2019-12-20 | 复旦大学 | Preparation method of memristor cross array |
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| CN113793881A (en) * | 2021-09-16 | 2021-12-14 | 中国科学院半导体研究所 | Photoelectric synapse device array, preparation method thereof and image processing equipment |
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