CN112951923B - Method and device for improving surface mobility of silicon carbide transverse double-diffusion field effect tube - Google Patents
Method and device for improving surface mobility of silicon carbide transverse double-diffusion field effect tube Download PDFInfo
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- 230000005669 field effect Effects 0.000 title claims abstract description 15
- 238000000034 method Methods 0.000 title abstract description 16
- 238000009792 diffusion process Methods 0.000 title abstract description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 79
- 229920005591 polysilicon Polymers 0.000 claims abstract description 73
- 238000002347 injection Methods 0.000 claims abstract description 36
- 239000007924 injection Substances 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000002955 isolation Methods 0.000 claims abstract description 9
- 229910052751 metal Inorganic materials 0.000 claims description 11
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- 108090000699 N-Type Calcium Channels Proteins 0.000 description 2
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- 238000003949 trap density measurement Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/404—Multiple field plate structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7817—Lateral DMOS transistors, i.e. LDMOS transistors structurally associated with at least one other device
- H01L29/7818—Lateral DMOS transistors, i.e. LDMOS transistors structurally associated with at least one other device the other device being a pn-junction diode
Abstract
A method and device for improving the surface mobility of a silicon carbide transverse double-diffusion field effect transistor (LDMOS) introduce a voltage bias tube, so that the surface electron concentration of a drift region is increased when the silicon carbide LDMOS is conducted in a forward direction, the probability that a single electron is captured by a surface trap of an oxide layer above the drift region is reduced, and the electron mobility is improved; the device comprises a P-type substrate, wherein a P-type isolation layer is arranged on the P-type substrate and divides the device into an LDMOS and a voltage bias tube. The LDMOS comprises a first N-type drift region, a first source region, a first drain region, a gate oxide layer and a polysilicon gate, and is characterized in that 4 polysilicon field plates which are mutually separated are arranged on the gate oxide layer. The voltage bias tube comprises a second N-type drift region, a second source region and a second drain region, and 4N + injection layers are arranged in the second N-type drift region. The polysilicon gate is connected with the second source region, the first drain region is connected with the second drain region, and the 4 polysilicon field plates are respectively connected with the 4N + injection layers.
Description
Technical Field
The invention mainly relates to the technical field of wide bandgap power semiconductor devices, in particular to a method and a device for improving the surface mobility of a silicon carbide transverse double-diffusion field effect transistor, which are suitable for various power control processing fields such as a switching power supply, an inverter and the like and used for reducing the on-state loss of the device under the condition of forward conduction.
Background
A Double-diffused metal oxide semiconductor field effect transistor (DMOS) has characteristics of large current, high voltage resistance, high switching speed, and the like. The method is widely applied to the fields of switch power supplies, household appliances, smart grids, traffic transmission and the like. There are two main types of DMOS, Vertical Double-diffused MOSFET (Vertical Double-diffused MOSFET) and Lateral Double-diffused MOSFET (Lateral Double-diffused MOSFET), where LDMOS is more widely used due to its easier compatibility with CMOS processes.
In recent years, silicon carbide (SiC) material, one of the third generation wide bandgap semiconductors, has been gradually substituted for silicon-based material as an ideal choice for producing high-voltage power electronic devices of the energy-saving type due to its advantages of high breakdown field strength and high thermal conductivity. Fig. 1 shows a conventional silicon carbide LDMOS, comprising: the semiconductor device comprises a P-type substrate, wherein an N-type drift region is arranged on the P-type substrate, a P-type base region and an N-type drain region are arranged in the N-type drift region, an N-type source region is arranged in the P-type base region, a gate oxide layer is arranged on the surface of the N-type drift region, a polysilicon gate is arranged on the upper surface of the gate oxide layer, and metal is connected to the source region and the drain region. When a sufficiently large positive voltage is applied to the polysilicon gate, an inversion channel is formed on the upper surface of the P-type base region, and when a voltage difference exists between the source electrode and the drain electrode, electrons can be injected into the N-type drift region from the N + type active region through the channel and are finally extracted by the drain electrode to form a current. However, as the current path of the silicon carbide LDMOS is below the oxide layer, the surface trap in the oxide layer can reduce the mobility of the carrier and affect the carrier transport, so that the conventional silicon carbide LDMOS has high on-resistance and poor forward on-characteristic.
Disclosure of Invention
The invention provides a method and a device for improving the surface mobility of a silicon carbide transverse double-diffusion field effect transistor, aiming at the problems.
The invention adopts the following technical scheme:
the method for improving the surface mobility of the silicon carbide transverse double-diffusion field effect transistor introduces a voltage bias tube, and when the silicon carbide LDMOS transistor is conducted in the forward direction, the high voltage of a drift region of the voltage bias tube can be transmitted to a plurality of polysilicon field plates above the surface of the drift region of the silicon carbide LDMOS transistor through metal. The high voltage on the polysilicon field plate has the function of attracting electrons, so that electrons on the surface of the LDMOS drift region are gathered, the electron concentration is improved, the probability of capturing a single electron by a trap on the surface of an oxide layer above the drift region is reduced, and the electron mobility is improved.
The invention relates to a device for improving the surface mobility of a silicon carbide transverse double-diffusion field effect transistor, which comprises: a P-type substrate, an N-type drift region disposed on the P-type substrate, a P-type isolation layer disposed in the N-type drift region and divided into a first N-type drift region and a second N-type drift region by the P-type isolation layer, a first P-type base region and a first N-type buffer layer are respectively arranged on the first N-type drift region, a P + source region and an N + source region which are connected are arranged in the first P-type base region, an N + drain region is arranged in the first N-type buffer layer, a gate oxide layer is arranged above the first N-type drift region, the left end of the gate oxide layer extends into the upper part of the P-type base region and is stopped at the right boundary of the N + source region, a polysilicon gate is arranged on the gate oxide layer, the right end of the gate oxide layer extends into the upper part of the first N-type buffer layer, a polysilicon field plate separated from the polysilicon gate is arranged on the gate oxide layer and is positioned between the polysilicon gate and the first N-type buffer layer; a second P-type base region and a second N-type buffer layer are respectively arranged on the second N-type drift region, a P source is arranged in the second P-type base region, a P drain is arranged in the second N-type buffer layer, an N + injection layer is arranged in the second N-type drift region, and the N + injection layer is positioned between the second P-type base region and the second N-type buffer layer; the P source is electrically connected with the polysilicon gate, the N + injection layer is electrically connected with the polysilicon field plate, and the P drain is electrically connected with the N + drain region.
Conventional methods for increasing carrier mobility in silicon carbide devices have mainly used additional process steps to reduce the surface trap density at the interface between the silicon carbide and the oxide layer, or used other materials to replace the silicon carbide (e.g., polysilicon material) where contact with the oxide layer is required to reduce the surface trap density at the interface. These methods all place a burden on the manufacturing process. Compared with the prior art, the invention has the following advantages:
under the same conditions, the characteristic on-resistance of the structure is reduced, the current capability is enhanced, and compared with the conventional structure, the current capability of the structure is improved by 76.29 percent (shown in figure 6) compared with the conventional structure under the condition that the forward conduction voltage drop is 1V. The innovation point of the invention is to research the influence of the surface mobility of the device on the performance of the device and provide a method for improving the surface mobility of the device. The structure of the invention is divided into two parts according to the function, one part is LDMOS with a plurality of polysilicon field plates, and the other part is a voltage bias tube. The voltage bias tube is composed of two reverse diodes, the first diode is composed of a second P-type base region 9 and a second N-type drift region 2b, and the second diode is composed of a second N-type buffer layer 10 and a P drain 12. The source electrode of the voltage bias tube is electrically connected with the polycrystalline silicon grid electrode of the LDMOS through metal, the drain electrode of the voltage bias tube is electrically connected with the drain electrode of the LDMOS, and the first to fourth N + injection layers on the upper surface of the drift region are respectively electrically connected with the first to fourth polycrystalline silicon field plates of the field effect tube through metal. The voltage bias tube is used for providing positive bias voltage for the polycrystalline silicon field plate of the LDMOS, so that electrons are gathered on the surface of the drift region below the polycrystalline silicon field plate, the electron concentration on the surface of the drift region is increased, the probability that a single electron on the surface of the drift region is captured by a trap on the surface of the oxidation layer is reduced, and the electron mobility is increased.
In the voltage bias tube, a PN junction is formed by the second N-type buffer layer 10 and the P drain, and a PN junction is formed by the second P-type base region 9 and the second N-type drift region 2 b; the voltage bias tube has two diodes in opposite directions. When the device works, a positive voltage is applied to the polysilicon gate of the LDMOS and the source electrode of the voltage bias tube, and the P-type base region in the LDMOS forms an N-type channel. Then, a positive voltage is applied to the drain of the LDMOS and the voltage bias tube, and at this time, no matter the drain voltage of the voltage bias tube is high and the source voltage is high, two PN junctions are positively biased one by one and reversely biased, and the drift region voltage is always approximately equal to the voltage of the higher voltage of the source or the drain minus the forward conduction voltage of the PN junction.
The N + injection layer on the N-type drift region forms ohmic contact with metal, the drift region voltage is transmitted to the first to fourth polysilicon field plates of the LDMOS through the metal, which is equivalent to applying a plurality of positive bias voltages above the N-type drift region of the LDMOS, so that electrons are accumulated on the surface of the N-type drift region (as shown in fig. 4), and the electron concentration on the current path of the LDMOS is increased (as shown in fig. 7). The electron concentration on the current path is increased, so that the probability that each electron is trapped by the surface trap of the oxide layer above the drift region is reduced, and the electron mobility on the surface of the drift region is increased. Due to the spacing distribution of the polysilicon field plates, the electron mobility of the surface of the N-type drift region under the polysilicon field plates is larger than that of the surface of the N-type drift region under the gaps of the polysilicon field plates, so that the electron mobility is distributed in a vertically fluctuating way (as shown in FIG. 8). The dual effect of the increased electron concentration and increased electron mobility in the current path results in a reduced characteristic on-resistance of the device and an increased current capability.
In the LDMOS transistor, a plurality of polysilicon field plates which are distributed at equal intervals are used instead of a continuous polysilicon field plate, and the purpose is to ensure that the breakdown voltage of the silicon carbide lateral double-diffusion metal oxide semiconductor field effect transistor with high surface mobility is not reduced. When the polycrystalline silicon field plates are used in an off state, the drift region below the polycrystalline silicon field plates is almost equipotential, so that the area of the drift region capable of resisting the voltage is reduced, and the breakdown voltage is reduced sharply.
Drawings
Fig. 1 is a cross-sectional view of a conventional structure.
Figure 2 shows a three-dimensional view of the structure of the present invention.
FIG. 3 is a cross-sectional view of a voltage bias tube of the present invention.
Fig. 4 shows the working principle of the present invention.
Fig. 5 shows a method flow diagram.
Fig. 6 is a diagram comparing the structure of the present invention with the conventional structure IV.
FIG. 7 is a graph showing a comparison of electron concentration in the current path between the structure of the present invention and the conventional structure.
FIG. 8 is a graph showing the electron mobility comparison between the structure of the present invention and the conventional structure.
Detailed Description
Example 1
A method for improving the surface mobility of a silicon carbide transverse double-diffusion field effect transistor introduces a voltage bias tube, and when a silicon carbide LDMOS transistor is conducted in the forward direction, the high voltage of a drift region of the voltage bias tube can be transmitted to a plurality of polysilicon field plates above the surface of the drift region of the silicon carbide LDMOS transistor through metal. The high voltage on the polysilicon field plate has the function of attracting electrons, so that electrons on the surface of the drift region of the LDMOS tube are gathered, the electron concentration is improved, the probability that a single electron is captured by a trap on the surface of an oxide layer above the drift region is reduced, and the electron mobility is improved.
Example 2
In general, the high surface mobility silicon carbide lateral double diffused metal oxide semiconductor field effect transistor of the present invention consists of an LDMOS with multiple polysilicon field plates and a voltage bias transistor.
The invention is described in detail below with reference to fig. 2 and 3:
a device used for the method for improving the surface mobility of the silicon carbide lateral double-diffused field effect transistor comprises the following steps: the structure comprises a P-type substrate 1, wherein an N-type drift region 2 is arranged on the P-type substrate 1, a P-type isolation layer 3 is arranged in the N-type drift region 2 and is divided into a first N-type drift region 2a and a second N-type drift region 2b by the P-type isolation layer 3, a first P-type base region 4 and a first N-type buffer layer 7 are respectively arranged on the first N-type drift region 2a, a P + source region 5 and an N + source region 6 which are connected are arranged in the first P-type base region 4, an N + drain region 8 is arranged in the first N-type buffer layer 7, a gate oxide layer 22 is arranged above the first N-type drift region 2a, one end of the gate oxide layer 22 extends into the upper part of the P-type base region 4 and is stopped at the boundary of the N + source region 6, and a polysilicon gate 17 is arranged on the gate oxide layer 22, so that a silicon carbide transverse double-diffusion metal oxide field effect transistor is formed; a polysilicon field plate separated from the polysilicon gate 17 is further arranged on the gate oxide layer 22 and is positioned between the polysilicon gate 17 and the first N-type buffer layer 7; a second P-type base region 9 and a second N-type buffer layer 10 are respectively arranged on the second N-type drift region 2b, a P source 11 is arranged in the second P-type base region 9, and a P drain 12 is arranged in the second N-type buffer layer 10, so that a voltage bias tube is formed; an N + injection layer is arranged in the second N-type drift region 2b and is positioned between the second P-type base region 9 and the second N-type buffer layer 10; the P source 11 is electrically connected to the polysilicon gate 17, the N + injection layer is electrically connected to the polysilicon field plate, and the P drain 12 is electrically connected to the N + drain region 8. Finally, an oxide layer 30 is applied over the entire device.
In this embodiment, the P source 11 and the polysilicon gate 17 are electrically connected, and the P drain 12 and the N + drain region 8 are electrically connected through metals 23 and 29, respectively.
The other end of the gate oxide layer 22 can extend into the upper part of the first N- type buffer layer 7, and 4 mutually separated polysilicon field plates, namely a first polysilicon field plate 18, a second polysilicon field plate 19, a third polysilicon field plate 20 and a fourth polysilicon field plate 21, are arranged on the gate oxide layer 22; 4N + injection layers are arranged in the second N-type drift region 2b, and are respectively a first N + injection layer 13, a second N + injection layer 14, a third N + injection layer 15 and a fourth N + injection layer 16; the first polysilicon field plate 18, the second polysilicon field plate 19, the third polysilicon field plate 20 and the fourth polysilicon field plate 21 are respectively electrically connected with the first N + injection layer 13, the second N + injection layer 14, the third N + injection layer 15 and the fourth N + injection layer 16, and more specifically, the first polysilicon field plate 18, the second polysilicon field plate 19, the third polysilicon field plate 20 and the fourth polysilicon field plate 21 are respectively electrically connected with the first N + injection layer 13, the second N + injection layer 14, the third N + injection layer 15 and the fourth N + injection layer 16 through metals 24, 25, 26 and 27; the spacing between the adjacent polysilicon field plates is equal, and the spacing between the adjacent N + injection layers is equal.
The doping concentration of the N + injection layer is 1.0 multiplied by 10 19 /cm 3 ～5.0×10 19 /cm 3 (ii) a The ratio of the width W1 of the first N-type drift region 2a to the width W2 of the second N-type drift region 2b is 10: 1; the width of the P-type isolation layer 3 is 2 micrometers, and the length of the polysilicon field plate is 1 micrometer.
The working principle of the invention is as follows:
in the voltage bias tube, a drain end N-type buffer layer and a P + drain region form a PN junction, and a source end P-type base region and an N-type drift region form a PN junction. I.e. the voltage biased tube has two backward diodes. When the device works, a positive voltage is applied to the polysilicon gate of the LDMOS and the source electrode of the voltage bias tube, and the P-type base region in the LDMOS forms an N-type channel. Then, a positive voltage is applied to the drain of the LDMOS and the voltage bias tube, and at the moment, no matter whether the drain voltage of the voltage bias tube is high or the source voltage is high, two PN junctions are positively biased one by one and reversely biased, and the drift region voltage is always approximately equal to the voltage of the higher voltage of the source or the drain minus the forward conduction voltage of the PN junction.
The high potential of the drift region is transmitted to the first to fourth polysilicon field plates of the LDMOS by forming ohmic contact with the metal through the N + injection layer. The high voltage on the polysilicon field plate can weaken the influence of negative surface trap charges formed by electrons trapped by surface traps of the oxide layer, and meanwhile, the positive voltage of the polysilicon field plate has an attraction effect on the electrons, so that the electron concentration on the surface of the N-type drift region of the LDMOS is increased. Because the current path of the N-type LDMOS is mainly concentrated on the surface of the drift region, the forward on-resistance of the LDMOS can be effectively reduced by improving the electron concentration on the surface of the drift region.
The surface traps of the oxide layer have the function of capturing electrons. After the electrons are trapped by the surface traps, the trapped electrons are often thermally excited and released back into the conduction band before they recombine with holes. Thus, the action of the trap on the electrons is a dynamic process. The electron mobility decreases due to the action of the traps on the trapping and releasing of electrons. The positive voltage on the polysilicon field plate attracts electrons to be accumulated on the surface of the drift region, the electron concentration on the surface of the drift region is increased, the probability that each electron is captured by the surface trap of the oxide layer is reduced, and the electron mobility is increased. The dual effects of increased electron concentration and increased electron mobility in the current path lead to a reduction in the characteristic on-resistance of the device and an increase in the current capability.
In conclusion, the method and the structure of the invention solve the problems of electron mobility reduction and device current capability reduction caused by traps at the interface of the traditional device, improve the forward conduction characteristic of the silicon carbide LDMOS, increase the current capability of the device and have great significance for improving the performance of the device.
Claims (7)
1. A device for improving the surface mobility of a silicon carbide lateral double-diffused field effect transistor (LDMOS), which introduces a voltage bias tube, when a silicon carbide LDMOS is in forward conduction, high voltage of a drift region of the voltage bias tube can be transmitted to a plurality of polysilicon field plates above the surface of the drift region of the silicon carbide LDMOS through metal, the high voltage on the polysilicon field plates has the function of attracting electrons, so that the electrons on the surface of the drift region of the LDMOS are gathered, the concentration of the electrons is improved, the probability that a single electron is captured by a trap on the surface of an oxide layer above the drift region is reduced, and the mobility of the electrons is improved, the device comprises: the transistor comprises a P-type substrate (1), wherein an N-type drift region (2) is arranged on the P-type substrate (1), a P-type isolation layer (3) is arranged in the N-type drift region (2) and is divided into a first N-type drift region (2a) and a second N-type drift region (2b) by the P-type isolation layer (3), a first P-type base region (4) and a first N-type buffer layer (7) are respectively arranged on the first N-type drift region (2a), a P + source region (5) and an N + source region (6) which are connected are arranged in the first P-type base region (4), an N + drain region (8) is arranged in the first N-type buffer layer (7), a gate oxide layer (22) is arranged above the first N-type drift region (2a), one end of the gate oxide layer (22) extends into the upper part of the first P-type base region (4) and is stopped at the boundary of the N + source region (6), and a polysilicon gate oxide layer (17) is arranged on the gate oxide layer (22), the gate oxide layer (22) is provided with a polysilicon field plate separated from the polysilicon gate (17), and the polysilicon field plate is positioned between the polysilicon gate (17) and the first N-type buffer layer (7); a second P-type base region (9) and a second N-type buffer layer (10) are respectively arranged on the second N-type drift region (2b), a P source (11) is arranged in the second P-type base region (9), a P drain (12) is arranged in the second N-type buffer layer (10), an N + injection layer is arranged in the second N-type drift region (2b) and is positioned between the second P-type base region (9) and the second N-type buffer layer (10); the P source (11) is electrically connected with the polysilicon gate (17), the N + injection layer is electrically connected with the polysilicon field plate, and the P drain (12) is electrically connected with the N + drain region (8).
2. Device according to claim 1, characterized in that 4 mutually separated polysilicon field plates are provided on the gate oxide layer (22) and respectively a first polysilicon field plate (18), a second polysilicon field plate (19), a third polysilicon field plate (20) and a fourth polysilicon field plate (21); 4N + injection layers are arranged in the second N-type drift region (2b), and are respectively a first N + injection layer (13), a second N + injection layer (14), a third N + injection layer (15) and a fourth N + injection layer (16); the first polysilicon field plate (18), the second polysilicon field plate (19), the third polysilicon field plate (20) and the fourth polysilicon field plate (21) are electrically connected with the first N + injection layer (13), the second N + injection layer (14), the third N + injection layer (15) and the fourth N + injection layer (16) respectively.
3. The device of claim 2, wherein the spacing between adjacent polysilicon field plates is equal and the spacing between adjacent N + implant layers is equal.
4. The device of claim 2, wherein the N + implanted layer has a doping concentration of 1.0 x 10 19 /cm 3 ～5.0×10 19 /cm 3 。
5. The device according to claim 2, wherein the ratio of the width W1 of the first N-type drift region (2a) to the width W2 of the second N-type drift region (2b) is 10: 1.
6. Device according to claim 2, characterized in that the width of the P-type isolation layer (3) is 2 μm.
7. The device of claim 2, wherein the polysilicon field plates are each 1 μm in length.
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| KR102286013B1 (en) * | 2015-10-07 | 2021-08-05 | 에스케이하이닉스 시스템아이씨 주식회사 | Lateral high voltage integrated device having tranch insulating field plate and metal field plate |
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| JP2005260100A (en) * | 2004-03-12 | 2005-09-22 | Fuji Electric Holdings Co Ltd | Trench lateral type semiconductor device, and manufacturing method thereof |
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