CN112951137B - Method and device for identifying signal transmission integrity - Google Patents
Method and device for identifying signal transmission integrity Download PDFInfo
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- CN112951137B CN112951137B CN202110124925.7A CN202110124925A CN112951137B CN 112951137 B CN112951137 B CN 112951137B CN 202110124925 A CN202110124925 A CN 202110124925A CN 112951137 B CN112951137 B CN 112951137B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2370/00—Aspects of data communication
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Abstract
The invention provides a method and a device for identifying signal transmission integrity. The method for identifying the signal transmission integrity is applied to any sending unit in the time sequence controller, the sending unit corresponds to the receiving unit of the source driving circuit one by one, and the method comprises the following steps: calculating the signal transmitted by the transmitting unit by adopting a first register in the transmitting unit, and obtaining a total value of the transmitted signal, and marking the total value as a first sum check code; calculating the signals received by the receiving unit by adopting a second register in the receiving unit, obtaining the summarized value of the received signals, and recording the summarized value as a second sum check code; a difference between the first sum check code and the second sum check code is calculated. The method and the device for identifying the signal transmission integrity are convenient for simulating whether the wiring layout of the display panel meets the requirement of signal complete transmission in advance and prevent the display image from being distorted.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a method and apparatus for identifying signal transmission integrity.
Background
The display device generally includes a display panel and a driving circuit for driving the display panel, the driving circuit including a timing controller, a gate driving circuit, and a source driving circuit. In the related art, the timing controller includes a plurality of transmitting units, the source driving circuit includes a plurality of receiving units, the plurality of transmitting units are in one-to-one correspondence with the plurality of receiving units, and the plurality of receiving units are connected with a plurality of columns of pixel units on the display panel one by one. When the display panel is required to be controlled to display images, each sending unit in the time sequence controller can send signals to the corresponding receiving unit, so that each receiving unit inputs display signals to a row of pixel units connected on the display panel according to the received signals, and each row of pixel units on the display panel sends out light with corresponding colors according to the input display signals, so that the display panel displays images.
With the development of large-size, high-resolution and high-refresh rate products, more and more liquid crystal displays adopt a P2P (peer-to-peer) transmission protocol, TCON (Timer Control Register, timing controller) is a transmitting end of the P2P transmission protocol, and a source driving circuit is a receiving end. Since the larger the size of the liquid crystal display, the larger the difference between the distance of P2P transmission is, some bit signals are easily lost during the long-distance transmission, resulting in picture distortion. Since the P2P transmission protocol includes the control command of the source driving circuit, if the control command is distorted, the display screen of the display panel may be "black" or abnormal. Therefore, it is necessary to improve this defect.
Disclosure of Invention
The invention provides a method and a device for identifying signal transmission integrity, which are used for solving the technical problem that a display panel in the prior art is incomplete in signal transmission due to circuit wiring layout and causes display picture distortion.
In order to solve the technical problems, the technical scheme provided by the invention is as follows:
the embodiment of the invention provides a method for identifying signal transmission integrity, which is applied to any one of a plurality of sending units of a time sequence controller, wherein the plurality of sending units are in one-to-one correspondence with a plurality of receiving units of a source electrode driving circuit, and the method comprises the following steps of:
calculating the signals transmitted by the transmitting unit by adopting a first register in the transmitting unit, and obtaining the total value of the transmitted signals, and marking the total value as a first total check code;
calculating the signals received by the receiving unit by adopting a second register in the receiving unit, obtaining a summarized value of the received signals, and recording the summarized value as a second sum check code;
a difference between the first sum check code and the second sum check code is calculated.
According to the method for identifying signal transmission integrity provided by the embodiment of the invention, the first sum check code in the first register stores the summarized value of all byte signals transmitted in a frame signal calculated by the transmitting unit.
According to the method for identifying signal transmission integrity provided by the embodiment of the invention, the second sum check code in the second register stores the summarized value of all byte signals received in a frame signal calculated by the receiving unit.
According to the method for identifying signal transmission integrity provided by the embodiment of the invention, the calculation formulas adopted by the first register and the second register for all byte signals in the same frame signal are the same.
According to the method for identifying signal transmission integrity provided by the embodiment of the invention, when the difference between the first sum check code and the second sum check code is zero, all byte signals sent by the sending unit are completely received by the receiving unit.
According to the method for identifying signal transmission integrity provided by the embodiment of the invention, when the difference between the first sum check code and the second sum check code is zero, the signal integrity state of the receiving unit in the source driving circuit is low level.
According to the method for identifying signal transmission integrity provided by the embodiment of the invention, when the difference between the first sum check code and the second sum check code is not zero, all byte signals sent by the sending unit are not completely received by the receiving unit.
According to the method for identifying signal transmission integrity provided by the embodiment of the invention, when the difference between the first sum check code and the second sum check code is not zero, the signal integrity state of the receiving unit in the source driving circuit is high level.
According to the method for identifying signal transmission integrity provided by the embodiment of the invention, the signal sent by the sending unit comprises a plurality of frame signals, each frame signal in the plurality of frame signals comprises a plurality of row signals, and each row signal in the plurality of row signals comprises: a timing detection signal, a line start identification signal, a line polarity control signal, a pixel data packet signal, a drive control register set signal, a vertical blanking polarity control signal, and a line cut-off identification signal; the line start identification signal is used for indicating the start position of each line signal, the line polarity control signal is used for controlling the polarity of each line signal, the vertical blanking polarity control signal is used for controlling the polarity of the vertical blanking of each line signal, and the line stop identification signal is used for indicating the stop position of each line signal.
The embodiment of the invention also provides a device for identifying the integrity of signal transmission, which comprises: the display device comprises a time sequence controller, a source electrode driving circuit, a printed circuit board, a flip chip film and a display panel; the time schedule controller comprises a plurality of sending units, the source electrode driving circuit comprises a plurality of receiving units, and the sending units are in one-to-one correspondence with the receiving units; the signal is transmitted between the sending unit and the receiving unit by adopting a point-to-point transmission protocol; the apparatus for identifying signal transmission integrity uses the method for identifying signal transmission integrity as described in any one of the above embodiments.
The beneficial effects are that: the embodiment of the invention provides a method and a device for identifying signal transmission integrity, which are characterized in that all signals sent by a sending unit in a time sequence controller are calculated, and corresponding calculation results are stored in a first register; calculating all signals received by a receiving unit in the source driving circuit, and storing corresponding calculation results in a second register; the difference between the first register and the second register is compared to judge the integrity of the signal transmission of the display panel. Whether the wiring layout of the point-to-point transmission protocol on the printed circuit board meets the requirement of complete signal transmission or not is conveniently simulated in advance, and the resolution of the problem of abnormal pictures is also facilitated; the signal received by the receiving unit is prevented from being distorted, and the image displayed by the display panel is prevented from being distorted.
Drawings
In order to more clearly illustrate the embodiments or technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below.
Fig. 1 is a flowchart of a method for identifying signal transmission integrity according to an embodiment of the present invention.
Fig. 2 is a schematic structural diagram of an apparatus for identifying signal transmission integrity according to an embodiment of the present invention.
Fig. 3 is a schematic signal diagram of a certain frame according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments refers to the accompanying drawings, which illustrate specific embodiments in which the invention may be practiced. The directional terms mentioned in the present invention, such as [ upper ], [ lower ], [ front ], [ rear ], [ left ], [ right ], [ inner ], [ outer ], [ side ], etc., are only referring to the directions of the attached drawings. Accordingly, directional terminology is used to describe and understand the invention and is not limiting of the invention. In the drawings, like elements are designated by like reference numerals.
As shown in fig. 1, a flowchart of a method for identifying signal transmission integrity is provided in an embodiment of the present invention. The method for identifying the signal transmission integrity is applied to any one of a plurality of sending units of the time schedule controller, and the plurality of sending units are in one-to-one correspondence with a plurality of receiving units of the source driving circuit. That is, a plurality of the transmitting units and a plurality of the receiving units may transmit signals using a P2P (peer-to-peer) transmission protocol. Specifically, the method for identifying signal transmission integrity includes the steps of:
s101, calculating the signals transmitted by the transmitting unit by adopting a first register in the transmitting unit, and obtaining the total value of the transmitted signals, and marking the total value as a first total check code;
s102, calculating the signals received by the receiving unit by adopting a second register in the receiving unit, obtaining a summarized value of the received signals, and recording the summarized value as a second sum check code;
s103, calculating and obtaining a difference value between the first sum check code and the second sum check code.
Wherein the first sum check code in the first register stores a summary value of all byte signals transmitted in one frame of signals calculated by the transmitting unit; the second sum check code in the second register stores a summary value of all byte signals received within one frame signal calculated by the receiving unit.
In this embodiment, the timing controller may be provided with a plurality of ports, and at least one channel may be provided in each port, for example, one channel, two channels, or three channels may be provided in each port. That is, a plurality of channels may be provided on the timing controller, and a plurality of transmitting units in the timing controller are connected to the plurality of channels in one-to-one correspondence. The source driving circuit comprises a plurality of source driving chips, each source driving chip is provided with a plurality of ports, each port can comprise at least one channel, namely, the source driving circuit can be provided with a plurality of channels, and a plurality of receiving units in the source driving circuit are connected with the channels in a one-to-one correspondence manner.
Further, the plurality of channels arranged on the time schedule controller are also connected with the plurality of channels arranged on the source electrode driving circuit in a one-to-one correspondence manner through signal lines, so that the plurality of sending units in the time schedule controller and the plurality of receiving units in the source electrode driving circuit are respectively connected with the ports on the time schedule controller, the signal lines and the ports on the source electrode driving circuit in a one-to-one correspondence manner.
Specifically, in this embodiment, the calculation formulas adopted by the first register and the second register for all byte signals in the same frame signal are the same. When the difference between the first sum check code and the second sum check code is zero, all byte signals sent by the sending unit are completely received by the receiving unit; when the difference between the first sum check code and the second sum check code is zero, the signal integrity state of the receiving unit in the source driving circuit is low level, that is, the signals sent by the sending unit in the time schedule controller are completely received by the receiving unit in the source driving circuit.
When the difference between the first sum check code and the second sum check code is not zero, all byte signals sent by the sending unit are not completely received by the receiving unit, namely the transmission signal is missing; when the difference between the first sum check code and the second sum check code is not zero, the signal integrity state of the receiving unit in the source driving circuit is high level, that is, the signal sent by the sending unit in the timing controller is not completely received by the receiving unit in the source driving circuit, and the transmitted signal is missing.
Specifically, in this embodiment, the signal sent by the sending unit includes a plurality of frame signals, each frame signal in the plurality of frame signals includes a plurality of row signals, and each of the row signals in the plurality of row signals includes: a timing detection signal, a line start identification signal, a line polarity control signal, a pixel data packet signal, a drive control register set signal, a vertical blanking polarity control signal, and a line cut-off identification signal; the line start identification signal is used for indicating the start position of each line signal, the line polarity control signal is used for controlling the polarity of each line signal, the vertical blanking polarity control signal is used for controlling the polarity of the vertical blanking of each line signal, and the line stop identification signal is used for indicating the stop position of each line signal.
The row polarity control signals comprise a positive row polarity control signal and a negative row polarity control signal, wherein only one row polarity control signal exists in each row signal, and the positive row polarity control signal or the negative row polarity control signal exists in each row signal. The vertical blanking polarity control signals include a positive vertical blanking polarity control signal and a negative vertical blanking polarity control signal, there being only one vertical blanking polarity control signal in each of the row signals, the positive vertical blanking polarity control signal or the negative vertical blanking polarity control signal.
The frame signal comprises the following components:
a row signal composed of N of the timing detection signals, one of the row start identification signals, one of the positive row polarity control signals, one of the pixel data packet signals, and one of the row stop identification signals;
a row signal composed of N of the timing detection signals, one of the row start identification signals, one of the negative row polarity control signals, one of the pixel data packet signals, and one of the row stop identification signals;
a row signal composed of N of the timing detection signals, one of the row start identification signals, one of the drive control register setting signals, one of the control register setting signals, and one of the row stop identification signals;
a row signal composed of N timing detection signals, one row start identification signal, one positive vertical blanking polarity control signal, and N timing detection signals; and
a row signal composed of N time sequence detection signals, one row start identification signal, one negative vertical blanking polarity control signal and N time sequence detection signals.
In summary, in the method for identifying signal transmission integrity provided in the present embodiment, all signals sent by the sending unit in the timing controller are calculated, and the corresponding calculation result is stored in the first register; calculating all signals received by a receiving unit in the source driving circuit, and storing corresponding calculation results in a second register; the difference between the first register and the second register is compared to judge the integrity of the signal transmission of the display panel. Whether the wiring layout of the point-to-point transmission protocol on the printed circuit board meets the requirement of complete signal transmission or not is conveniently simulated in advance, and the resolution of the problem of abnormal pictures is also facilitated; the signal received by the receiving unit is prevented from being distorted, and the image displayed by the display panel is prevented from being distorted.
As shown in fig. 2, an apparatus for identifying signal transmission integrity according to an embodiment of the present invention is shown in a schematic structure. The means for identifying signal transmission integrity comprises: a timing controller 10, a source driving circuit 20, a printed circuit board 30, a flip chip film 40 and a display panel 50; the timing controller 10 includes a plurality of transmitting units, the source driving circuit 20 includes a plurality of receiving units 201, and the plurality of transmitting units are in one-to-one correspondence with the plurality of receiving units 201; the transmitting unit and the receiving unit 201 transmit signals using a point-to-point transmission protocol, i.e. the means for identifying the integrity of the signal transmission uses a point-to-point transmission protocol.
Specifically, the timing controller 10 may be provided with a plurality of ports, and at least one channel may be provided in each port, for example, one channel, two channels, or three channels may be provided in each port. That is, a plurality of channels may be provided on the timing controller 10, and a plurality of transmitting units in the timing controller 10 are connected to the plurality of channels in one-to-one correspondence. The source driving circuit 20 includes a plurality of source driving chips, each source driving chip is provided with a plurality of ports, each port includes at least one channel, that is, a plurality of channels may be provided on the source driving circuit 20, and the plurality of receiving units 201 are connected to the plurality of channels in a one-to-one correspondence manner. Further, the channels provided on the timing controller 10 are also connected with the channels provided on the source driving circuit 20 in a one-to-one correspondence manner through signal lines, so that the transmitting units in the timing controller 10 and the receiving units 201 in the source driving circuit 20 are respectively connected with the ports on the timing controller 10, the signal lines and the ports on the source driving circuit 20 in a one-to-one correspondence manner.
The display panel 50 is provided with a plurality of pixel units arranged in an array, each pixel unit at least comprises a thin film transistor and a pixel electrode which are connected, the pixel units can form a plurality of columns of pixel units, and the pixel units in the plurality of columns can be correspondingly connected with the receiving units 201 in the source driving circuit 20 one by one. Optionally, the apparatus may further include a gate drive circuit 60.
The apparatus for identifying signal transmission integrity provided in this embodiment may be: a liquid crystal display device or an OLED (Organic Light-Emitting Diode) display device, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital camera, a navigator, or any product or component having a display function.
Specifically, the apparatus for identifying signal transmission integrity provided in this embodiment uses the method for identifying signal transmission integrity described in the above embodiment, and the method is described with reference to fig. 1 and related description, and is not repeated here.
Fig. 3 is a schematic signal diagram of a certain frame according to an embodiment of the present invention. The frame signal provided in this embodiment includes: a plurality of vertical display (V-display) line signals and three vertical blanking (V-blank) line signals;
wherein the vertical display (V-display) line signal includes:
positive row polarity row signal: n CTs (timing detection signals), one CS (Command Start), one CM1 (positive line polarity control signal), one pixeldata (pixel packet signal), one CE (line cut-off identification signal); wherein, the time sequence detection signal (CT) sends a plurality of periods and mainly aims at detecting the communication frequency between the time sequence controller and the source electrode driving circuit; the line start identification signal (CS) is sent for only one period; the forward polarity control signal (CM 1) is sent for only one cycle; the line cut-off identification signal (CE) is sent only for one period;
negative row polarity row signal: n CTs, one CS, one CM2 (negative line polarity control signal), one pixeldata, and one CE; wherein, the time sequence detection signal (CT) sends a plurality of periods and mainly aims at detecting the communication frequency between the time sequence controller and the source electrode driving circuit; the line start identification signal (CS) is sent for only one period; the negative row polarity control signal (CM 2) is sent for only one cycle; the line cut-off identification signal (CE) is transmitted for only one period.
And the vertical display (V-display) line signal is cyclically generated in the order of the positive line polarity line signal, the negative line polarity line signal, and the positive line polarity line signal.
Wherein the vertical blanking (V-blank) line signal includes:
control register row signals: n CTs, one CS, one CM3 (drive control register set signal), one Control register setting (control register set signal), and one CE; wherein, the time sequence detection signal (CT) sends a plurality of periods and mainly aims at detecting the communication frequency between the time sequence controller and the source electrode driving circuit; the line start identification signal (CS) is sent for only one period; the drive control register setting signal (CM 3) is sent for only one cycle; the line cut-off identification signal (CE) is sent only for one period;
positive vertical blanking polarity line signal: n CTs, one CS, one CM4 (positive vertical blanking polarity control signal), N CTs; wherein, the time sequence detection signal (CT) sends a plurality of periods and mainly aims at detecting the communication frequency between the time sequence controller and the source electrode driving circuit; the line start identification signal (CS) is sent for only one period; the positive vertical blanking polarity control signal (CM 4) is sent for only one period;
negative vertical blanking polarity line signal: n CTs, one CS, one CM5 (negative vertical blanking polarity control signal), N CTs; wherein, the time sequence detection signal (CT) sends a plurality of periods and mainly aims at detecting the communication frequency between the time sequence controller and the source electrode driving circuit; the line start identification signal (CS) is sent for only one period; the negative vertical blanking polarity control signal (CM 5) is transmitted for only one period.
Wherein the vertical display (V-display) line signal includes: a line blanking (H-blank) signal and a line display (H-display) signal. The line blanking (H-blank) signal comprises the timing detection signal (CT), the line start identification signal (CS) and the line polarity control signals (CM 1, CM 2). The line display (H-display) signal includes the pixel data packet signal (pixel data) and the line cut-off identification signal (CE).
The bit unit of the timing detection signal (CT) may be 111100001, the bit unit of the line start identification signal (CS) may be 000011110, the bit unit of the positive line polarity control signal (CM 1) may be 011001111, the bit unit of the negative line polarity control signal (CM 2) may be 100110000, the bit unit of the driving control register setting signal (CM 3) may be 100000011, the bit unit of the positive vertical blanking polarity control signal (CM 4) may be 011101111, the bit unit of the negative vertical blanking polarity control signal (CM 5) may be 100010000, and the bit unit of the line cut-off identification signal (CE) may be 011111100.
The foregoing has described in detail a method and apparatus for identifying signal transmission integrity provided by embodiments of the present invention, and specific examples have been applied herein to illustrate the principles and embodiments of the present invention, the above description of the embodiments is only for aiding in understanding the technical solution and core idea of the present invention; those of ordinary skill in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.
Claims (8)
1. A method of identifying signal transfer integrity, wherein the method is applied to any one of a plurality of transmitting units of a timing controller, the plurality of transmitting units being in one-to-one correspondence with a plurality of receiving units of a source driving circuit, the method comprising the steps of:
calculating the signal sent by the sending unit by adopting a first register in the sending unit, and obtaining a total value of the sent signal, wherein the signal sent by the sending unit comprises a plurality of frame signals, each frame signal in the plurality of frame signals comprises a plurality of row signals, and each row signal in the plurality of row signals comprises: the first sum check code in the first register stores the sum value of all byte signals sent in a frame signal calculated by the sending unit;
calculating the signals received by the receiving unit by adopting a second register in the receiving unit, obtaining a summary value of the received signals, and recording the summary value as a second sum check code, wherein the second sum check code in the second register stores the summary value of all byte signals received in a frame of signals calculated by the receiving unit;
a difference between the first sum check code and the second sum check code is calculated.
2. The method of claim 1, wherein the first register and the second register use the same calculation formula for all byte signals within the same frame signal.
3. The method of claim 1, wherein when the difference between the first sum check code and the second sum check code is zero, all byte signals transmitted by the transmitting unit are received in their entirety by the receiving unit.
4. The method of claim 3, wherein the signal integrity status of the receiving unit in the source driver circuit is low when the difference between the first and second checksum is zero.
5. The method of claim 1, wherein when the difference between the first sum check code and the second sum check code is not zero, all byte signals transmitted by the transmitting unit are not completely received by the receiving unit.
6. The method of claim 5, wherein the signal integrity status of the receiving unit in the source driver circuit is high when the difference between the first and second checksum codes is non-zero.
7. The method of claim 1, wherein the line start identification signal is used to indicate a start position of each of the line signals, the line polarity control signal is used to control a polarity of each of the line signals, the vertical blanking polarity control signal is used to control a polarity of a vertical blanking of each of the line signals, and the line stop identification signal is used to indicate a stop position of each of the line signals.
8. An apparatus for identifying signal transmission integrity, comprising: the display device comprises a time sequence controller, a source electrode driving circuit, a printed circuit board, a flip chip film and a display panel;
the time schedule controller comprises a plurality of sending units, the source electrode driving circuit comprises a plurality of receiving units, and the sending units are in one-to-one correspondence with the receiving units; the signal is transmitted between the sending unit and the receiving unit by adopting a point-to-point transmission protocol;
the means for identifying signal transmission integrity uses a method of identifying signal transmission integrity as claimed in any one of claims 1 to 7.
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| JP2011237490A (en) * | 2010-05-06 | 2011-11-24 | Canon Inc | Data processor, display control method in data processor, and its program |
| CN107799045B (en) * | 2016-09-05 | 2021-07-20 | 奇景光电股份有限公司 | Display panel driving device, display and operation method thereof |
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| CN108696288B (en) * | 2017-06-09 | 2022-02-01 | 京东方科技集团股份有限公司 | Signal transmission method, transmitting unit, receiving unit and display device |
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