CN112949586B - Electroencephalogram signal processing chip and electroencephalogram signal processing system - Google Patents
Electroencephalogram signal processing chip and electroencephalogram signal processing system Download PDFInfo
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Abstract
The invention provides an electroencephalogram signal processing chip and an electroencephalogram signal processing system, wherein the electroencephalogram signal processing chip comprises: the electroencephalogram signal acquisition module is used for acquiring electroencephalogram signals; the IIR filter module is used for filtering the target frequency band of the electroencephalogram signal; the characteristic extraction module is connected with the IIR filter and is used for extracting characteristics of the electroencephalogram signals of the target frequency band. By implementing the invention, the IIR filter is adopted to replace the FIR filter, so that the number of filters is reduced and the chip area is reduced on the basis of ensuring good filtering effect.
Description
Technical Field
The invention relates to the field of electroencephalogram signal processing, in particular to an electroencephalogram signal processing chip and an electroencephalogram signal processing system.
Background
The brain electrical signal contains a large amount of physiological and disease information, and in clinical medicine, the brain electrical signal processing not only can provide diagnosis basis for certain brain diseases, but also can provide effective treatment means for certain brain diseases. In engineering application, people also try to realize brain-computer interface (BCI) by using brain electrical signals, and realize effective extraction and classification of brain electrical signals by using brain electrical differences of people on different sensory, motor or cognitive activities. In the related art, a traditional FIR filter is adopted when an electroencephalogram signal processing chip processes an electroencephalogram signal, so that a large number of FIR filters are needed for obtaining a good filtering effect, and the area of the chip is greatly increased.
Disclosure of Invention
In view of the above, the embodiment of the invention provides an electroencephalogram signal processing chip and an electroencephalogram signal processing system, so as to solve the defect that in the prior art, in order to obtain a good filtering effect, a large number of FIR filters are needed, and the chip area is greatly increased.
According to a first aspect, an embodiment of the present invention provides an electroencephalogram signal processing chip, including: the electroencephalogram signal acquisition module is used for acquiring electroencephalogram signals; the IIR filter module is used for filtering the target frequency band of the electroencephalogram signal; the characteristic extraction module is connected with the IIR filter module and is used for extracting characteristics of the electroencephalogram signals of the target frequency band.
Optionally, the electroencephalogram signal processing chip further includes: and one end of the signal synchronization module is connected with the electroencephalogram signal acquisition module, and the other end of the signal synchronization module is connected with the IIR filter module and is used for synchronously processing the electroencephalogram signals.
Optionally, the IIR filter module is formed by cascading eight second-order IIR filters, the second-order IIR filters include multipliers and adders, the second-order IIR filters use a first clock frequency to call the multipliers to achieve multiplication operation or use the first clock frequency to call the adders to achieve addition operation, and the first clock frequency is higher than the working frequency of the second-order IIR filters.
Optionally, the signal synchronization module includes: at least two stages of registers for reducing metastability probability; and the counter is connected with the output ends of the at least two stages of registers and is used for expanding the period length of the output level of the at least two stages of registers to the target period length so as to realize signal synchronization.
Optionally, the feature extraction module includes: the frequency band energy calculation module is used for solving the following formulas according to the Booth code and the compressor to determine the energy of the electroencephalogram signals of the target frequency band:
where E (i) is the electroencephalogram signal energy of the frequency band i, N is the number of sampling points in one period, and X (m) is the energy level at the N points.
Optionally, the electroencephalogram signal acquisition module is externally connected with a first gating clock module; the IIR filter module is externally connected with a second gating clock module; and the signal synchronization module is externally connected with a third gating clock module.
Optionally, the target frequency band is 0-48HZ.
Optionally, the multiplier is a booth multiplier.
According to a second aspect, an embodiment of the present invention provides an electroencephalogram signal processing system, including: an electroencephalogram signal processing chip as in the first aspect or any one of the embodiments of the first aspect; the Bluetooth module is connected with the electroencephalogram signal processing chip according to the first aspect or any implementation manner of the first aspect, and is used for transmitting the extracted electroencephalogram signal characteristics.
Optionally, the electroencephalogram signal processing chip further includes: the analog-to-digital conversion module is connected with the electroencephalogram signal processing chip according to the first aspect or any implementation manner of the first aspect, and is used for converting an analog electroencephalogram signal into a digital electroencephalogram signal.
The technical scheme of the invention has the following advantages:
1. according to the electroencephalogram signal processing chip provided by the embodiment, the IIR filter is adopted to replace the FIR filter, so that the number of filters is reduced on the basis of ensuring a good filtering effect, and the chip area is reduced.
2. The electroencephalogram signal processing system provided by the embodiment can realize data interaction through the external Bluetooth module, and is used for controlling the electroencephalogram signal processing chip and receiving information sent by the electroencephalogram signal processing chip so as to form wearable equipment.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIGS. 1 to 17 are diagrams illustrating specific examples of an electroencephalogram signal processing chip according to an embodiment of the present invention;
fig. 18 is a diagram illustrating a specific example of an electroencephalogram signal processing system according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made apparent and fully in view of the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the description of the present invention, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, or can be communicated inside the two components, or can be connected wirelessly or in a wired way. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
In addition, the technical features of the different embodiments of the present invention described below may be combined with each other as long as they do not collide with each other.
The present embodiment provides an electroencephalogram signal processing chip, as shown in fig. 1, including:
an electroencephalogram signal acquisition module 101 for acquiring an electroencephalogram signal;
the IIR filter module 102 is configured to filter a target frequency band of the electroencephalogram signal;
the feature extraction module 103 is connected to the IIR filter 102, and is configured to perform feature extraction on the electroencephalogram signal in the target frequency band.
Illustratively, the electroencephalogram signal acquisition module 101 can be an ADS1299 chip. The ADS1299 chip adopts a standard SPI communication protocol, and a timing diagram of the communication protocol is shown in fig. 2. Wherein cpol=0 and cpha=1, i.e. data is collected at the rising edge and the falling edge of SCLK, and at the same time ADS1299 has various control instructions as shown in table 1 below, the instructions are stored in RAM, and the address can be sent to RAM through bluetooth to invoke corresponding instructions to realize corresponding functions.
TABLE 1
| ADDR[3:0] | COMMAND[7:0]Function of |
| 0000(0h) | 0000 0010 (02 h), wake-up after starting up |
| 0001(1h) | 0000 0100 (04 h), enter standby |
| 0010(2h) | 0000 0110 (06 h), reset device |
| 0011(3h) | 0000 1000 (08 h), start-up and restart transition |
| 0100(4h) | 0000 1010 (0 Ah), stop converting |
| 0101(5h) | 0001 0000 (10 h), read-through mode [ power-on default ]] |
| 0110(6h) | 0001 0001 (11 h), stopRead-through |
| 0111(7h) | 0001 0010 (12 h), read data by command |
| 1000(8h) | 0010 0001 (21 h), reading registers from 01h |
| 1001(9h) | 0010 0101 (25 h), reading registers from 05h |
| 1010(Ah) | 0100 0001 (41 h), write registers starting from 01h |
| 1011(Bh) | 0100 0101 (45 h), writing the register from 05h |
When the electroencephalogram signal acquisition module 101 is an ADS1299 chip, the data sampling rate is 250SPS, namely, 250 data can be converted in 1 second, namely, the sampling frequency is 250Hz. Then IIR filter module 102 may also employ a sampling frequency of 250HZ in order to keep its sampling frequency synchronized.
The IIR filter module 102 is configured to filter a target frequency band of the electroencephalogram signal, where the target frequency band may select an arbitrary frequency band range, and the target frequency band range is not limited in this embodiment, and may be determined by a person skilled in the art according to needs. The rhythmic activity of an electroencephalogram signal is typically composed of four frequency bands: delta band (0.1-3 Hz), theta band (4-7 Hz), alpha band (8-12 Hz) and beta band (13-25 Hz), frequencies above 25Hz are referred to as gamma band. It can be seen that the brain state can be accurately described by the brain signals in the 0-48HZ frequency band, and in order to further reduce the data processing amount of the brain signal processing chip, the brain signals in the 0-48HZ frequency band can be selected.
In this embodiment, the target frequency band is 0-48HZ, and since delta frequency band (0.1-3 HZ), theta frequency band (4-7 HZ) and alpha frequency band (8-12 HZ) are all 4HZ in four frequency bands of the brain electrical signal rhythmic activity, 12 IIR filters with the frequency band width of 4HZ may be integrated in the IIR filter module 102 in order to simplify the circuit and implement the filtering of 0-48HZ. The types of IIR filters may be classified into elliptic filters, chebyshev filters, butterworth filters, etc., and since elliptic filters have minimal passband and stopband fluctuations under the same order, the preferred IIR filter type may be elliptic filters, and the embodiment does not limit the IIR filter type in the IIR filter module, and those skilled in the art may determine the type as needed.
The IIR filter module 102 may be of any order, and through comparison of filter tests on different orders, it is found that the filtering effect is better when the selected order is 16, so, as shown in fig. 3, the IIR filter module 102 of this embodiment may be cascaded by eight second-order IIR filters into a 16-order IIR filter, where the output of the last second-order IIR filter is used as the input of the next second-order IIR filter. Each second order IIR filter has a differential equation that can be expressed as:
a 0 *y(n)＝b 0 *x(n)+b 1 *x(n-1)+b 2 *x(n-2)-a 1 *y(n-1)-a 2 *y(n-2)； (1)
where y (n) is the current output, y (n-1) and y (n-2) are the past filter outputs, x (n) is the current input, x (n-1) and x (n-2) are the past filter inputs, a 0 、a 1 、a 2 、b 0 、b 1 、b 2 Is a coefficient. The zero point is satisfied to make the numerator of the transfer function zero, and the pole is satisfied to make the denominator of the transfer function zero, namely, in the formula, the zero point is the first three terms of the differential equation, and the pole is the second two terms.
According to the above formula (1), the internal principle structural diagram of each second-order IIR filter is shown in FIG. 4, b 0 x(n)、b 1 x(n-1)、b 2 x (n-2) (zero) minus a 1 y(n-1)、a 2 y (n-2) (the sum of poles) gives a 0 y (n), wherein a 0 、a 1 、a 2 、b 0 、b 1 、b 2 These coefficients can be generated by the FDATOOL tool in MATLAB, which generates coefficients that are floating point numbers, thus requiring quantization of these coefficients. Due to coefficient a 0 Finally, the division operation is performed in the FPGA as a divisor, so in order to avoid the occurrence of the division operation, the division operation is implemented by using a data shift method, so the quantization method is to amplify the floating point number generated by the original tool by 2 # -14=16384 times, and then round it to be rounded. As shown in fig. 5, for the coefficient before data processing, as shown in fig. 6, since the amplification factor is n times of power of 2, the final division by a0 corresponds to division by 16384, and the shift is realized by shifting the data of the register to the right by 14 bits in the FPGA, and the function of normalizing the coefficient is also realized.
In the FPGA, in order to ensure that the data does not overflow, the number of bits of the result of each multiplication is the sum of the number of bits of zero-order point data (24 bits, the conversion result of ADS1299 chip, 24 bits for each channel, so the pole zero in the system is 24 bits) and the number of parameter bits (16384 as the quantization multiple in quantization, 16 bits for preventing overflow of parameter data), so a0_y (n) is stored in a 40-bit register. In normal cases, the signal passing through the filter will not be amplified, so that the effective value of a0_y (n) will not exceed the input signal size (24 bits) at this time, and in order to facilitate the input of the next filter, the lower 24 bits of a0_y (n) need to be taken as the output result, and the output result, while being the input of the next filter, is also fed into the shift register prepared by the current filter as feedback of the current moment to the future moment. The feedback mode may be as shown in fig. 7, and the data of the previous clock can still be called in the current clock through beat processing, so as to achieve the feedback effect.
The feature extraction module 103 is used for extracting a biomarker from the electroencephalogram signal, wherein the biomarker shows a large difference between the period of onset and the period of onset, and the energy of a frequency band can be used as the biomarker to distinguish different states.
When the FIR filter filters, the equivalent filtering effect of the IIR filter is required, more FIR filters are needed, and the EEG signal processing chip provided by the embodiment adopts the IIR filter to replace the FIR filter, so that the number of filters is reduced and the chip area is reduced on the basis of ensuring good filtering effect.
As an alternative implementation manner of this embodiment, as shown in fig. 1, the electroencephalogram signal processing chip further includes:
and one end of the signal synchronization module 104 is connected with the electroencephalogram signal acquisition module 101, and the other end of the signal synchronization module is connected with the IIR filter module 102 and is used for synchronously processing the electroencephalogram signals.
Illustratively, when the sampling frequency of the IIR filter in the IIR filter block 102 is different from the sampling frequency of the electroencephalogram signal acquisition block 101, signal synchronization is required. In this embodiment, the electroencephalogram signal acquisition module 101 is used as an example, and the sampling frequency of the IIR filter in the IIR filter module 102 is 128 HZ.
The signal synchronization module 104 includes: at least two stages of registers for reducing metastability probability; and the counter is connected with the output ends of the at least two stages of registers and is used for expanding the period length of the output level of the at least two stages of registers to the target period length so as to realize signal synchronization.
As shown in fig. 8, the clock terminals of the register 1 and the register 2 adopt 256HZ, the input terminal of the register 1 is the 250HZ sampling data of the electroencephalogram signal acquisition module 101, and the metastable state probability of the register 1 is set to be p 1 The metastability probability of register 2 is p 2 Then the metastability probability p after passing through the two stages of registers 3 ＝p 1 ×p 2 Therefore, the probability of metastability can be reduced, the output result is D1, and the specific timing diagram is shown in fig. 9.
The counter is a one-bit counter, the 0-1 cycle counts, each cycle counts once, the input of the register 3 (D trigger) is controlled by taking the counter as a judging signal of the selector, when the counter output is 1, the input data of the register 3 (D trigger) can be kept for one cycle (the target cycle length is twice of the output level cycle), when the counter output is 0, the register 3 (D trigger) receives a new input signal, a specific timing diagram is shown in fig. 9, by expanding the level, the Q1 data which can be collected can be stabilized by taking the clock rising edge of the register 4 with 128Hz as the working clock can be ensured, no violations of the establishment time and the keeping time can be generated, so that the metastable state is avoided, the 250Hz data can be converted on the clock domain with 128Hz, and the follow-up 128Hz IIR filter module 102 can conveniently use the brain electrical signal which is collected by the brain electrical signal collection module 101 through 250Hz.
As an alternative implementation manner of this embodiment, the IIR filter module 102 is formed by cascading eight second-order IIR filters, where the second-order IIR filters include multipliers and adders, and the second-order IIR filters use a first clock frequency to call the multipliers to implement multiplication or use the first clock frequency to call the adders to implement addition, and the first clock frequency is higher than the operating frequency of the second-order IIR filter module.
For example, the first clock frequency may be 1024HZ when the operating frequency of IIR filter block 102 is 128 HZ. By adopting the 1024Hz first clock frequency to process the computing unit of the IIR filter, one period under 128Hz can be divided into 8 periods under 1024Hz, and according to the formula (1), the IIR filter needs to perform multiplication operation for five times at one time, namely, 5 multipliers are required to be simultaneously started for completing the filtering at the 128Hz working frequency, and the multiplication operation can be performed respectively in 5 periods through the 1024Hz working frequency, so that only one multiplier is required to be reused, the number of 4 multipliers is reduced, 80% of computing resources are saved, and the area of the IIR filter module is also reduced. For a plurality of addition operations, the adder may be time-division multiplexed in the manner described above.
For each second-order IIR filter of 128HZ, when the clock frequency of 1024HZ is adopted, the operation flow of filtering in the calculation formula (1) is shown in fig. 10, x (n), y (n) recorded in the register is loaded in the first period of 1024HZ, and beat processing is performed as shown in fig. 7, so as to obtain a feedback signal at the last moment; sequentially calling a multiplier to perform multiplication operation from the second period to the sixth period of 1024 Hz; calculating the difference between the zero and the pole sum in the seventh period of 1024 Hz; and outputting y (n) in the eighth period of 1024Hz, and completing filtering.
As an optional implementation manner of this embodiment, the feature extraction module 103 may include a band energy calculation module, configured to determine the energy of the electroencephalogram signal of the target band according to the following formula by using a booth code and a compressor:
where E (i) is the electroencephalogram signal energy of the frequency band i, N is the number of sampling points in one period, and X (m) is the energy level at the N points. Where the target band is 0-48 and 12 IIR filters with a bandwidth of 4HZ are integrated in IIR filter block 102, i e (1, 12) here.
In processing the square computation of equation (2) in feature extraction module 103, a Booth code is used, including a quasi-Booth code and a constraint-Booth code, and a compressor is used to generate and process the partial product.
The quasi-value Booth code, the multiplier is 24 bits, the multiplicand is 16 bits, and the operation principle is as follows: first, a "0" is added to the last bit of the multiplier, that is, the least significant bit, because each bit of the booth code is related to the last bit and the next bit of the booth code, and the least significant bit is not present, so that it is necessary to add a "0" to the last bit of the booth code, and zero addition does not affect the operation, then the multiplicand (at this time, the multiplicand has 25 bits in total, wherein 24 bits are the most significant bit of the multiplier, 1 bit is the least significant bit of the multiplier, and 0 bit has a value of 0) is cross-valued every three bits (i.e., 2-0,4-2,6-4,8-6, 10-8, 12-10, 14-12, 16-14, 18-16, 20-18, 22-18, 24-22 times), each 3 bits respectively corresponds to one of the partial product arrays (2-0 bits corresponds to the first row, 4-2 bits corresponds to the second row … …), and the partial product of the full set of the booth code has the following four portions, as shown in fig. 11: the method comprises the steps of expanding a sign bit (E), expanding the most significant bit (the middle bit of the expanding sign bit and the partial product is the same as the most significant bit number of the partial product), the partial product and taking the inverse carry (S), wherein the taking the inverse carry means taking the 1 adding step of adding 1 when the multiplier part corresponding to the partial product is a multiplicand of negative multiple, so that S=0 when the multiplier part corresponding to the partial product takes the positive multiple of the multiplicand, and S=1 when the multiplier part corresponding to the partial product takes the negative multiple.
First, the partial block and the inverse carry (S) are taken, the value of the inverse carry is shown in the following table 2, and when the multiplier bit corresponding to the partial block is 000, the value of the partial block is 0 (+0 times), and the inverse carry S is taken as 0; when the multiplication digits are 001 and 010, the numerical value of the partial product block is multiplicand (+1 times), and the inverse carry S is taken as 0; when the multiplication digit is 011, the multiplicand shifts left by one bit to take the lower 16 bits as the numerical value (+2 times) of the partial product block, and takes the inverse carry S to take 0; when the multiplication number is 100, the multiplicand shifts left by one bit to take the lower 16 bits for inversion to be used as the numerical value (-2 times) of the partial product block, and takes the inverted carry S to take 1; when the multiplication bits are 101 and 110, the multiplicand takes the inverse to be the numerical value (-1 times) of the partial product block, and takes the inverse carry S to take 1; when the multiplication digit is 111, the value of the partial product block is 0 (-0 times), and the inverse carry S is taken as 1.
TABLE 2
The following circuit formula can be derived from table 2 to calculate the inverted carry S:
the complete partial block also includes extended most significant bits (most significant bits) and extended sign bits (E). The most significant bit of expansion is 0 when the partial product block takes +0 or-0 times; when the partial product takes a positive multiple (excluding +0), the value of this bit takes the most significant bit of the multiplicand; when the partial product takes a negative multiple (excluding-0), the value of this bit is the value of the inverse of the most significant bit of the multiplicand, i.e., 0→1/1→0.
The extension sign bit is related to the value of the multiplicand and the partial block, when the highest bit of the multiplicand is 0, namely positive number and the partial block takes positive multiple (excluding +0), or when the highest bit of the multiplicand is 1, namely negative number and the partial block takes negative multiple (excluding-0), or the partial block takes +0 or-0 multiple, the extension sign bit E takes 1; correspondingly, when the multiplicand is negative and part of the blocks take positive multiples (excluding +0), or when the multiplicand is positive and part of the blocks take negative multiples (excluding-0), the extension sign bit E takes a value of 0.
As shown in FIG. 11, in the 24x16 quasi-value Booth coding of this embodiment, the first partial block is added before the partial block and has an extension sign bit E in addition to the extension most significant bit,Three bits, and the extension sign bit in front of the last part blocks is only E one bit, and the 10 rows in the middle are 1 and E two bits.
From the above description of the quasi-valued booth encoding, a truth table of quasi-valued booth encoded partial blocks can be obtained, as shown in table 3:
TABLE 3 Table 3
The logical expression of each bit of the partial product block can be reduced by using a truth table of quasi-booth encoding:
through verification, the extended most significant bit can be obtained by a logical expression through the sign bit of the extended multiplicand in advance, namely, the original 24-bit by 16-bit generation partial product block is converted into the 24-bit by 17-bit generation partial product block, so that a block of logic circuits for generating the extended most significant bit through a comparator and a selector can be saved.
According to the formula (3), the circuit corresponding to the quasi-value booth encoding includes 5 exclusive-or gates, 3 and 1 or gate and 1 not gate, in order to further reduce the operation complexity and the size of the logic circuit, the embodiment provides the approximate-value booth encoding truth table as shown in table 4.
TABLE 4 Table 4
From the above truth table 4, partial product pp can be deduced in a simplified manner ij Is a logical expression for each bit of:
by changing the values of the individual partial blocks in the table 3, the simplified logic expression only comprises 2 exclusive-OR gates and 1 AND gate, and compared with the quasi-value Booth coding, the complexity of the operation is greatly reduced, so that the circuit area is also greatly reduced, the operation speed is improved to a certain extent, and the power consumption is also reduced. As can be seen from truth table 4, the circled portions are compared to the varying portions of table 3, and the error rate of this approximate booth code is 4/32=12.5%.
In order to further reduce the computational complexity, the present embodiment also provides a radix booth encoding, as shown in table 5.
TABLE 5
According to the true valueTABLE 5 simplified derivation of partial block pp ij Is a logical expression for each bit of:
in the approximate value booth code corresponding to table 5, the logic expression is simpler, the chip area is correspondingly smaller, the operation speed is faster, the circled part is compared with the part changed in table 3, the theoretical error rate is 25%, but the method has both positive error and negative error, and the positive error and the negative error are cancelled in practical application, so the overall error rate can be basically kept within an acceptable range. The encoding method as in table 5 may also be selected to achieve approximate booth encoding for smaller area and faster operation. The choice of the about value booth code is not limited in this embodiment, and can be determined by one skilled in the art as needed.
After the coding scheme has been selected, the partial product arrays need to be summed, and the present embodiment uses an approximately 4-2 compressor. The 4-2 compressor, as shown in fig. 12, is formed by a cascade of two full adders, one 4-2 compressor having 5 inputs, 4 addend inputs and 1 carry from the lower bit, with a total of 3 outputs. The cascade for the 4-2 compressor is shown in FIG. 13, typically Cout for the upper stage and input for the lower stage of the Carry.
Since the 4-2 compressor uses a large number of exclusive-or gates and consumes a large amount of resources, the 4-2 compressor is considered to perform the reduction processing in order to further save the resources and increase the operation speed. The present embodiment provides a method for ignoring the low-order to high-order constraint value, i.e. ignoring Cout, and only outputting Carry as the input of the next stage, so that the next stage compressor reduces one-bit input Cin, and at the same time, in order to generate more redundancy terms, so that the logic expression can be more simplified, four-bit inputs can be converted first, and two new definitions, namely, a propagation signal (propagation) and a generation signal (generation), are introduced, and the corresponding logic expression is as follows:
P ij ＝X i +X j ；
G ij ＝X i *X j ；
the corresponding conversion logic expression at four inputs after introducing the propagation signal and generating the signal is:
Y 1 ＝P 13 ，Y 2 ＝G 13 ，Y 3 ＝X 2 ，Y 4 ＝Carryin；
the truth table after conversion is shown in table 6 below:
TABLE 6
| Y1 | Y2 | Y3 | Y4 | Carryout | Sum |
| 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 1 | 0 | 1 |
| 0 | 0 | 1 | 0 | 0 | 1 |
| 0 | 0 | 1 | 1 | 1 | 1 |
| 0 | 1 | 0 | 0 | X | X |
| 0 | 1 | 0 | 1 | X | X |
| 0 | 1 | 1 | 0 | X | X |
| 0 | 1 | 1 | 1 | X | X |
| 1 | 0 | 0 | 0 | 0 | 1 |
| 1 | 0 | 0 | 1 | 0 | 1 |
| 1 | 0 | 1 | 0 | 0 | 1 |
| 1 | 0 | 1 | 1 | 1 | 1 |
| 1 | 1 | 0 | 0 | 1 | 1 |
| 1 | 1 | 0 | 1 | 1 | 1 |
| 1 | 1 | 1 | 0 | 1 | 1 |
| 1 | 1 | 1 | 1 | 1 | 1 |
Simplifying the table 6 to obtain the logic expression of the 4-2 compressor after the reduced value processing:
Sum＝Y 1 +Y 3 +Y 4 ；
Carryout＝Y 2 +Y 3 *Y 4 ；
the original 4-2 quasi-value compressor can only process the summation of 3 rows of data, and in the case of more partial blocks, the 4-2 compressor subjected to the approximate value processing in the above manner can process the summation of 4 data, and at this time, the input of the compressor is changed from the original four input to five input, so that the input needs to be converted, and the five input is converted into the four input, and the logic expression of the conversion is as follows:
Y 1 ＝Carryin，Y 2 ＝G 14 +G 23 ，Y 3 ＝P 23 ，Y 4 ＝P 14 ；
then, Y1, Y2, Y3 and Y4 can be directly substituted into the logical expression of the 4-2 compressor after the about value processing, so that about value 5 can be obtained: sum and Carryout of 2 compressors.
As shown in fig. 14, the above-described booth encoding method and the procedure of the compressor calculating the square part of the formula (2) are performed three times in total, and the first time the compression is performed by the compressor, the quasi-value part generates 4 new partial products, and the approximate-value part generates 3 new partial products. The second time the compression is performed using the compressor, the quasi-valued part will generate 2 new partial products and the approximate-valued part will generate 1 new partial product. The third order criterion part adopts full adder cascade to obtain the upper 20 bits of the final result, and the lower 20 bits are the calculated result after the second order criterion part is compressed.
As an optional implementation manner of this embodiment, the electroencephalogram signal acquisition module is externally connected with the first gating clock module; the IIR filter module is externally connected with the second gating clock module; the signal synchronization module is externally connected with a third gating clock module.
The first gating clock module, the second gating clock module and the third gating clock module may be composed of the same circuits, and are used for controlling the working states of the modules connected with the first gating clock module, the specific circuit structure of the first gating clock module, the second gating clock module and the third gating clock module may be as shown in fig. 15, the enable signal end EN is connected with an external trigger signal, such as a bluetooth module located at the periphery of the electroencephalogram signal processing chip, and when the trigger signal of the bluetooth module is received, the start-up work of the corresponding connected module is controlled.
According to the electroencephalogram signal processing chip provided by the embodiment, the gating clock circuit is used for integrating the circuits in the whole chip, and a part of selectors in the circuits can be replaced, so that the area of the part of selectors is saved, meanwhile, the essence of the gating clock is to control whether a register works or not, and compared with the case that all the internal modules are in a working state for a long time as long as the chip is electrified, the gating clock can control the working state of the modules according to actual conditions, and the power consumption of the modules connected with the gating clock is reduced.
As an alternative implementation of this embodiment, the multiplier is a booth multiplier. Since the presence of feedback in the IIR filter results in error accumulation, a quasi-Booth multiplier is used to ensure proper function. Compared with the traditional multiplication unit, the Booth multiplier has fewer partial products, so that the full adder is less in use, and the Booth multiplier can directly process the signed number without processing the signed number in advance because the data participating in operation in filtering is the signed number.
The area of the electroencephalogram signal processing chip provided by the embodiment is shown in fig. 16, and the areas of other electroencephalogram signal processing chips are shown in fig. 17, so that the area of the electroencephalogram signal processing chip provided by the embodiment is reduced by 60% compared with the area of other electroencephalogram signal processing chips.
The present embodiment provides an electroencephalogram signal processing system, as shown in fig. 18, including:
the electroencephalogram signal processing chip 201 as in the above-described embodiment;
the bluetooth module 202 is connected to the electroencephalogram signal processing chip 201 in the above embodiment, and is used for transmitting the extracted electroencephalogram signal characteristics.
Illustratively, the Bluetooth module 202 may be a Bluetooth module with low power consumption, and in particular may be a cellular internet of things TLS-02 module, where the TLS-02 chip uses the URAT (Universal Asynchronous Receiver/Transmitter) protocol, and instructions may be sent to the electroencephalogram processing chip on the mobile device through the UART protocol. The UART protocol is shown in fig. 17, and each time the host transmits one byte (8 bits) of data to the slave for reception, the transmission signal is at a high level when idle, when the signal is pulled down for the first time, the start of data transmission is indicated, the next eight bits of data are output data, and when the transmission is completed, the signal is pulled up again and returns to an idle state. In this embodiment, the counter is used to count the transferred bytes, and once every 4 bytes are transferred, the data of at most 32 bits can be sent to the register at a time, and the data of 32 bits can meet the use requirement.
The electroencephalogram signal processing system provided by the embodiment can realize data interaction through the external Bluetooth module, is used for controlling the electroencephalogram signal processing chip and receiving information sent by the electroencephalogram signal processing chip so as to form a wearable device, can be used for monitoring neurological diseases such as epilepsy and the like, and can also be used for judging human emotion to people.
As an alternative implementation of this embodiment, as shown in fig. 18, the method further includes:
the analog-to-digital conversion module 203 is connected to the electroencephalogram signal processing chip in the above embodiment, and is configured to convert an analog electroencephalogram signal into a digital electroencephalogram signal, and the analog-to-digital conversion module 203 may be an ADS1299 chip.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While still being apparent from variations or modifications that may be made by those skilled in the art are within the scope of the invention.
Claims (3)
1. An electroencephalogram signal processing chip, characterized by comprising:
the electroencephalogram signal acquisition module is used for acquiring electroencephalogram signals;
the IIR filter module is used for filtering the target frequency band of the electroencephalogram signal;
the characteristic extraction module is connected with the IIR filter and is used for extracting characteristics of the electroencephalogram signals of the target frequency band; the feature extraction module includes: the frequency band energy calculation module is used for solving the following formulas according to the Booth code and the compressor to determine the energy of the electroencephalogram signals of the target frequency band:
，
wherein E (i) is the electroencephalogram signal energy of a frequency band i, N is the number of sampling points in one period, and X (m) is the energy at the N point; the target frequency band is 0-48HZ;
the signal synchronization module is connected with the electroencephalogram signal acquisition module at one end and the IIR filter module at the other end, and is used for performing synchronization processing on the electroencephalogram signals; the signal synchronization module comprises: at least two stages of registers for reducing metastability probability; the counter is connected with the output ends of the at least two stages of registers and is used for expanding the period length of the output level of the at least two stages of registers to the target period length so as to realize signal synchronization;
the electroencephalogram signal acquisition module is externally connected with a first gating clock module;
the IIR filter module is externally connected with a second gating clock module; the IIR filter module is formed by cascading eight second-order IIR filters, the second-order IIR filters comprise multipliers and adders, the second-order IIR filters adopt a first clock frequency to call the multipliers to achieve multiplication operation or adopt the first clock frequency to call the adders to achieve addition operation, and the first clock frequency is higher than the working frequency of the second-order IIR filters; the multiplier is a booth multiplier;
and the signal synchronization module is externally connected with a third gating clock module.
2. An electroencephalogram signal processing system, characterized by comprising:
the electroencephalogram signal processing chip according to claim 1;
the bluetooth module is connected with the electroencephalogram signal processing chip according to claim 1 and is used for transmitting the extracted electroencephalogram signal characteristics.
3. The electroencephalogram signal processing system according to claim 2, further comprising:
the analog-to-digital conversion module is connected with the electroencephalogram signal processing chip according to claim 1 and used for converting analog electroencephalogram signals into digital electroencephalogram signals.
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| CN108431699A (en) * | 2015-12-23 | 2018-08-21 | 马克斯·普朗克科学促进学会 | The clock of high efficient and reliable in hardware synchronizes |
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