CN112946995A - Mask and method for forming semiconductor structure - Google Patents

Mask and method for forming semiconductor structure Download PDF

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Publication number
CN112946995A
CN112946995A CN201911259659.8A CN201911259659A CN112946995A CN 112946995 A CN112946995 A CN 112946995A CN 201911259659 A CN201911259659 A CN 201911259659A CN 112946995 A CN112946995 A CN 112946995A
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China
Prior art keywords
pattern
layer
hard mask
mask
material layer
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CN201911259659.8A
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Chinese (zh)
Inventor
游林
张婉娟
陈术
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN201911259659.8A priority Critical patent/CN112946995A/en
Publication of CN112946995A publication Critical patent/CN112946995A/en
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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • G03F7/2022—Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70466—Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)

Abstract

A method for forming a mask and a semiconductor structure, the mask comprising: the first mask comprises a main pattern and an inverted auxiliary pattern positioned in the main pattern; the second mask plate is matched with the first mask plate and comprises a compensation pattern, the light transmission characteristic of the compensation pattern is opposite to that of the reversed auxiliary pattern, and the projection of the compensation pattern on the first mask plate covers the reversed auxiliary pattern and is positioned in the main pattern. The mask plate of the embodiment of the invention also comprises a second mask plate matched with the first mask plate, if the reversed-phase auxiliary pattern in the first mask plate develops a pattern in the photoetching process, the pattern formed by the reversed-phase auxiliary pattern in the photoetching process can be removed by utilizing the second mask plate, so that a target pattern meets the design requirement, the size of the reversed-phase auxiliary pattern is not required to be reduced for preventing the problem of developing the reversed-phase auxiliary pattern in the photoetching process, the process window for forming the mask plate and the process window for photoetching are favorably increased, and the pattern transfer precision is improved.

Description

Mask and method for forming semiconductor structure
Technical Field
The embodiment of the invention relates to the field of semiconductor manufacturing, in particular to a mask and a method for forming a semiconductor structure.
Background
The photoetching technology is a vital technology in the semiconductor manufacturing technology, and can realize the transfer of a pattern from a mask to the surface of a silicon wafer to form a semiconductor product meeting the design requirement. The photolithography process includes an exposure step, a development step performed after the exposure step, and an etching step after the development step. In the exposure step, light irradiates on a silicon wafer coated with photoresist through a light-transmitting area in a mask plate, and the photoresist undergoes a chemical reaction under the irradiation of the light; in the developing step, photoetching patterns are formed by utilizing the different dissolution degrees of photosensitive and non-photosensitive photoresist to a developer, so that the mask pattern is transferred to the photoresist; in the etching step, the silicon wafer is etched based on the photoetching pattern formed by the photoetching adhesive layer, and the pattern of the mask is further transferred to the silicon wafer.
In semiconductor manufacturing, as the design size is continuously reduced and the design size is closer to the limit of the lithography imaging system, the diffraction Effect of light becomes more and more obvious, which causes the Optical image degradation of the design pattern, the actual formed lithography pattern is seriously distorted relative to the pattern on the mask, and the actual pattern and the design pattern formed by lithography on the silicon wafer are different, and this phenomenon is called Optical Proximity Effect (OPE). Sub-Resolution Assist Features (Sub-Resolution Assist Features), Optical Proximity Correction (OPC), Inverse Lithography (ILT), Double Patterning, Self-aligned Double Patterning, and the like are used to improve the Lithography Resolution.
A Scattering Bar (SB) is a sub-resolution auxiliary graph, and auxiliary graph bars are arranged around a Main graph (Main Feature), so that a sparse graph is similar to a dense graph in an optical angle, the uniformity of a focal depth and a process window is improved, the process difference caused by different graph densities in an integrated circuit layout is reduced, the common process window of photoetching is increased, and the photoetching quality of the Main graph is improved. Wherein, the main pattern is an exposable pattern, and the scattering bars are usually non-exposable patterns.
Disclosure of Invention
The embodiment of the invention provides a mask and a method for forming a semiconductor structure, and aims to enlarge a photoetching process window.
To solve the above problems, an embodiment of the present invention provides a mask, including: the first mask comprises a main pattern and an inverted auxiliary pattern positioned in the main pattern; the second mask plate is matched with the first mask plate and comprises a compensation graph, the light transmission characteristic of the compensation graph is opposite to that of the reversed-phase auxiliary graph, and the projection of the compensation graph on the first mask plate covers the reversed-phase auxiliary graph and is located in the main graph.
Optionally, the reversed auxiliary pattern is a long strip-shaped structure, and a distance from a long edge of the reversed auxiliary pattern to a corresponding edge on the same side of the main pattern is greater than or equal to 15 nm.
Optionally, the inverted auxiliary pattern has a strip structure, the length of the inverted auxiliary pattern is greater than or equal to 40nm, and the distance from the short edge of the inverted auxiliary pattern to the corresponding edge on the same side of the main pattern is greater than or equal to 15 nm.
Optionally, the distance from the projection of the long side of the compensation pattern on the first mask to the long side of the same side of the reversed-phase auxiliary pattern is 2nm to 5 nm.
Optionally, the inverted auxiliary pattern is a developable pattern.
Optionally, the width of the reverse auxiliary pattern is greater than or equal to 15nm,
optionally, the main pattern is a shading pattern, the reverse phase auxiliary pattern is a light-transmitting pattern, and the compensation pattern is a shading pattern.
Optionally, the main pattern is a transparent pattern, the reverse phase auxiliary pattern is a light-shielding pattern, and the compensation pattern is a transparent pattern.
Correspondingly, an embodiment of the present invention further provides a method for forming a semiconductor structure, including: providing a substrate; forming a hard mask material layer on the substrate; forming a first graphic layer on the hard mask material layer by adopting a first mask in the masks; patterning the hard mask material layer by taking the first pattern layer as a mask; forming a second graphic layer on the hard mask material layer by adopting a second mask in the masks; patterning the hard mask material layer by taking the second pattern layer as a mask; patterning the hard mask material layer by taking the first graphic layer as a mask, and patterning the hard mask material layer by taking the second graphic layer as a mask, wherein the remaining hard mask material layer is taken as a hard mask layer; and patterning the substrate by taking the hard mask layer as a mask to form a target pattern.
Optionally, the step of forming the hard mask material layer includes: forming a bottom hard mask material layer on the substrate; a top hard mask material layer is formed on the bottom hard mask material layer.
Optionally, with the first pattern layer as a mask, the step of patterning the hard mask material layer includes: patterning the top hard mask material layer by taking the first pattern layer as a mask to form a first hard mask layer, wherein an initial pattern corresponding to the reverse auxiliary pattern is formed in the first hard mask layer; after the first graph layer is used as a mask and the top hard mask material layer is patterned, forming a second graph layer on the bottom hard mask material layer, wherein the second graph layer covers the initial graph; and with the second graphic layer as a mask, the step of patterning the hard mask material layer comprises: and patterning the bottom hard mask material layer by taking the second patterning layer and the first hard mask layer as masks to form a second hard mask layer, wherein the second hard mask layer is used as the hard mask layer.
Optionally, with the second pattern layer as a mask, the step of patterning the hard mask material layer includes: patterning the top hard mask material layer by taking the second patterning layer as a mask to form a first hard mask layer; after the second graph layer is used as a mask and the top hard mask material layer is patterned, forming a first graph layer on the bottom hard mask material layer, wherein an initial graph is formed in the first graph layer, and the projection of the initial graph on a substrate is positioned in the first hard mask layer; with the first patterning layer as a mask, the step of patterning the hard mask material layer includes: and patterning the bottom hard mask material layer by taking the first pattern layer and the first hard mask layer as masks to form a second hard mask layer, wherein the second hard mask layer is used as the hard mask layer.
Optionally, the step of forming the first graphic layer includes: forming a first pattern material layer on the hard mask material layer; and carrying out exposure and development treatment on the first graphic material layer by adopting a first mask plate in the mask plates to form the first graphic layer.
Optionally, the main pattern is a light-transmitting pattern, and in the step of performing exposure and development processing on the first pattern material layer, a negative development process is used for performing development processing; or, the main pattern is a shading pattern, and in the step of carrying out exposure and development processing on the first pattern material layer, development processing is carried out by adopting a forward development process.
Optionally, the step of forming the second graphic layer includes: forming a second pattern material layer on the hard mask material layer; and carrying out exposure and development treatment on the second graphic material layer by adopting a second mask plate in the mask plates to form the second graphic layer.
Optionally, the main pattern is a light-transmitting pattern, and in the step of performing exposure and development processing on the second pattern material layer, a negative development process is used for performing development processing; or, the main pattern is a shading pattern, and in the step of carrying out exposure and development processing on the first pattern material layer, development processing is carried out by adopting a forward development process.
Optionally, the target pattern is an island-like structure.
Optionally, the target pattern is an island-shaped structure; the initial pattern is a trench.
Optionally, the material of the first pattern layer includes photoresist.
Optionally, the material of the second pattern layer includes photoresist.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
the mask provided by the embodiment of the invention comprises a first mask and a second mask, wherein the first mask is internally provided with an inverted auxiliary graph positioned in a main graph, and the inverted auxiliary graph is used for preventing the problem of contact (Bridge) between actual graphs formed on a substrate when the distance between adjacent main graphs is short; the second mask plate and the first mask plate are matched with each other for use, the light transmission characteristic of a compensation pattern in the second mask plate is opposite to that of an inverted auxiliary pattern, the projection of the compensation pattern on the first mask plate covers the inverted auxiliary pattern and is positioned in the main pattern, if the inverted auxiliary pattern in the first mask plate develops a pattern in a photoetching process, the pattern developed on the substrate by the inverted auxiliary pattern can be removed by using the second mask plate, so that a formed target pattern meets the design requirement, and the embodiment of the invention does not need to reduce the size of the inverted auxiliary pattern in order to prevent the problem of developing the inverted auxiliary pattern in the photoetching process, thereby being beneficial to increasing the process window for forming the mask plate, increasing the window of the photoetching process and improving the pattern transfer precision.
Drawings
FIG. 1 is a schematic diagram of a mask;
FIG. 2 is an actual pattern formed on a wafer by photolithography using the mask of FIG. 1 as a mask;
FIG. 3 is a schematic structural diagram of another mask;
FIG. 4 is an actual pattern formed on a wafer by photolithography using the mask of FIG. 3 as a mask;
FIGS. 5 and 6 are schematic structural views of a first reticle in an embodiment of a reticle of the present invention;
FIGS. 7 and 8 are schematic structural views of a second reticle in an embodiment of the reticle of the present invention;
FIGS. 9-15 are schematic structural diagrams corresponding to steps of a method of forming a semiconductor structure according to an embodiment of the present invention;
fig. 16 to 21 are schematic structural diagrams corresponding to steps in another embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
As is known from the background art, the actually formed lithographic pattern is easily distorted with respect to the pattern on the reticle, and the actual pattern and the design pattern formed by lithography on the silicon wafer are different.
For example, referring to FIG. 1, a reticle is shown having a plurality of main features 1 therein. When photolithography is performed using the reticle as a mask, as shown in fig. 2, the actual patterns 2 formed on the wafer are easily distorted, and particularly, when the main patterns 1 have a large feature size and a small space (space), the actual patterns 2 formed on the wafer are easily contacted (bridge) (as shown by a dotted frame in fig. 2).
Referring to fig. 3 and 4 in combination, a schematic structural diagram of another reticle and an actual pattern formed on a wafer by photolithography using the reticle in fig. 3 as a mask are respectively shown.
In order to solve the above problem, one method at present is to add a Reverse Sub Resolution assist Feature (Reverse SRAF)4 to the main pattern 3, where the light transmission characteristic of the Reverse assist Feature 4 is opposite to that of the main pattern 3, and the Reverse assist Feature 4 is located in the main pattern 3, which is beneficial to improving the problem of contact (bridge) of the main pattern 3 with large size and small space during photolithography, so that the actual pattern 5 formed on the wafer meets the design requirement.
The reverse auxiliary pattern 4 only plays a role in scattering light, and the reverse auxiliary pattern 4 is not transferred onto a wafer in the photoetching process, so that the target pattern is prevented from being influenced.
However, as the process node advances further, the resolution of the photolithography process is gradually improved, which easily causes the reversed auxiliary pattern to be developed on the wafer during the photolithography process, which easily reduces the precision of pattern transfer, and the actual pattern formed on the wafer is difficult to meet the design requirement.
Therefore, in order to prevent the reverse auxiliary pattern from developing on the wafer, the current method is to narrow the line width of the reverse auxiliary pattern.
However, reducing the line width of the inverted assist pattern easily causes the following two problems:
first, if the inverse auxiliary pattern is too small, the requirement for space dimensional accuracy is high to prevent the problem of bridge between adjacent patterns during photolithography, but this reduces the process window for forming the main patterns, particularly the spaces between adjacent main patterns.
Secondly, the line width of the reversed phase auxiliary pattern is too small, which is easy to increase the difficulty of forming a mask, for example: the precision of the process for forming the mask is difficult to achieve the line width of the reverse auxiliary pattern, and further the process window for forming the mask is reduced.
In order to solve the technical problem, an embodiment of the present invention provides a mask, including: the first mask comprises a main pattern and an inverted auxiliary pattern positioned in the main pattern; the second mask plate is matched with the first mask plate and comprises a compensation graph, the light transmission characteristic of the compensation graph is opposite to that of the reversed-phase auxiliary graph, and the projection of the compensation graph on the first mask plate covers the reversed-phase auxiliary graph and is located in the main graph.
The mask provided by the embodiment of the invention comprises a first mask and a second mask, wherein the first mask is internally provided with an inverted auxiliary graph positioned in a main graph, and the inverted auxiliary graph is used for preventing the problem of contact (Bridge) between actual graphs formed on a substrate when the distance between adjacent main graphs is short; the second mask plate and the first mask plate are matched with each other for use, the light transmission characteristic of a compensation pattern in the second mask plate is opposite to that of an inverted auxiliary pattern, the projection of the compensation pattern on the first mask plate covers the inverted auxiliary pattern and is positioned in the main pattern, if the inverted auxiliary pattern in the first mask plate develops a pattern in a photoetching process, the pattern developed on the substrate by the inverted auxiliary pattern can be removed by using the second mask plate, so that a formed target pattern meets the design requirement, and the embodiment of the invention does not need to reduce the size of the inverted auxiliary pattern in order to prevent the problem of developing the inverted auxiliary pattern in the photoetching process, thereby being beneficial to increasing the process window for forming the mask plate, increasing the window of the photoetching process and improving the pattern transfer precision.
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.
Referring to fig. 5 to 8, schematic structural diagrams of the first reticle and the second reticle in an embodiment of the reticle of the present invention are shown. Fig. 5 and 6 show a top view and a partial cross-sectional view of an embodiment of the first reticle of the present invention, respectively, and fig. 7 and 8 show a top view and a partial cross-sectional view of an embodiment of the first reticle of the present invention, respectively.
The mask plate comprises: a first mask 10 including a main pattern 11 and an inverted auxiliary pattern 12 in the main pattern 11; the second mask 20, which is matched with the first mask 10, includes a compensation pattern 21, the light transmission characteristic of the compensation pattern 21 is opposite to the light transmission characteristic of the inverse auxiliary pattern 12, and the projection of the compensation pattern 21 on the first mask 10 covers the inverse auxiliary pattern 21 and is located in the main pattern 11.
The mask provided by the embodiment of the invention comprises a first mask 10 and a second mask 20, wherein the first mask 10 is provided with an inverted auxiliary pattern 12 positioned in a main pattern 11, and the inverted auxiliary pattern 12 is used for preventing the problem of contact (Bridge) between actual patterns formed on a substrate when the distance between adjacent main patterns 11 is short; the second mask 20 and the first mask 10 are used in cooperation, the light transmission characteristic of the compensation pattern 21 in the second mask 20 is opposite to the light transmission characteristic of the inverse auxiliary pattern 12, the projection of the compensation pattern 21 on the first mask 10 covers the inverse auxiliary pattern 12 and is located in the main pattern 11, if the reverse-phase auxiliary pattern 12 in the first reticle 10 is developed into a pattern during the photolithography process, the developed pattern of the reverse-phase auxiliary pattern 12 on the substrate can be removed by using the second reticle 20, so that the formed target pattern meets the design requirements, and the embodiment of the present invention does not need to reduce the size of the reverse phase auxiliary pattern 12 in order to prevent the problem of developing the reverse phase auxiliary pattern during photolithography, therefore, the method is beneficial to enlarging the process window for forming the mask and the window for the photoetching process, and improves the precision of pattern transfer.
The first Mask 10 is a Mask Reticle (Mask Reticle) used as a Mask (Mask) for selectively exposing a Photoresist (PR), so as to pattern the Photoresist and further transfer a pattern.
Specifically, the first mask 10 is used as a mask to expose photoresist on the wafer to form a photoresist pattern of each chip region on the wafer, and the photoresist pattern can be used to etch the chip region of the wafer and form semiconductor structures such as a gate, a metal interconnection line, or a conductive plug in the chip region of the wafer.
The first reticle 10 may be a photolithography reticle or a projection reticle.
Referring to fig. 6 in combination, a schematic partial cross-sectional view of a first mask 10 in an embodiment of the present invention is shown, where the first mask 10 includes a first substrate 13 and a first light-shielding layer 14 located below the first substrate 13, and a light transmittance of the first substrate 14 is greater than a light transmittance of the light-shielding layer 14.
In this embodiment, the first substrate 13 is made of a transparent substrate, so that light rays can pass through the substrate during exposure.
In this embodiment, the material of the first substrate 13 is Quartz (Quartz).
In this embodiment, the first light shielding layer 14 is made of an opaque material, and can have a strong reflection effect or a strong refraction effect on light during exposure, so as to block a portion of light, further implement selective exposure on the photoresist, and correspondingly implement transfer of the pattern on the first mask 10 onto the photoresist.
In this embodiment, the first light shielding layer 14 is a chromium layer. The chromium layer has a very low light transmittance and is substantially completely opaque to light, which is advantageous for improving the light blocking effect of the first light-shielding layer 14.
The first mask 10 includes a main pattern 11, and an inverted auxiliary pattern 12 positioned in the main pattern 11.
Wherein the main pattern 11 corresponds to a target pattern formed on a wafer.
In this embodiment, the main pattern 11 is a rectangular pattern.
In this embodiment, the main patterns 11 have a larger line width, and the main patterns 11 have a smaller space (space) therebetween.
As shown in fig. 6, in the present embodiment, the main pattern 11 is located in a light-transmitting region of the first mask 10, that is, the main pattern 11 is a light-transmitting pattern.
The reversed auxiliary pattern 12 is used to adjust the light distribution and the optical intensity of the light passing through the first reticle 10 during exposure, so that the asymmetry of the optical intensity in different directions or the difference of the optical intensity in different directions is reduced.
In this embodiment, the light transmission characteristics of the inverted auxiliary pattern 12 and the main pattern 11 are opposite.
The inverse auxiliary pattern 12 is opposite to the light transmission characteristic of the main pattern 11 in the sense that: when the main pattern 11 is a pattern that is completely transparent to light, the inverted auxiliary pattern 12 is a pattern that is completely opaque to light, or when the main pattern 11 is a pattern that is not completely transparent to light, for example: when the light transmittance of the main pattern 11 is 90%, the light transmittance of the reverse phase auxiliary pattern 12 is 10%.
Specifically, the inverted auxiliary pattern 12 is located in the main pattern 11, and the light transmission characteristic of the inverted auxiliary pattern 12 is opposite to that of the main pattern 11, that is, the light transmission characteristic of the inverted auxiliary pattern 12 is the same as that of the space (space), so that the density of the space (space) is increased, and the distribution density of the patterns on the first mask 11 is adjusted to reduce the difference in the pattern density on the first mask 11, thereby being beneficial to preventing the problem of contact between actual patterns formed on the substrate when the distance between adjacent main patterns 11 is short.
In this embodiment, the inverse auxiliary pattern 12 is located in a shielding region of the first mask 10 according to the light transmission characteristics of the main pattern 11, that is, the inverse auxiliary pattern 12 is a shielding pattern.
In this embodiment, the reverse auxiliary pattern 12 is a developable pattern, that is, the line width of the reverse auxiliary pattern 12 is greater than or equal to the critical dimension of the resolution of the photolithography process.
In this embodiment, the inverted auxiliary pattern 12 is a strip structure.
In this embodiment, the width of the reverse auxiliary pattern 12 is greater than or equal to 15nm, so as to ensure that the reverse auxiliary pattern 12 can be developed and to increase the process window for forming the first mask 10.
In this embodiment, the distance from the long side of the inverted auxiliary pattern 12 to the long side of the main pattern 11 on the same side is greater than or equal to 15 nm.
In this embodiment, the length of the inverted auxiliary pattern 12 is greater than or equal to 40nm, and the distance from the inverted auxiliary pattern 12 to the short side of the main pattern 11 on the same side is greater than or equal to 15 nm.
The second mask 20 is also used as a mask to expose the photoresist on the wafer to form a photoresist pattern of each chip region on the wafer, and the photoresist pattern can be used to etch the chip region of the wafer and form semiconductor structures such as a gate, a metal interconnection line or a conductive plug in the chip region of the wafer.
The second mask 20 may be a photolithography mask or a projection mask.
The second mask 20 is used in cooperation with the first mask 10.
Specifically, when the reverse-phase auxiliary pattern 12 in the first reticle 10 is developed during the photolithography process, the developed pattern of the reverse-phase auxiliary pattern 12 on the substrate can be removed by using the second reticle 20, so that the target pattern formed on the substrate meets the design requirements.
In this embodiment, the first mask 10 includes a second substrate 23 and a second light shielding layer 24 located below the second substrate 23, and a light transmittance of the second substrate 23 is greater than a light transmittance of the second light shielding layer 24.
In this embodiment, the material of the second substrate 23 is quartz. For a detailed description of the second substrate 23, reference may be made to the foregoing detailed description of the first substrate 13, and this embodiment is not repeated herein.
In this embodiment, the second light shielding layer 24 is a chromium layer. The chromium layer has a very low light transmittance and is substantially completely opaque to light, which is advantageous for improving the light blocking effect of the second light-shielding layer 24.
In this embodiment, the light transmission characteristic of the compensation pattern 21 is opposite to the light transmission characteristic of the inverted auxiliary pattern 12. The light transmission characteristic of the compensation pattern 21 is opposite to that of the reverse auxiliary pattern 12 in the sense that: when the reverse phase auxiliary pattern 12 is a pattern that is completely light-shielded, the compensation pattern 21 is a pattern that is completely light-transmissive, or when the reverse phase auxiliary pattern 12 is a pattern that is not completely light-shielded, for example: when the light transmittance of the reverse auxiliary pattern 12 is 10%, the light transmittance of the compensation pattern 21 is 90%.
The projection of the compensation pattern 21 on the first mask 10 covers the inverse auxiliary pattern 12 and is located in the main pattern 11, so as to ensure that when the inverse auxiliary pattern 12 is developed during the photolithography process, the developed pattern of the inverse auxiliary pattern 12 on the substrate can be removed by using the compensation pattern 21 in the second mask 20, and the developed pattern of the main pattern 11 in the first mask 10 is not affected.
Referring to fig. 6 in combination, in the embodiment, the compensation pattern 21 is located in the light-transmitting region of the second mask 20 according to the light-transmitting characteristics of the main pattern 11 and the inverted auxiliary pattern 12, that is, the compensation pattern 21 is a light-transmitting pattern, so that the compensation pattern 21 is opposite to the light-transmitting characteristics of the inverted auxiliary pattern 12.
In the present embodiment, the main pattern 11 is a light-transmitting pattern, the inverted auxiliary pattern 12 is a light-shielding pattern, and the compensation pattern 21 is a light-transmitting pattern. Correspondingly, the photoresist is exposed by using the first mask 10 as a mask, Negative Tone Development (NTD) is performed, and a pattern corresponding to the main pattern 11 formed on the substrate is an Island-shaped structure (Island).
In other embodiments, the main pattern may be a light-shielding pattern according to actual process requirements, and accordingly, the reverse-phase auxiliary pattern is a light-transmitting pattern, and the compensation pattern is a light-shielding pattern. Correspondingly, the photoresist is exposed by taking the first mask as a mask, and then Positive development (PTD) is performed, so that a pattern corresponding to the main pattern formed on the substrate subsequently is an island-shaped structure.
In other embodiments, the main pattern and the reverse auxiliary pattern may not be completely transparent or not completely opaque, i.e., semitransparent, patterns according to the actual process. For example: when the light transmittance of the main pattern is 90%, the light transmittance of the reverse phase auxiliary pattern may be 10%, and the light transmittance of the compensation pattern may be 90%; alternatively, for example: when the light transmittance of the main pattern is 10%, the light transmittance of the inversion auxiliary pattern may be 90% and the light transmittance of the compensation pattern may be 10%.
In this embodiment, the compensation pattern 21 is a strip structure.
It should be noted that the projection distance from the long side of the compensation pattern 21 on the first mask 10 to the long side of the inverted auxiliary pattern 12 is not too large, otherwise, too large Overlap (Overlap) is easily caused, and further, the difficulty of the subsequent photolithography process is easily increased, and side effects are generated. For this reason, in this embodiment, the projection distance of the long side of the compensation pattern 21 on the first mask 10 to the long side of the inverted auxiliary pattern 12 is less than or equal to 5 nm.
Meanwhile, in consideration of actual process errors, process fluctuations and the like, in this embodiment, the projection of the long side of the compensation pattern 21 on the first mask 10 is 2nm to 5nm from the long side of the inverted auxiliary pattern 12, so as to ensure that the compensation pattern 21 can cover the inverted auxiliary pattern 12 and that a pattern formed by the second mask 10 subsequently can cover a pattern formed by the inverted auxiliary pattern 12.
Correspondingly, the invention also provides a forming method of the semiconductor structure. Referring to fig. 9 to 15, schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure of the present invention are shown.
Referring to fig. 9, a substrate 100 is provided.
The substrate 100 is used for providing a process platform for a process, and the substrate 100 is also used as a film layer to be patterned.
The substrate 100 may include a film layer to be etched for forming an interconnection line, a contact hole plug, a gate electrode, and the like.
NMOS, PMOS and other devices may also be formed in the substrate 100, and functional structures such as resistors and capacitors may also be formed in the substrate 100.
With continued reference to fig. 9, a layer of hard mask material is formed on the substrate 100.
The hard mask material layer is used as a layer to be etched in a subsequent patterning process.
In this embodiment, the step of forming the hard mask material layer includes: forming a bottom hard mask material layer 110 on the substrate 100; a top hard mask material layer 120 is formed on the bottom hard mask material layer 110.
The hard mask material layer comprises a bottom hard mask material layer 110 and a top hard mask material layer 120 located on the bottom hard mask material layer 110, so that the bottom hard mask material layer 110 and the top hard mask material layer 120 correspond to one mask respectively in a subsequent patterning process.
The material of the bottom hard mask material layer 110 is different from the material of the top hard mask material layer 120.
In this embodiment, the bottom hard mask material layer 110 is made of silicon oxide. In other embodiments, the material of the bottom hard mask material layer may also be silicon nitride or silicon oxynitride.
The top hard mask layer material layer 120 is selected from a material having a greater etch selectivity than the bottom hard mask layer material layer 110. In this embodiment, the top hard mask material layer 120 is made of silicon nitride.
In this embodiment, the bottom hard mask material layer 110 and the top hard mask material layer 120 are formed by a deposition process. The deposition process may be a chemical vapor deposition process or an atomic layer deposition process.
With continued reference to fig. 9, a first patterning layer 112 is formed on the hard mask material layer using the first reticle 10 of the reticles of the previous embodiments.
The first patterning layer 112 is used as a mask for patterning the hard mask material layer.
As can be seen from the foregoing embodiments, the first mask 10 is provided with the inverted auxiliary patterns 12 located in the main patterns 11, and the inverted auxiliary patterns 12 are used to prevent the problem of contact (bridge) between corresponding actual patterns formed on the substrate 100 when the distance between adjacent main patterns 11 is short, and the embodiment of the present invention does not need to reduce the size of the inverted auxiliary patterns 12 in order to prevent the problem of development of the inverted auxiliary patterns during photolithography, thereby facilitating the increase of the window of the photolithography process and improving the precision of pattern transfer.
In this embodiment, the first pattern layer 112 is made of photoresist.
In this embodiment, the step of forming the first graphic layer 112 includes: forming a first pattern material layer (not shown) on the hard mask material layer; the first mask 10 in the previous embodiment is used to perform exposure and development processing on the first pattern material layer to form the first pattern layer 112.
In this embodiment, the first pattern material layer is formed by a coating (coating) process.
In this embodiment, the material of the first pattern material layer is photoresist. Specifically, in this embodiment, the material of the first pattern material layer is a positive photoresist.
In this embodiment, the main pattern 11 in the first mask 10 is a light-transmitting pattern, and the inverted auxiliary pattern 12 is a light-shielding pattern, so that in the step of performing exposure and development processing on the first pattern material layer, Negative development (NTD) processing is performed on the first pattern material layer, that is, after the first pattern material layer is exposed by using the first mask 10, the adopted developing solution can remove the portion of the first pattern material layer that is not irradiated by light, so that after the first pattern layer 112 is formed, protrusions (island-shaped structures) corresponding to the main pattern 11 and recesses corresponding to the inverted auxiliary pattern 12 are formed in the first pattern layer 112.
In other embodiments, when the main pattern in the first mask is a light-shielding pattern and the reverse auxiliary pattern is a light-transmitting pattern, in the step of performing exposure and development processing on the first pattern material layer, a positive development (PTD) process is used for performing development processing, so that after the first pattern layer is formed, protrusions (island structures) corresponding to the main pattern and recesses corresponding to the reverse auxiliary pattern are formed in the first pattern layer
In this embodiment, before forming the first pattern layer 112 on the hard mask material layer, the method for forming the semiconductor structure further includes: a first anti-reflective coating 111 is formed on the hard mask material layer.
The first anti-reflection coating 111 is used for reducing the reflection effect during exposure, so that the pattern transfer precision is improved, and the appearance quality and the size precision of the first pattern layer 112 are improved. In this embodiment, the material of the first anti-reflective coating 111 is Si-ARC (Silicon-containing anti-reflective coating). In other embodiments, the material of the first Anti-reflective Coating layer may also be a Bottom Anti-reflective Coating (BARC) material or a Dielectric Anti-reflective Coating (DARC) material.
Referring to fig. 10 and 11 in combination, fig. 11 is a partial top view corresponding to fig. 10, and the hard mask material layer is patterned by using the first pattern layer 112 as a mask.
In this embodiment, with the first pattern layer 112 as a mask, the step of patterning the hard mask material layer includes: and patterning the top hard mask material layer 120 by using the first pattern layer 112 as a mask to form a first hard mask layer 130, wherein an initial pattern corresponding to the reverse auxiliary pattern 12 is formed in the first hard mask layer 130.
In this embodiment, the initial pattern is a trench 135.
In this embodiment, a dry etching process is adopted, for example: an anisotropic dry etch process patterns the top hard mask material layer 120. The dry etching process has better etching profile controllability and high etching precision, and is favorable for improving the precision of pattern transfer.
In this embodiment, in the step of patterning the hard mask material layer by using the first pattern layer 112 as a mask, the first pattern layer 112 and the first anti-reflective coating 111 are also gradually consumed, so that after the first hard mask layer 130 is formed, the first pattern layer 112 and the first anti-reflective coating 111 are already removed.
In other embodiments, after patterning the hard mask material layer by using the first pattern layer as a mask, the first pattern layer and the first anti-reflective coating layer may also remain a part of the thickness. Correspondingly, the forming method of the semiconductor structure further comprises the following steps: and removing the first pattern layer and the first anti-reflection coating. Specifically, the first pattern layer and the first anti-reflective coating layer may be removed using one or both of an ashing process and a wet stripping process.
Referring to fig. 12, a second pattern layer 122 is formed on the hard mask material layer using the second reticle 20 of the reticles of the previous embodiments.
The second patterning layer 122 is used as a mask for patterning the hard mask material layer.
Specifically, the second pattern layer 122 is used to remove the initial pattern formed in the previous step corresponding to the inverted auxiliary pattern 12, thereby ensuring that the actual pattern formed on the substrate 100 meets the design requirements.
In this embodiment, the compensation pattern 21 is a transparent pattern, and the second pattern layer 122 is a protrusion (an island structure) corresponding to the compensation pattern 21.
In this embodiment, after patterning the top hard mask material layer 120 by using the first pattern layer 112 as a mask, the second pattern layer 122 is formed on the bottom hard mask material layer 110, the second pattern layer 122 covers the initial pattern, and a projection of the second pattern layer 122 on the substrate 100 is located in the first hard mask layer 130.
In this embodiment, the material of the second pattern layer 122 includes photoresist.
In this embodiment, the step of forming the second graphic layer 122 includes: forming a second pattern material layer (not shown) on the hard mask material layer; the second patterning material layer is exposed and developed by using the second reticle 20 in the previous embodiment, so as to form the second patterning layer 122.
In this embodiment, the second pattern material layer is formed by a coating (coating) process.
In this embodiment, the material of the second pattern material layer is a positive photoresist.
In this embodiment, in the step of performing the exposure and development process on the second pattern material layer, a negative development process is used for performing the development process, that is, after the second mask 20 is used for exposing the second pattern material layer, the used developing solution can remove the portion of the second pattern material layer that is not irradiated by the light, so that the second pattern layer 122 is a protrusion corresponding to the compensation pattern 21.
In other embodiments, when the main pattern and the compensation pattern are light-shielding patterns and the inverted auxiliary pattern is a light-transmitting pattern, the second pattern material layer is correspondingly subjected to a positive development process to form an island-shaped structure.
In this embodiment, before forming the second pattern layer 122, the method for forming the semiconductor structure further includes: a second anti-reflective coating 121 is formed on the first hard mask layer 130, and the second anti-reflective coating 121 covers the first hard mask layer 130.
The second anti-reflection coating 121 is used for reducing reflection effect during exposure, so as to improve the transfer precision of the pattern, and the second anti-reflection coating 121 is also used for providing a flat surface for forming the second pattern layer 122, so as to improve the topography quality and the size precision of the second pattern layer 122. In this embodiment, the second anti-reflective coating layer 121 is made of Si-ARC (Silicon anti-reflective-coating). In other embodiments, the material of the second anti-reflective coating layer can also be a BARC material or a DARC material, etc.
Referring to fig. 13 and 14 in combination, fig. 14 is a partial top view corresponding to fig. 13, and the hard mask material layer is patterned by using the second pattern layer 122 as a mask.
In this embodiment, with the second pattern layer 122 as a mask, the step of patterning the hard mask material layer includes: and patterning the bottom hard mask material layer 110 by using the second patterning layer 122 and the first hard mask layer 112 as masks to form a second hard mask layer 140.
In this embodiment, a dry etching process is adopted, for example: an anisotropic dry etch process patterns the bottom hard mask material layer 110. The dry etching process has better etching profile controllability and high etching precision, and is favorable for improving the precision of pattern transfer.
In this embodiment, in the step of patterning the hard mask material layer by using the second pattern layer 122 as a mask, the second pattern layer 122 and the second anti-reflective coating layer 121 are gradually consumed, so that after the second hard mask layer 140 is formed, the second pattern layer 122 and the second anti-reflective coating layer 121 are removed.
In other embodiments, after patterning the hard mask material layer by using the second pattern layer as a mask, the second pattern layer and the second anti-reflection coating layer may also remain a part of the thickness. Correspondingly, the forming method of the semiconductor structure further comprises the following steps: and removing the second pattern layer and the second antireflection coating. Specifically, the second pattern layer and the second anti-reflective coating layer may be removed using one or both of an ashing process and a wet stripping process.
With continued reference to fig. 13 and 14, after patterning the hard mask material layer with the first patterning layer 112 as a mask and patterning the hard mask material layer with the second patterning layer 122 as a mask, the remaining hard mask material layer serves as a hard mask layer.
In this embodiment, the first mask 10 and the second mask 20 in the foregoing embodiments are respectively adopted to perform patterning processing on the hard mask material layer twice, so that a pattern formed in the hard mask material layer meets design requirements.
Moreover, the top hard mask material layer 120 and the bottom hard mask material layer 110 are patterned respectively, which is beneficial to reducing the difficulty of patterning the hard mask material layer, increasing the process window of the patterned hard mask material layer and improving the precision of pattern transmission.
In this embodiment, the second hard mask layer 140 is used as a hard mask layer.
The hard mask layer is used as a mask for subsequent patterning of the substrate 100.
It should be noted that, in this embodiment, the first pattern layer 112 is formed by first using the first mask 10 in the foregoing embodiment, and then the second pattern layer 122 is formed by using the second mask 20 in the foregoing embodiment as an embodiment.
In other embodiments, according to an actual process, the second pattern layer may be formed by first using the second mask in the foregoing embodiments, and then the first pattern layer may be formed by using the first mask in the foregoing embodiments.
Referring to fig. 15, the substrate 100 is patterned using the hard mask layer as a mask to form a target pattern.
In this embodiment, the target pattern is an Island structure (Island).
As can be seen from the foregoing steps, the pattern transfer precision of the patterning process of this embodiment is high, the process window of the photolithography process is large, and the probability of contact (bridge) between adjacent target patterns is small, thereby improving the pattern quality of the target patterns.
In this embodiment, the target pattern may be a gate, a dielectric spacer, or the like. The grooves or the through holes between the medium interlayers can provide space positions for forming functional structures such as interconnection lines, conductive plugs and the like.
Fig. 16 to 21 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure of the present invention.
The same parts of this embodiment as those of the previous embodiments are not described herein again. The present embodiment differs from the previous embodiments in that: the sequence of forming the first pattern layer is different from the sequence of forming the second pattern layer, and accordingly, the step of patterning the hard mask material layer is also different from the foregoing embodiment.
Referring to fig. 16, a second patterning layer 212 is formed on the hard mask material layer using the second reticle 20 of the previous embodiment.
In this embodiment, the second pattern layer 212 is formed on the top hard mask material layer 230.
For a detailed description of forming the second graphic layer 212, reference may be made to the related description of the foregoing embodiments, and the description of the present embodiment is not repeated herein.
Referring to fig. 17 and 18, fig. 18 is a partial top view corresponding to fig. 17, and the hard mask material layer is patterned by using the second pattern layer 212 as a mask.
In this embodiment, the step of patterning the hard mask material layer by using the second pattern layer 212 as a mask includes: the top hard mask material layer 220 is patterned using the second pattern layer 212 as a mask to form a first hard mask layer 230.
Referring to fig. 19, a first pattern layer 222 is formed on the hard mask material layer using the first reticle 10 in the previous embodiment.
In this embodiment, after the top hard mask material layer 220 is patterned by using the second pattern layer 212 as a mask, the first pattern layer 222 is formed on the bottom hard mask material layer 210, an initial pattern is formed in the first pattern layer 222, and a projection of the initial pattern on the substrate 100 is located in the first hard mask layer 230.
In this embodiment, the initial pattern is a pattern opening 235. The pattern opening 235 corresponds to the inverted auxiliary pattern.
Referring to fig. 20 and 21, fig. 21 is a partial top view corresponding to fig. 20, and the hard mask material layer is patterned by using the first pattern layer 222 as a mask.
In this embodiment, with the first pattern layer 222 as a mask, the step of patterning the hard mask material layer includes: the bottom hard mask material layer 210 is patterned using the first patterning layer 222 and the first hard mask layer 230 as masks to form a second hard mask layer 240.
With continuing reference to fig. 20 and 21, the hard mask material layer is patterned with the first pattern layer 222 as a mask, and the remaining hard mask material layer is used as a hard mask layer after the hard mask material layer is patterned with the second pattern layer 212 as a mask.
In this embodiment, the second hard mask layer 240 is used as the hard mask layer.
For a detailed description of the method for forming the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (20)

1. A reticle, comprising:
the first mask comprises a main pattern and an inverted auxiliary pattern positioned in the main pattern;
the second mask plate is matched with the first mask plate and comprises a compensation graph, the light transmission characteristic of the compensation graph is opposite to that of the reversed-phase auxiliary graph, and the projection of the compensation graph on the first mask plate covers the reversed-phase auxiliary graph and is located in the main graph.
2. The mask of claim 1, wherein the inverted auxiliary pattern has a strip shape, and a distance from a long side of the inverted auxiliary pattern to a corresponding edge of the same side of the main pattern is greater than or equal to 15 nm.
3. The mask of claim 1, wherein the inverted auxiliary pattern has a strip shape, the length of the inverted auxiliary pattern is greater than or equal to 40nm, and the distance from the short side of the inverted auxiliary pattern to the corresponding edge of the same side of the main pattern is greater than or equal to 15 nm.
4. The mask of claim 1, wherein a projection of a long side of the compensation pattern on the first mask to a long side of the same side of the inverted auxiliary pattern is from 2nm to 5 nm.
5. The reticle of claim 1, wherein the inverse assist feature is a developable feature.
6. The reticle of claim 1, wherein the inverted assist feature has a width of greater than or equal to 15 nm.
7. The mask of claim 1, wherein the main pattern is a light-shielding pattern, the reverse auxiliary pattern is a light-transmitting pattern, and the compensation pattern is a light-shielding pattern.
8. The mask of claim 1, wherein the main pattern is a light-transmissive pattern, the reverse auxiliary pattern is a light-blocking pattern, and the compensation pattern is a light-transmissive pattern.
9. A method of forming a semiconductor structure, comprising:
providing a substrate;
forming a hard mask material layer on the substrate;
forming a first pattern layer on the hard mask material layer using a first one of the reticles of any one of claims 1 to 8;
patterning the hard mask material layer by taking the first pattern layer as a mask;
forming a second patterned layer on the hard mask material layer using a second one of the reticles of any one of claims 1 to 8;
patterning the hard mask material layer by taking the second pattern layer as a mask;
patterning the hard mask material layer by taking the first graphic layer as a mask, and patterning the hard mask material layer by taking the second graphic layer as a mask, wherein the remaining hard mask material layer is taken as a hard mask layer;
and patterning the substrate by taking the hard mask layer as a mask to form a target pattern.
10. The method of forming a semiconductor structure of claim 9, wherein forming the layer of hard mask material comprises: forming a bottom hard mask material layer on the substrate;
a top hard mask material layer is formed on the bottom hard mask material layer.
11. The method of claim 10, wherein patterning the hard mask material layer using the first pattern layer as a mask comprises: patterning the top hard mask material layer by taking the first pattern layer as a mask to form a first hard mask layer, wherein an initial pattern corresponding to the reverse auxiliary pattern is formed in the first hard mask layer;
after the first graph layer is used as a mask and the top hard mask material layer is patterned, forming a second graph layer on the bottom hard mask material layer, wherein the second graph layer covers the initial graph;
and with the second graphic layer as a mask, the step of patterning the hard mask material layer comprises: and patterning the bottom hard mask material layer by taking the second patterning layer and the first hard mask layer as masks to form a second hard mask layer, wherein the second hard mask layer is used as the hard mask layer.
12. The method of claim 10, wherein patterning the hard mask material layer using the second pattern layer as a mask comprises: patterning the top hard mask material layer by taking the second patterning layer as a mask to form a first hard mask layer;
after the second graph layer is used as a mask and the top hard mask material layer is patterned, forming a first graph layer on the bottom hard mask material layer, wherein an initial graph is formed in the first graph layer, and the projection of the initial graph on a substrate is positioned in the first hard mask layer;
with the first patterning layer as a mask, the step of patterning the hard mask material layer includes: and patterning the bottom hard mask material layer by taking the first pattern layer and the first hard mask layer as masks to form a second hard mask layer, wherein the second hard mask layer is used as the hard mask layer.
13. The method of forming a semiconductor structure of claim 9, wherein the step of forming the first pattern layer comprises: forming a first pattern material layer on the hard mask material layer;
the first pattern material layer is exposed and developed by using a first mask plate of the mask plates according to any one of claims 1 to 8 to form the first pattern layer.
14. The method for forming a semiconductor structure according to claim 13, wherein the main pattern is a light-transmitting pattern, and the step of performing exposure development processing on the first pattern material layer is performed by performing development processing using a negative development process;
or, the main pattern is a shading pattern, and in the step of carrying out exposure and development processing on the first pattern material layer, development processing is carried out by adopting a forward development process.
15. The method of forming a semiconductor structure of claim 9, wherein the step of forming the second pattern layer comprises: forming a second pattern material layer on the hard mask material layer;
the second pattern material layer is exposed and developed by using a second mask plate of the mask plates according to any one of claims 1 to 8 to form the second pattern layer.
16. The method for forming a semiconductor structure according to claim 15, wherein the main pattern is a light-transmitting pattern, and the step of performing exposure development processing on the second pattern material layer comprises performing development processing by a negative development process;
or, the main pattern is a shading pattern, and in the step of carrying out exposure and development processing on the first pattern material layer, development processing is carried out by adopting a forward development process.
17. The method for forming a semiconductor structure according to claim 9, 14 or 16, wherein the target pattern is an island-like structure.
18. The method for forming a semiconductor structure according to claim 11 or 12, wherein the target pattern is an island-like structure; the initial pattern is a trench.
19. The method of forming a semiconductor structure of claim 9, wherein a material of the first pattern layer comprises a photoresist.
20. The method of forming a semiconductor structure of claim 9, wherein a material of the second pattern layer comprises a photoresist.
CN201911259659.8A 2019-12-10 2019-12-10 Mask and method for forming semiconductor structure Pending CN112946995A (en)

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Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0822114A (en) * 1994-07-04 1996-01-23 Lg Semicon Co Ltd Preparation of phase inversion mask
US20020150824A1 (en) * 2001-04-11 2002-10-17 Chul-Hong Park Mask for adjusting transmittance of a light and method for manufacturing the same
US20050175907A1 (en) * 2004-02-11 2005-08-11 Ji-Soong Park Photo mask including scattering bars and method of manufacturing the same
CN101571670A (en) * 2009-04-21 2009-11-04 上海宏力半导体制造有限公司 Mask plate for enlarging focal depth parameter process window, reverse mask plate and exposing method thereof
CN102129166A (en) * 2010-01-12 2011-07-20 中芯国际集成电路制造(上海)有限公司 Method for setting sub-resolution assistance feature and method for producing photoetching mask plate
CN103050383A (en) * 2012-12-24 2013-04-17 上海集成电路研发中心有限公司 Method for eliminating side lobe pattern
CN103984200A (en) * 2014-05-20 2014-08-13 上海华力微电子有限公司 Design method of auxiliary graph as well as production method and photoetching method of test map
CN104423172A (en) * 2013-08-27 2015-03-18 中芯国际集成电路制造(北京)有限公司 Detection method for scattering bar simulation printing
CN105655289A (en) * 2016-01-04 2016-06-08 京东方科技集团股份有限公司 Array substrate, manufacturing method thereof and display device
CN106610563A (en) * 2015-10-22 2017-05-03 中芯国际集成电路制造(上海)有限公司 Mask and double graphical method
CN107168010A (en) * 2016-03-08 2017-09-15 中芯国际集成电路制造(上海)有限公司 The manufacture method of lithography mask version
CN107799402A (en) * 2017-10-24 2018-03-13 德淮半导体有限公司 The forming method of secondary figure
CN110119062A (en) * 2018-02-06 2019-08-13 中芯国际集成电路制造(上海)有限公司 Optical adjacent correction method, photomask manufacturing method and patterning process
CN110221515A (en) * 2018-03-02 2019-09-10 中芯国际集成电路制造(上海)有限公司 The production method of optical adjacent correction method and mask plate

Patent Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0822114A (en) * 1994-07-04 1996-01-23 Lg Semicon Co Ltd Preparation of phase inversion mask
US20020150824A1 (en) * 2001-04-11 2002-10-17 Chul-Hong Park Mask for adjusting transmittance of a light and method for manufacturing the same
US20050175907A1 (en) * 2004-02-11 2005-08-11 Ji-Soong Park Photo mask including scattering bars and method of manufacturing the same
CN101571670A (en) * 2009-04-21 2009-11-04 上海宏力半导体制造有限公司 Mask plate for enlarging focal depth parameter process window, reverse mask plate and exposing method thereof
CN102129166A (en) * 2010-01-12 2011-07-20 中芯国际集成电路制造(上海)有限公司 Method for setting sub-resolution assistance feature and method for producing photoetching mask plate
CN103050383A (en) * 2012-12-24 2013-04-17 上海集成电路研发中心有限公司 Method for eliminating side lobe pattern
CN104423172A (en) * 2013-08-27 2015-03-18 中芯国际集成电路制造(北京)有限公司 Detection method for scattering bar simulation printing
CN103984200A (en) * 2014-05-20 2014-08-13 上海华力微电子有限公司 Design method of auxiliary graph as well as production method and photoetching method of test map
CN106610563A (en) * 2015-10-22 2017-05-03 中芯国际集成电路制造(上海)有限公司 Mask and double graphical method
CN105655289A (en) * 2016-01-04 2016-06-08 京东方科技集团股份有限公司 Array substrate, manufacturing method thereof and display device
CN107168010A (en) * 2016-03-08 2017-09-15 中芯国际集成电路制造(上海)有限公司 The manufacture method of lithography mask version
CN107799402A (en) * 2017-10-24 2018-03-13 德淮半导体有限公司 The forming method of secondary figure
CN110119062A (en) * 2018-02-06 2019-08-13 中芯国际集成电路制造(上海)有限公司 Optical adjacent correction method, photomask manufacturing method and patterning process
CN110221515A (en) * 2018-03-02 2019-09-10 中芯国际集成电路制造(上海)有限公司 The production method of optical adjacent correction method and mask plate

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