CN112930481A - Three-phase three-wire system current sampling circuit and method - Google Patents
Three-phase three-wire system current sampling circuit and method Download PDFInfo
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- CN112930481A CN112930481A CN202080005858.0A CN202080005858A CN112930481A CN 112930481 A CN112930481 A CN 112930481A CN 202080005858 A CN202080005858 A CN 202080005858A CN 112930481 A CN112930481 A CN 112930481A
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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- G01R19/25—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
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Abstract
The application discloses a three-phase three-wire system current sampling circuit and a method, wherein the three-phase three-wire system circuit comprises a first sampling resistor, a first current sampling circuit, a second sampling resistor, a second current sampling circuit, a third current sampling circuit and a processing chip, the first sampling resistor is connected in series in a first electric wire, and the input end of the first current sampling circuit is connected with the first sampling resistor; the second sampling resistor is connected in series in a second electric wire, and the input end of the second current sampling circuit is connected with the second sampling resistor; the third current sampling circuit comprises an arithmetic circuit, and the input end of the arithmetic circuit is respectively connected with the first current sampling circuit and the second current sampling circuit; the output ends of the first current sampling circuit, the second current sampling circuit and the third current sampling circuit are connected with the processing chip, and based on the three-phase three-wire system current sampling circuit, the application also provides a three-phase three-wire system current sampling method. By implementing the method and the device, the response time of current sampling is short and the production cost is low.
Description
Technical Field
The application relates to the technical field of electronics, in particular to a three-phase three-wire system current sampling circuit and a method.
Background
With the development of the switching power supply and the motor control technology, the three-phase three-wire current sampling is indispensable in the switching power supply and the three-phase motor control, and the three-phase three-wire current affects the power factor of the power supply and the control parameters of the motor. How to collect the current of the three-phase three-wire system so as to realize the correction of the power factor of the power supply and the configuration of the control parameter of the motor is a problem which is always researched.
At present, two typical three-phase three-wire system current sampling methods are used in the market, wherein one method is Hall current sensor current sampling; the other is current transformer current sampling. The Hall current sensor is a magnetoelectric conversion device made of semiconductor materials, the production process is complex, and the generation cost is high; the current transformer can only measure sine wave alternating current, and when the waveform of the sine wave is distorted or the frequency of the sine wave is changed, the response time of the current transformer is longer.
Disclosure of Invention
Based on the problems, the application provides a three-phase three-wire system current sampling circuit and a method, two resistors are connected in series in any two-phase electric wire, the electric wire current of any two phases is sampled, and the operation circuit is used for obtaining the current of the remaining one phase, so that the current sampling of the three-phase three-wire system is realized, the response time of the current sampling is short, and the production cost is low.
The application provides a three-phase three-wire system current sampling circuit, three-phase three-wire system current sampling circuit includes first sampling resistor, first current sampling circuit, second sampling resistor, second current sampling circuit, third current sampling circuit and processing chip, and the three-wire includes first electric wire, second electric wire and third electric wire, wherein:
the first sampling resistor is connected in series in the first electric wire, the first current sampling circuit comprises a first rectifying circuit, the input end of the first rectifying circuit is connected with the first sampling resistor, and the output end of the first rectifying circuit is connected with the processing chip;
the second sampling resistor is connected in series in the second electric wire, the second current sampling circuit comprises a second rectifying circuit, the input end of the second rectifying circuit is connected with the second sampling resistor, the output end of the second rectifying circuit is connected with the processing chip, and the resistance value of the first sampling resistor is the same as that of the second sampling resistor;
the third current sampling circuit comprises an operational circuit and a third rectifying circuit, wherein the input end of the operational circuit is connected with the input end of the first rectifying circuit and the input end of the second rectifying circuit respectively, the output end of the operational circuit is connected with the input end of the third rectifying circuit, and the output end of the third rectifying circuit is connected with the processing chip.
In one possible embodiment, the first current sampling circuit further comprises a first isolation amplifying circuit; and the input end of the first isolation amplifying circuit is connected with two ends of the first sampling resistor.
Optionally, the first current sampling circuit further includes a first differential amplifying circuit;
the input end of the first differential amplification circuit is connected with the output end of the first isolation amplification circuit, and the output end of the first differential amplification circuit is connected with the input end of the first rectification circuit.
In one possible embodiment, the first current sampling circuit further comprises a first follower circuit;
the input end of the first following circuit is connected with the output end of the first rectifying circuit, and the output end of the first following circuit is connected with the first port of the processing chip.
In one possible embodiment, the second current sampling circuit further comprises a second isolation amplifying circuit;
and the input end of the second isolation amplifying circuit is connected with two ends of the second sampling resistor.
Optionally, the second current sampling circuit further includes a second differential amplifier circuit;
the input end of the second differential amplification circuit is connected with the output end of the second isolation amplification circuit, and the output end of the second differential amplification circuit is connected with the input end of the second rectification circuit.
In one possible embodiment, the second current sampling circuit further comprises a second follower circuit;
the input end of the second following circuit is connected with the output end of the second rectifying circuit, and the output end of the second following circuit is connected with the second port of the processing chip.
In a possible implementation manner, the input end of the first rectifying circuit and the input end of the second rectifying circuit are connected with the non-inverting input end of the operational circuit, and the direction of the voltage output by the operational circuit is opposite to the current direction of the third wire;
or the input end of the first rectifying circuit and the input end of the second rectifying circuit are connected with the inverting input end of the operational circuit, and the direction of the voltage output by the operational circuit is the same as the current direction of the third wire.
In one possible embodiment, the third current sampling circuit further comprises a third follower circuit;
the input end of the third following circuit is connected with the output end of the third rectifying circuit, and the output end of the third following circuit is connected with the third port of the processing chip.
The application also provides a three-phase three-wire system current sampling method, which is based on the three-phase three-wire system current sampling circuit, and the method comprises the following steps:
the first current sampling circuit obtains voltages at two ends of a first sampling resistor to obtain a first sampling voltage, the first rectifying circuit converts the first sampling voltage into a first direct current pulsating voltage and transmits the first direct current pulsating voltage to the processing chip;
the second current sampling circuit acquires voltages at two ends of a second sampling resistor to obtain a second sampling voltage, and the second rectifying circuit converts the second sampling voltage into a second direct current pulsating voltage and transmits the second direct current pulsating voltage to the processing chip;
the operation circuit adds the first sampling voltage and the second sampling voltage to obtain a third sampling voltage, and a third rectifying circuit converts the third sampling voltage into a third direct current pulsating voltage and transmits the third direct current pulsating voltage to the processing chip;
the processing chip obtains the first direct current ripple voltage, the second direct current ripple voltage and the third direct current ripple voltage, determines the current of the first wire according to the first direct current ripple voltage and the first sampling resistor, determines the current of the second wire according to the second direct current ripple voltage and the second sampling resistor, and determines the current of the third wire according to the third direct current ripple voltage and the resistance value of the first sampling resistor.
The method comprises the steps that any two phases of three-phase three-wire are subjected to current sampling by using two sampling resistors to obtain a first sampling voltage and a second sampling voltage, and an operation circuit in a third current sampling circuit obtains the first sampling voltage and the second sampling voltage and adds the first sampling voltage and the second sampling voltage to obtain a third sampling voltage; the first rectifying circuit converts the first sampling voltage into a first direct current pulsating voltage, the second rectifying circuit converts the second sampling voltage into a second direct current pulsating voltage, the third rectifying circuit converts the third sampling voltage into a third direct current pulsating voltage, the processing chip collects the first direct current pulsating voltage, the second direct current pulsating voltage and the third direct current pulsating voltage in real time, obtains the current of a first wire according to the first direct current pulsating voltage and a first sampling resistance value, obtains the current of a second wire according to the second direct current pulsating voltage and a second sampling resistance value, and obtains the current of a third wire according to the third direct current pulsating voltage and the resistance value of the first sampling resistance. By implementing the embodiment of the application, the two resistors are connected in series in any two-phase electric wire, the current of any two-phase electric wire is sampled, and the residual current of one phase is obtained by using the operation circuit, so that the current of the three-phase three-wire system is sampled, the response time of current sampling is short, and the production cost is low.
Drawings
Fig. 1 is a circuit block diagram of a three-phase three-wire current sampling circuit according to an embodiment of the present application;
fig. 2 is a circuit block diagram of another three-phase three-wire current sampling circuit provided in an embodiment of the present application;
fig. 3 is a schematic circuit diagram of another three-phase three-wire current sampling circuit according to an embodiment of the present application;
fig. 4 is a waveform schematic diagram of a three-phase three-wire current sampling circuit according to an embodiment of the present application;
fig. 5 is a schematic flowchart of a three-phase three-wire system current sampling method according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The following describes embodiments of the present application in further detail with reference to the accompanying drawings.
Referring to fig. 1, fig. 1 is a circuit block diagram of a three-phase three-wire current sampling circuit according to an embodiment of the present application. As shown in fig. 1, the three-phase three-wire system current sampling circuit includes a first sampling resistor 100, a first current sampling circuit 101, a second sampling resistor 110, a second current sampling circuit 111, a third current sampling circuit 121, and a processing chip 130, and the three wires include a first wire, a second wire, and a third wire, where:
the first sampling resistor 100 is connected in series in the first electric wire, the first current sampling circuit 101 includes a first rectifying circuit 1010, an input end of the first rectifying circuit 1010 is connected to the first sampling resistor 100, and an output end of the first rectifying circuit 1010 is connected to the processing chip 130. Specifically, since the current of the first wire flows through the first sampling resistor 100, a voltage drop is formed across the resistor, and the first current sampling circuit 101 obtains the voltage across the first sampling resistor 100 to obtain a first sampling voltage. The first sampled voltage reflects a current of the first wire, and in a possible embodiment, the three-phase three-wire is a power supply mode of a commercial power, and the first wire, the second wire and the third wire are ac voltages, and then the first sampled voltage is also an ac voltage. The first rectifying circuit 1010 converts the first sampled voltage into a first dc pulsating voltage and transmits the first dc pulsating voltage to the processing chip 130. Since the voltage recognized by the processing chip 130 is a positive voltage, and the first sampling voltage obtained by the first current sampling circuit 101 is an ac voltage, and the ac voltage includes a negative voltage, the first rectifying circuit 1010 converts the negative voltage in the first sampling voltage into a positive voltage, that is, the first sampling voltage is converted into the first dc pulsating voltage to be recognized by the processing chip 130. It is understood that the first dc pulsating voltage may be referred to as a dc voltage, and the voltage value of the first dc pulsating voltage is a positive voltage.
The second sampling resistor 110 is connected in series in the second electric wire, the second current sampling circuit 111 includes a second rectifying circuit 1110, an input end of the second rectifying circuit 1110 is connected to the second sampling resistor 110, an output end of the second rectifying circuit 1110 is connected to the processing chip 130, wherein a resistance value of the first sampling resistor 100 is the same as a resistance value of the second sampling resistor 110. Specifically, since the current of the second wire flows through the second sampling resistor 110, a voltage drop is formed across the resistor, and the second current sampling circuit 111 obtains the voltage across the second sampling resistor 110 to obtain a second sampling voltage. The second sampled voltage reflects a current of the second wire. In one possible embodiment, the second sampled voltage is an alternating voltage. The second rectifying circuit 1110 converts the second sampled voltage into a second dc pulsating voltage and transmits the second dc pulsating voltage to the processing chip 130. Since the voltage recognized by the processing chip 130 is a positive voltage, and the second sampled voltage obtained by the second current sampling circuit 111 is an ac voltage including a negative voltage, the second rectifying circuit 1110 converts the negative voltage in the second sampled voltage into a positive voltage, that is, the second sampled voltage is converted into the second dc pulsating voltage to be recognized by the processing chip 130. It is understood that the second dc pulsating voltage may be referred to as a dc voltage, and the second dc pulsating voltage is a positive voltage.
The third current sampling circuit 121 includes an operation circuit 1210 and a third rectification circuit 1211, an input end of the operation circuit 1210 is connected to an input end of the first rectification circuit 1010 and an input end of the second rectification circuit 1110, an output end of the operation circuit 1210 is connected to an input end of the third rectification circuit 1211, and an output end of the third rectification circuit 1211 is connected to the processing chip 130. Specifically, the operation circuit 1210 adds the first sampling voltage and the second sampling voltage to obtain a third sampling voltage. According to kirchhoff's current law, in the three-phase three-wire system circuit, the sum of the currents of the first electric wire, the second electric wire, and the third electric wire is zero. Illustratively, the first wire has a current of IaThe current of the second wire is IbThe current of the second wire is IcFrom kirchhoff's law of current, I can be knowna+Ib+IcWhen the value is 0, (I)a+Ib+Ic) X R is 0, R is the resistance of the first sampling resistor 100 and the second sampling resistor 110, and IaXr is a voltage drop formed by the current of the first wire flowing through the first sampling resistor 100, that is, the first sampling voltage; in a similar manner, the said IbXr is the voltage drop formed by the current of the second wire flowing through the second sampling resistor 110, i.e. the second wireThe voltage is sampled. The third current sampling circuit 121 includes a third rectifying circuit 1211, the third rectifying circuit 1211 converts the third sampled voltage into a third dc pulsating voltage, the third current sampling circuit 121 is connected to the processing chip 130, and the third current sampling circuit 121 transmits the third dc pulsating voltage to the processing chip 130. Since the third sampling voltage is obtained by adding the first sampling voltage and the second sampling voltage by the operation circuit 1210, that is, the first sampling voltage and the second sampling voltage are ac voltages, the third sampling voltage is also an ac voltage. The voltage recognized by the processing chip 130 is a positive voltage, and the third sampled voltage obtained by the operation circuit 1210 is an ac voltage including a negative voltage, and the third rectification circuit 1211 converts the third sampled voltage into the third dc pulsating voltage to be recognized by the processing chip 130. It is understood that the third dc pulsating voltage may be referred to as a dc voltage, and the third dc pulsating voltage is a positive voltage.
In one possible implementation, the input terminal of the first rectifying circuit 1010 and the input terminal 1110 of the second rectifying circuit 1110 are connected to a non-inverting input terminal of the arithmetic circuit 1210, and the direction of the voltage output by the arithmetic circuit 1210 is opposite to the current direction of the third wire. Specifically, the operational circuit 1210 may be an in-phase addition operational amplifier, the first rectifying circuit 1010 transmits the first sampling voltage to an in-phase input terminal of the addition operational amplifier, the second rectifying circuit 1110 transmits the second sampling voltage to the in-phase input terminal of the addition operational amplifier, and an output terminal of the addition operational amplifier is a sum of the first sampling voltage and the second sampling voltage, that is, the third sampling voltage is Ia×R+IbX R according to (I)a+Ib+Ic) X R is 0, then I is shownc×R＝-(Ia×R+IbXr), then the third sampling voltage Ia×R+IbXr and current I of the third wirecIn the opposite direction. Optionally, the processing chip 130 is according to the aboveAnd the direction of the third sampling voltage is opposite to the direction of the current of the third electric wire for further processing, and when a current curve is fitted according to the third direct current pulsating voltage, the phase is inverted, so that the current curve fitted by the processing chip 130 is the current curve of the third electric wire.
In another possible implementation manner, the input terminal of the first rectifying circuit 1010 and the input terminal of the second rectifying circuit 1110 are connected to the inverting input terminal of the arithmetic circuit 1210, and the direction of the voltage output by the arithmetic circuit 1210 is the same as the current direction of the third wire. Specifically, the operational circuit 1210 may be an inverting operational amplifier, the first rectifying circuit 1010 transmits the first sampling voltage to an inverting input terminal of the inverting operational amplifier, and the second rectifying circuit 1110 transmits the second sampling voltage to the inverting input terminal of the inverting operational amplifier, so that an absolute value of an output terminal of the inverting operational amplifier is a sum of the first sampling voltage and the second sampling voltage, that is, the third sampling voltage is- (I)a×R+IbX R) according to (I)a+Ib+Ic) X R is 0, then I is shownc×R＝-(Ia×R+IbXr), then the third sampled voltage- (I)a×R+IbXr) and current I of the third wirecIn the same direction. Optionally, the processing chip 130 fits a current curve according to the third sampling voltage without negating the phase, and the current curve fitted by the processing chip 130 is the current curve of the third wire.
Considering the implementation effect of the circuit, the three-phase three-wire system current sampling circuit may include other circuits besides the circuits included in the embodiment of fig. 1, and the following describes the circuits that the three-phase three-wire system may include in detail. Referring to fig. 2, fig. 2 is a circuit block diagram of another three-phase three-wire sampling circuit provided in an embodiment of the present application. As shown in fig. 2:
in one possible embodiment, the first current sampling circuit 101 further comprises a first isolation amplifying circuit 1011; the input end of the first isolation amplifying circuit 1011 is connected to two ends of the first sampling resistor 100. Specifically, the first isolation amplifying circuit 1011 amplifies the voltage of the first sampling resistor 100 to obtain the first sampling voltage. The first isolation amplifying circuit 1011 further has a function of isolating its own input port from its own output port, and isolates electromagnetic interference on the first electric wire connected to the input end of the first isolation amplifying circuit 1011, so as to prevent the electromagnetic interference from being transmitted to the processing chip 130. Optionally, the first isolation amplifying circuit 1011 may be a fully differential isolation amplifier, model AMC 1200. Optionally, the resistance values of the first sampling resistor 100 and the second sampling resistor 110 are 5 milliohms, the amplitude of the voltage obtained by the first isolation amplifying circuit 1011 across the first sampling resistor 100 is about several hundred millivolts, and the first isolation amplifying circuit 1011 amplifies the voltage across the first sampling resistor 100. Optionally, the fully differential isolation amplifier superimposes a dc component of 2.5V on the voltage across the first sampling resistor 100, as the first sampling voltage.
Further, the first current sampling circuit 101 further includes a first differential amplifying circuit 1012.
The input end of the first differential amplifier circuit 1012 is connected to the output end of the first isolation amplifier circuit 1011, and the output end of the first differential amplifier circuit 1012 is connected to the input end of the first rectifier circuit 1010. Specifically, the first differential amplifier circuit 1012 removes a dc component of the isolated and amplified voltage in the first isolated amplifier circuit 1011, and sets the isolated and amplified voltage from which the dc component is removed as the first sampling voltage. For example, the first differential amplifier circuit 1012 performs a differential operation on the voltage output from the first isolation amplifier circuit 1011, subtracts a dc voltage signal from the differential voltage output from the first isolation amplifier circuit 1011, subtracts a dc component and a remaining ac component, and sets the isolated and amplified voltage from which the dc component is removed as the first sampling voltage. Alternatively, the first differential amplifying circuit 1012 may be a differential operational amplifier.
Optionally, the first current sampling circuit 101 further includes a first follower circuit 1013. The input end of the first follower circuit 1013 is connected to the output end of the first rectifier circuit 1010, and the output end of the first follower circuit 1013 is connected to the first port of the processing chip 130. Specifically, the magnitude of the output voltage of the first follower circuit 1013 is the same as the magnitude of the voltage input to the first follower circuit 1013, that is, the output voltage of the first rectifier circuit 1010 is the same as the output voltage of the first follower circuit 1013. For example, the first follower circuit 1013 may be a voltage follower, and the voltage follower has a characteristic of high input impedance and low output impedance.
In another possible embodiment, the second current sampling circuit 111 further includes a second isolation amplifying circuit 1111; the input end of the second isolation amplifying circuit 1111 is connected to two ends of the second sampling resistor 110. Specifically, the second isolation amplifying circuit 1111 amplifies the voltage of the second sampling resistor 110 to obtain the second sampling voltage. The second isolation amplifying circuit 1111 further has a function of isolating an input/output port of the second isolation amplifying circuit from an output port of the second isolation amplifying circuit, and isolates electromagnetic interference on the second wire connected to an input terminal of the second isolation amplifying circuit 1111, so as to prevent the electromagnetic interference from being transmitted to the processing chip 130. Optionally, the second isolation amplifier 1111 may be a fully differential isolation amplifier, model AMC 1200. In a possible implementation manner, if the resistance values of the first sampling resistor 100 and the second sampling resistor 110 are 5 milliohms, the second isolation amplification circuit 1111 obtains that the amplitude of the voltage across the second sampling resistor 110 is about several hundred millivolts, and the second isolation amplification circuit 1111 amplifies the voltage across the second sampling resistor 110. Optionally, the fully differential isolation amplifier superimposes a dc component of 2.5V on the voltage across the second sampling resistor 110, as the second sampling voltage.
Further, the second current sampling circuit 111 further includes a second differential amplifying circuit 1112. An input end of the second differential amplifying circuit 1112 is connected to an output end of the second isolation amplifying circuit 1111, and an output end of the second differential amplifying circuit 1112 is connected to an input end of the second rectifying circuit 1110. Specifically, the second differential amplifier circuit 1112 removes a dc component of the isolated and amplified voltage in the second isolation amplifier circuit 1111, and sets the isolated and amplified voltage from which the dc component is removed as the second sampling voltage. For example, the second differential amplifier circuit 1112 performs a differential operation on the voltage output from the second isolation amplifier circuit 1111, subtracts a dc voltage signal from the differential voltage output from the second isolation amplifier circuit 1111, subtracts a dc component and a remaining ac component, and sets the isolated and amplified voltage from which the dc component is removed as the second sampling voltage. Alternatively, the second differential amplifying circuit 1112 may be a differential operational amplifier.
Optionally, the second current sampling circuit 111 further includes a second follower circuit 1113. The input end of the second follower circuit 1113 is connected to the output end of the second rectifying circuit 1110, and the output end of the second follower circuit 1113 is connected to the second port of the processing chip 130. Specifically, the output voltage of the second follower circuit 1113 has the same magnitude as the voltage input to the second follower circuit 1113, that is, the output voltage of the second rectifier circuit 1110 is the same as the output voltage of the second follower circuit 1113. Illustratively, the second follower circuit 1113 may be a voltage follower. The voltage follower has the characteristics of high input impedance and low output impedance.
In yet another possible embodiment, the third current sampling circuit 121 further includes a third follower circuit 1212. An input end of the third follower circuit 1212 is connected to an output end of the third rectification circuit 1211, and an output end of the third follower circuit 1212 is connected to a third port of the processing chip 130. Specifically, the output voltage of the third follower circuit 1212 is the same as the voltage input to the third follower circuit 1212, that is, the output voltage of the arithmetic circuit 1210 is the same as the output voltage of the third follower circuit 1212. Illustratively, the third follower circuit 1212 may be a voltage follower having a high input impedance and a low output impedance.
In a possible embodiment, the three-phase three-wire is used to provide the charger 140 with electric energy. Specifically, the three-phase three-wire is from a three-phase three-wire in the commercial power, and the phases of the three-phase three-wire differ by 120 degrees, respectively, so as to provide electric energy for the three-phase of the charger 140.
The operation principle of the three-phase three-wire system current sampling circuit is described with reference to the accompanying drawings, and reference is made to fig. 3 and fig. 4.
Referring first to fig. 3, fig. 3 is a schematic circuit diagram of another three-phase three-wire current sampling circuit according to an embodiment of the present application. As shown in fig. 3, the three-phase three-wire system current sampling circuit includes a first sampling resistor 300, a first current sampling circuit 301, a second sampling resistor 310, a second current sampling circuit 311, a third current sampling circuit 320, and a processing chip 330, and the three wires include a first wire, a second wire, and a third wire, where:
the first sampling resistor 300 comprises a first resistor R1, the first resistor R1 being connected in series in the first wire; the second sampling resistor 310 includes a second resistor R2, the second resistor R2 being connected in series in the second wire. Specifically, the first resistor R1 and the second resistor R2 have the same resistance value, and optionally, the first resistor R1 and the second resistor R2 have a resistance value of 5 milliohms. The first resistor R1 and the second resistor R2 influence the sampling precision of the three-phase three-wire system current, in order to improve the current sampling precision, resistors with high precision, small temperature drift and small parasitic parameters are selected, the first resistor R1 and the second resistor R2 are relatively high in cost, the kirchhoff current law is utilized in the application, two sampling resistors are used for collecting the three-wire current, the Hall current sensor with high production cost is prevented from being used for current sampling, and the production cost of one sampling resistor and one isolation amplifier is further saved.
The first current sampling circuit 301 includes a first rectifying circuit 3011, where the first rectifying circuit 3011 includes a first operational amplifier U1, a second operational amplifier U2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a first diode D1, and a second diode D2, and optionally, the first rectifying circuit 3011 may further include an eighth resistor R8 and a ninth resistor R9.
In one possible embodiment, the first current sampling circuit 301 further includes a first isolation amplifying circuit 3012, and the first isolation amplifying circuit 3012 includes a first fully differential isolation amplifier Q1.
Further, the first current sampling circuit 301 further includes a first differential amplification circuit 3013, and the first differential amplification circuit 3013 includes a third operational amplifier U3, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, and a thirteenth resistor R13.
Further, the first current sampling circuit 301 further includes a first follower circuit 3014, the first follower circuit 3014 includes a fourth operational amplifier U4, wherein:
the first sampling resistor 300 is connected to the first isolation amplifying circuit 3012, specifically, the first fully differential isolation amplifier Q1 includes 8 ports, the first port and the eighth port are power ports, the fourth port and the fifth port are ground ports, the second port and the third port are differential input ports, the sixth port and the seventh port are differential output ports, and two ends of the first resistor R1 are connected to the second port and the third port of the first fully differential isolation amplifier Q1.
For better understanding of the functional implementation of each circuit, reference may be made to fig. 4, where fig. 4 is a waveform schematic diagram of a three-phase three-wire current sampling circuit provided in an embodiment of the present application. It is understood that the waveform diagrams in fig. 4 are schematic waveforms implemented by the functions of the respective circuits, and do not represent the relationship between the amplitude and the phase of the voltage output by the respective circuits.
As shown in fig. 4, the waveform diagram of the input end of the first fully differential isolation amplifier is shown as the sampling voltage 4a in fig. 4, and the sampling voltage 4a is a voltage waveform diagram of the two ends of the first resistor R1, which reflects the current of the first wire. The output waveform through the first fully differential isolation amplifier Q1 is shown as a sampling voltage 4b in fig. 4, the first fully differential amplifier Q1 performs isolation amplification on the voltage across the first sampling resistor 300 to obtain the first sampling voltage, and the first sampling voltage is superimposed with a dc component through the first isolation amplifying circuit 3012, for example, the amplitude of the dc component is 2.5V.
The first isolation amplifying circuit 3012 is connected to the first differential amplifying circuit 3013, and specifically, the first isolation amplifying circuit 3012 comprises a first fully differential isolation amplifier Q1, a sixth port of the first fully differential isolation amplifier Q1 is connected with one end of the tenth resistor R10, a seventh port of the first fully differential isolation amplifier Q1 is connected to one end of the eleventh resistor R11, the other end of the eleventh resistor R11 is connected to one end of the twelfth resistor R12 and the non-inverting input terminal of the third operational amplifier U3, the other end of the twelfth resistor R12 is connected to ground, the other end of the tenth resistor R10 is connected to one end of the thirteenth resistor R13 and the inverting input terminal of the third operational amplifier U3, the other end of the thirteenth resistor R13 is connected to the output terminal of the third operational amplifier U3. The waveform of the output of the first differential amplifier circuit 3013 is shown as a sampling voltage 4c in fig. 4, the input end of the first differential amplifier circuit 3013 is connected to the output end of the first isolation amplifier circuit 3012, the first differential amplifier circuit 3013 is configured to remove the dc component of the voltage isolated and amplified in the first isolation amplifier circuit 3012, and use the isolated and amplified voltage with the dc component removed as the first sampling voltage, where the waveform of the first sampling voltage is shown as the sampling voltage 4 c.
The first differential amplifier circuit 3013 is connected to the first rectifier circuit 3011, and specifically, an output terminal of the third operational amplifier U3 in the first differential amplifier circuit 3013 is connected to one terminal of the fifth resistor R5 and one terminal of the third resistor R3, the other end of the third resistor R3 is connected with the inverting input terminal of the first operational amplifier U1, the cathode of the first diode D1 and one end of the fourth resistor R4, the anode of the first diode D1 is connected with the cathode of the second diode D2 and the output terminal of the first operational amplifier U1, an anode of the second diode D2 is connected to the other end of the fourth resistor R4 and one end of the sixth resistor R6, the other end of the sixth resistor R6 is connected to the inverting input terminal of the second operational amplifier U2 and one end of the seventh resistor R7, the other end of the seventh resistor R7 is connected to the output end of the second operational amplifier U2. Optionally, a non-inverting input terminal of the first operational amplifier U1 is connected to one end of the eighth resistor R8, and the other end of the eighth resistor R8 is connected to ground, so that the eighth resistor R8 can stabilize the operating state of the first operational amplifier U1. Similarly, the non-inverting input terminal of the second operational amplifier U2 is connected to one end of a ninth resistor R9, and the other end of the ninth resistor R9 is connected to ground, so as to stabilize the operating state of the second operational amplifier U2. The first rectifying circuit 3011 is configured to convert the first sampling voltage into a first dc pulsating voltage, and the first current sampling circuit 301 is connected to the processing chip 330 and configured to transmit the first dc pulsating voltage to the processing chip 330, and specifically, the first rectifying circuit 3011 converts the first sampling voltage with a waveform shown as a sampling voltage 4c into the first dc pulsating voltage shown as a dc pulsating voltage 4 d.
The first rectifying circuit 3011 is connected to the first follower circuit 3014, specifically, an output end of the second operational amplifier U2 is connected to a non-inverting input end of the fourth operational amplifier U4, an inverting input end of the fourth operational amplifier U4 is connected to an output end of the fourth operational amplifier U4, and an output end of the fourth operational amplifier U4 is connected to the first port of the processing chip 330. The first follower circuit 3014 transmits a first dc pulse voltage as shown in 4d to the processing chip 330. The processing chip 330 obtains the first dc ripple voltage, and determines the current of the first wire according to the first dc ripple voltage and the resistance value of the first resistor R1.
In one possible implementation, the first operational amplifier U1, the second operational amplifier U2, the third operational amplifier U3, and the fourth operational amplifier U4 may be integrated on a single operational amplifier integrated chip.
The first current sampling circuit 301 may further include a fourteenth resistor R14 and a first capacitor C1, one end of the fourteenth resistor R14 is connected to the output end of the fourth operational amplifier U4 in the first follower circuit 3014, the other end of the fourteenth resistor R14 is connected to one end of the first capacitor C1 and the first port of the processing chip 330, and the other end of the first capacitor C1 is connected to ground. The fourteenth resistor R14 and the first capacitor C1 form an RC low-pass filter circuit to prevent high-frequency signals from interfering with the processing chip 330.
The second current sampling circuit 311 includes a second rectifying circuit 3111, the second rectifying circuit 3111 includes a fifth operational amplifier U5, a sixth operational amplifier U6, a fifteenth resistor R15, a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, a nineteenth resistor R19, a third diode D3, and a fourth diode D4, and optionally, the second rectifying circuit 3111 may further include a twentieth resistor R20 and a twenty-first resistor R21.
In one possible embodiment, the second current sampling circuit 311 further includes a second isolation amplifying circuit 3112, and the second isolation amplifying circuit 3112 includes a second fully differential isolation amplifier Q2.
Further, the second current sampling circuit 311 further includes a second differential amplifier circuit 3113, and the second differential amplifier circuit 3113 includes a seventh operational amplifier U7, a twenty-second resistor R22, a twenty-third resistor R23, a twenty-fourth resistor R24, and a twenty-fifth resistor R25.
Further, the second current sampling circuit 311 further includes a second follower circuit 3114, and the second follower circuit 3114 includes an eighth operational amplifier U8, wherein:
the second sampling resistor 310 is connected to the second isolation amplifier circuit 3112, specifically, the second isolation amplifier circuit 3112 includes a second fully differential isolation amplifier Q2, the second fully differential isolation amplifier Q2 includes 8 ports, the first port and the eighth port are power ports, the fourth port and the fifth port are ground ports, the second port and the third port are differential input ports, the sixth port and the seventh port are differential output ports, and two ends of the second resistor R35 2 are connected to the second port and the third port of the second fully differential isolation amplifier Q2.
For better understanding of the functional implementation of each circuit, reference may be made to fig. 4, where fig. 4 is a waveform schematic diagram of a three-phase three-wire current sampling circuit provided in an embodiment of the present application.
As shown in fig. 4, a waveform diagram of an input end of the second fully differential isolation amplifier is shown as a sampling voltage 4a in fig. 4, and the sampling voltage 4a is a voltage waveform diagram of the two ends of the second resistor R2, which reflects the current of the second wire. The output waveform through the second fully differential isolation amplifier Q2 is shown as a sampling voltage 4b, the second fully differential amplifier Q2 performs isolation amplification on the voltage across the second sampling resistor 310 to obtain the second sampling voltage, and the second sampling voltage is superimposed with a dc component through the second isolation amplifier circuit 3112, for example, the amplitude of the dc component is 2.5V.
The second isolation amplifier circuit 3112 is connected to the second differential amplifier circuit 3113, specifically, a sixth port of the second fully differential isolation amplifier Q2 is connected to one end of the twenty-second resistor R22, a seventh port of the second fully differential isolation amplifier Q2 is connected to one end of the twenty-third resistor R23, the other end of the twenty-third resistor R23 is connected to one end of the twenty-fourth resistor R24 and the non-inverting input terminal of the seventh operational amplifier U7, the other end of the twenty-fourth resistor R24 is connected to ground, the other end of the twenty-second resistor R22 is connected to one end of the twenty-fifth resistor R25 and the inverting input terminal of the seventh operational amplifier U7, and the other end of the twenty-fifth resistor R25 is connected to the output terminal of the seventh operational amplifier U7. The waveform of the output of the second differential amplifier circuit 3113 is as shown by a sampling voltage 4c, the input of the second differential amplifier circuit 3113 is connected to the output of the second isolation amplifier circuit 3112, the second differential amplifier circuit 3113 is configured to remove the dc component of the voltage isolated and amplified in the second isolation amplifier circuit 3112, and the isolated and amplified voltage from which the dc component is removed is used as the second sampling voltage, where the waveform of the second sampling voltage is as shown by the sampling voltage 4 c.
The second differential amplifier circuit 3113 is connected to the second rectifier circuit 3111, and more specifically, an output terminal of a seventh operational amplifier U7 in the second differential amplifier circuit 3113 is connected to one terminal of a fifteenth resistor R15 and one terminal of a seventeenth resistor R17, the other terminal of the fifteenth resistor R15 is connected to an inverting input terminal of the fifth operational amplifier U5, a cathode of the third diode D3 and one terminal of the sixteenth resistor R16, an anode of the third diode D3 is connected to a cathode of the fourth diode D4 and an output terminal of the fifth operational amplifier U5, an anode of the fourth diode D4 is connected to the other terminal of the sixteenth resistor R16 and one terminal of the eighteenth resistor R18, and the other terminal of the eighteenth resistor R18 is connected to an inverting input terminal of the sixth operational amplifier U6 and one terminal of the nineteenth resistor R19, the other end of the nineteenth resistor R19 is connected to the output terminal of the sixth operational amplifier U6. Optionally, a non-inverting input terminal of the fifth operational amplifier U5 is connected to one end of the twentieth resistor R20, and the other end of the twentieth resistor R20 is connected to ground, so that the twentieth resistor R20 can stabilize the operating state of the fifth operational amplifier U5. Similarly, the non-inverting input terminal of the sixth operational amplifier U6 is connected to one end of a twenty-first resistor R21, and the other end of the twenty-first resistor R21 is connected to ground, so as to stabilize the operating state of the sixth operational amplifier U6. The second rectifier circuit 3111 is configured to convert the second sampling voltage into a second dc pulsating voltage, and the second current sampling circuit 311 is connected to the processing chip 330 and configured to transmit the second dc pulsating voltage to the processing chip 330, specifically, the second rectifier circuit 3111 converts the second sampling voltage with a waveform shown as a sampling voltage 4c into the second dc pulsating voltage shown as a dc pulsating voltage 4 d.
The second rectifier circuit 3111 is connected to the second follower circuit 3114, specifically, an output terminal of the sixth operational amplifier U6 is connected to a non-inverting input terminal of the eighth operational amplifier U8, an inverting input terminal of the eighth operational amplifier U8 is connected to an output terminal of the eighth operational amplifier U8, and an output terminal of the eighth operational amplifier U8 is connected to the second port of the processing chip 330. The second follower circuit 3114 transmits a second dc pulse voltage as indicated by a dc pulsating voltage 4d to the processing chip 330.
Alternatively, the fifth operational amplifier U5, the sixth operational amplifier U6, the seventh operational amplifier U7, and the eighth operational amplifier U8 may be integrated on one chip of an integrated operational amplifier.
The second current sampling circuit 311 may further include a twenty-sixth resistor R26 and a second capacitor C2, wherein one end of the twenty-sixth resistor R26 is connected to the output end of the eighth operational amplifier U8 in the second follower circuit 3114, the other end of the twenty-sixth resistor R26 is connected to one end of the second capacitor C2 and the second port of the processing chip 330, and the other end of the second capacitor C2 is connected to ground. The twenty-sixth resistor R26 and the second capacitor C2 form an RC low-pass filter circuit to prevent high-frequency signals from interfering with the processing chip 330.
The third current sampling circuit 320 includes an operational circuit 3201 and a third rectification circuit 3202, the operational circuit 3201 includes a ninth operational amplifier U9, a twenty-seventh resistor R27, a twenty-eighth resistor R28, a twenty-ninth resistor R29, and a thirtieth resistor R30; the third rectifying circuit 3202 includes a tenth operational amplifier U10, an eleventh operational amplifier U11, a thirty-first resistor R31, a thirty-second resistor R32, a thirty-third resistor R33, a thirty-fourth resistor R34, a thirty-fifth resistor R35, a fifth diode D5, and a sixth diode D6, and optionally, the third rectifying circuit 3202 may further include a thirty-sixth resistor R36 and a thirty-seventh resistor R37.
Optionally, the third current sampling circuit 320 further includes a third follower circuit 3203, the third follower circuit 3203 includes a twelfth operational amplifier U12, wherein:
the third current sampling circuit 320 is respectively connected to the first current sampling circuit 301 and the second current sampling circuit 311, specifically, the first differential amplifier circuit 3013 in the first current sampling circuit 301 is connected to the operational circuit 3201 in the third current sampling voltage 320, so that the output end of the third operational amplifier U3 is connected to one end of the twenty-seventh resistor R27, and the other end of the twenty-seventh resistor R27 is connected to the inverting input end of the ninth operational amplifier U9 and one end of the twenty-ninth resistor R29; the second differential amplifier circuit 3113 in the second current sampling circuit 311 is connected to the operational circuit 3201 in the third current sampling circuit 320, so that the output terminal of the seventh operational amplifier U7 is connected to one end of the twenty-eighth resistor R28, and the other end of the twenty-eighth resistor R28 is connected to the inverting input terminal of the ninth operational amplifier U9 and one end of the twenty-ninth resistor R29. The other end of the twenty-ninth resistor R29 is connected to the output end of the ninth operational amplifier U9, one end of the thirty-fifth resistor R30 is connected to the non-inverting input end of the ninth operational amplifier U9, and the other end of the thirty-fifth resistor R30 is connected to ground. The ninth operational amplifier U9 performs an inverse phase addition on the first sampled voltage and the second sampled voltage to obtain the third sampled voltage, so that the voltage waveform of the third wire output by the output terminal of the ninth operational amplifier U9 is opposite in phase to the waveform diagram in the sampled voltage 4 a.
The operational circuit 3201 is connected to the third rectifying circuit 3202, and specifically, an output terminal of a ninth operational amplifier U9 in the operational circuit 3201 is connected to one terminal of the thirty-first resistor R31 and one terminal of a thirty-third resistor R33, the other terminal of the thirty-first resistor R31 is connected to an inverting input terminal of the tenth operational amplifier U10, a cathode of the fifth diode D5 and one terminal of the thirty-second resistor R32, an anode of the fifth diode D5 is connected to a cathode of the sixth diode D6 and an output terminal of the tenth operational amplifier U10, an anode of the sixth diode D6 is connected to the other terminal of the thirty-second resistor R32 and one terminal of the thirty-fourth resistor R34, and the other terminal of the thirty-fourth resistor R34 is connected to an inverting input terminal of the eleventh operational amplifier U11 and one terminal of the thirty-fifth resistor R35, the other end of the thirty-fifth resistor R35 is connected with the output end of the eleventh operational amplifier U11. Optionally, a non-inverting input terminal of the tenth operational amplifier U10 is connected to one end of the thirty-sixth resistor R36, and the other end of the thirty-sixth resistor R36 is connected to ground, so that the thirty-sixth resistor R36 can stabilize an operating state of the tenth operational amplifier U10. Similarly, the non-inverting input terminal of the eleventh operational amplifier U11 is connected to one end of a thirty-seventh resistor R37, and the other end of the thirty-seventh resistor R37 is connected to ground, so as to stabilize the operating state of the eleventh operational amplifier U11. The third rectifying circuit 3202 is configured to convert the third sampled voltage into a third dc pulsating voltage, and the third current sampling circuit 320 is connected to the processing chip 330 and configured to transmit the third dc pulsating voltage to the processing chip 330, where, for example, a waveform of the third dc pulsating voltage is shown as a dc pulsating voltage 4 d.
The third rectifying circuit 3202 is connected to the third follower circuit 3203, specifically, an output terminal of the eleventh operational amplifier U11 is connected to a non-inverting input terminal of the twelfth operational amplifier U12, an inverting input terminal of the twelfth operational amplifier U12 is connected to an output terminal of the twelfth operational amplifier U12, and an output terminal of the twelfth operational amplifier U12 is connected to the third port of the processing chip 330. The third follower circuit 3203 transmits a third dc pulse voltage, as shown by the dc pulsating voltage 4d, to the processing chip 330.
In one possible implementation, the ninth operational amplifier U9, the tenth operational amplifier U10, the eleventh operational amplifier U11, and the twelfth operational amplifier U12 may be integrated on a single operational amplifier integrated chip.
The third current sampling circuit 320 may further include a thirty-eighth resistor R38 and a third capacitor C3, one end of the thirty-eighth resistor R38 is connected to the output terminal of the twelfth operational amplifier U12 in the third follower circuit 3203, the other end of the thirty-eighth resistor R38 is connected to one end of the third capacitor C3 and the third port of the processing chip 330, and the other end of the third capacitor C3 is connected to ground. The thirty-eighth resistor R38 and the third capacitor C3 form an RC low-pass filter circuit to prevent high-frequency signals from interfering with the processing chip 330.
In this embodiment, the first sampling resistor 300 is connected in series to a first wire, the first isolation amplifying circuit 3012 obtains voltages at two ends of the first sampling resistor 300, performs isolation amplification on the voltages at two ends of the first sampling resistor 300, and transmits the amplified voltages to the first differential operational amplifier circuit 3013 to obtain a first sampling voltage, the first rectifying circuit 3011 converts the first sampling voltage into a first dc pulsating voltage, the processing chip 330 collects the first dc pulsating voltage in real time, and obtains a current of the first wire according to the first dc pulsating voltage and a resistance value of the first sampling resistor 300; similarly, the second sampling resistor 310 is connected in series to a second wire, the second isolation amplifier 3112 circuit obtains a voltage across the second sampling resistor 310, performs isolation amplification on the voltage across the second sampling resistor 310, and transmits the voltage to the second differential operational amplifier 3113 to obtain a second sampling voltage, the second rectifier circuit 3111 converts the second sampling voltage into a second dc pulsating voltage, the processing chip 330 collects the second dc pulsating voltage in real time, and obtains a current of the second wire according to the second dc pulsating voltage and a resistance value of the second sampling resistor 310; an arithmetic circuit 3201 in the third current sampling circuit 320 obtains the first sampling voltage and the second sampling voltage, adds the first sampling voltage and the second sampling voltage to obtain a third sampling voltage, transmits the third sampling voltage to a third rectifying circuit 3202, converts the third sampling voltage into a third dc pulsating voltage by the third rectifying circuit 3202, and transmits the third dc pulsating voltage to the processing chip 330, and the processing chip 330 collects the third dc pulsating voltage in real time and obtains a current of the third wire according to the third dc pulsating voltage and the resistance value of the first sampling resistor 300. In the embodiment, two resistors are connected in series in any two-phase electric wire, the electric wire current of any two phases is sampled, and the remaining electric current of one phase is obtained by using the arithmetic circuit, so that the current sampling of the three-phase three-wire system is realized, the response time is short, and the production cost is low.
Based on the three-phase three-wire system current sampling circuit described above with reference to fig. 1, an embodiment of the present application further provides a three-phase three-wire system current sampling method, referring to fig. 5, fig. 5 is a schematic flow chart of the three-phase three-wire system current sampling method provided by the embodiment of the present application, and as shown in fig. 5, the specific implementation steps are as follows:
s500, the first current sampling circuit obtains voltages at two ends of a first sampling resistor to obtain a first sampling voltage, the first rectifying circuit converts the first sampling voltage into a first direct current pulsating voltage, and the first direct current pulsating voltage is transmitted to a processing chip.
Specifically, the current of the first wire flows through the first sampling resistor, a voltage drop is formed at two ends of the resistor, the first current sampling circuit obtains the voltage at two ends of the first sampling resistor to obtain a first sampling voltage, and the first sampling voltage reflects the current of the first wire. The first sampling voltage is an alternating current voltage. The first rectifying circuit converts the first sampling voltage into a first direct current pulsating voltage and transmits the first direct current pulsating voltage to the processing chip.
S501, the second current sampling circuit obtains voltages at two ends of a second sampling resistor to obtain a second sampling voltage, the second rectifying circuit converts the second sampling voltage into a second direct current pulsating voltage, and the second direct current pulsating voltage is transmitted to the processing chip.
Specifically, the current of the second wire flows through the second sampling resistor, a voltage drop is formed at two ends of the resistor, the second current sampling circuit obtains the voltage at two ends of the second sampling resistor to obtain a second sampling voltage, and the second sampling voltage reflects the current of the second wire. The second sampling voltage is an alternating current voltage. The second rectifying circuit converts the second sampling voltage into a second direct current pulsating voltage and transmits the second direct current pulsating voltage to the processing chip.
S502, the operation circuit adds the first sampling voltage and the second sampling voltage to obtain a third sampling voltage, and the third rectifying circuit converts the third sampling voltage into a third direct current pulsating voltage and transmits the third direct current pulsating voltage to the processing chip.
S503, the processing chip obtains the first direct current pulsating voltage, the second direct current pulsating voltage and the third direct current pulsating voltage, determines the current of the first wire according to the first direct current pulsating voltage and the first sampling resistor, determines the current of the second wire according to the second direct current pulsating voltage and the second sampling resistor, and determines the current of the third wire according to the third direct current pulsating voltage and the resistance value of the first sampling resistor.
Specifically, a digital-to-analog conversion module in the processing chip collects voltage signals output from the first current sampling circuit, the second current sampling circuit and the third current sampling circuit in real time, wherein the voltage signals include the first direct current pulsating voltage, the second direct current pulsating voltage and the third direct current pulsating voltage. An operation module in the processing chip acquires the current of the first sampling resistor according to the first direct current pulsating voltage and the resistance value of the first sampling resistor, the first sampling resistor is connected in series in the first electric wire, and the current of the first sampling resistor is known to be the current of the first electric wire according to the fact that the currents in the series circuits are equal; similarly, the operation module in the processing chip obtains the current of the second sampling resistor according to the second dc pulsating voltage and the resistance value of the second sampling resistor, and the second sampling resistor is connected in series in the second electric wire, and the current of the second sampling resistor is the current of the second electric wire; the digital-to-analog conversion module in the processing chip can acquire the third direct current pulsating voltage in real time,and an operation module in the processing chip acquires the current of the third wire according to the third direct current pulsating voltage and the resistance value of the first sampling resistor. Illustratively, the first dc pulsating voltage collected by the processing chip in real time is UaThe second DC pulsating voltage is UbThe third DC pulsating voltage is UcWherein U isa＝Ia×R，Ub＝Ib×R，Uc＝IcX R, the first wire current Ia＝Ua/R, the second line current Ib＝Ub/R, the third wire current Ic＝Uc/R。
It should be noted that the processing chip includes a plurality of ports, and the ports through which the first dc pulsating voltage, the second dc pulsating voltage, and the third dc pulsating voltage are transmitted to the processing chip are different, so as to ensure the accuracy of collecting the first dc pulsating voltage, the second dc pulsating voltage, and the third dc pulsating voltage. Therefore, the processing chip determines the current of the first wire according to the first direct current pulsating voltage and the first sampling resistor, determines the current of the second wire according to the second direct current pulsating voltage and the second sampling resistor, and determines the current of the third wire according to the third direct current pulsating voltage and the resistance value of the first sampling resistor.
By implementing the embodiment, the resistors can be used for sampling the current of any two phases in the three-phase three-wire system, and then the current of the remaining one phase is obtained according to the current sampling circuit, so that the current of the three-phase three-wire system is sampled, and the production cost is reduced.
It should be noted that the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. It is understood that the corresponding examples of fig. 3 and fig. 4 are only used to explain the embodiments of the present application, and should not be construed as limiting, and in the alternative, fig. 3 and fig. 4 may also have other implementations, for example, the operational amplifier of fig. 3 may be integrated into an operational amplifier integrated chip, the waveform diagram of fig. 4 may be subjected to an inverting input process, and the like, which are not listed here.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like.
The above disclosure is only for the purpose of illustrating the preferred embodiments of the present application and is not to be construed as limiting the scope of the present application, so that the present application is not limited thereto, and all equivalent variations and modifications can be made to the present application.
Claims (10)
1. A three-phase three-wire system current sampling circuit is characterized by comprising a first sampling resistor, a first current sampling circuit, a second sampling resistor, a second current sampling circuit, a third current sampling circuit and a processing chip, wherein the three wires comprise a first electric wire, a second electric wire and a third electric wire, and the three wires comprise:
the first sampling resistor is connected in series in the first electric wire, the first current sampling circuit comprises a first rectifying circuit, the input end of the first rectifying circuit is connected with the first sampling resistor, and the output end of the first rectifying circuit is connected with the processing chip;
the second sampling resistor is connected in series in the second electric wire, the second current sampling circuit comprises a second rectifying circuit, the input end of the second rectifying circuit is connected with the second sampling resistor, the output end of the second rectifying circuit is connected with the processing chip, and the resistance value of the first sampling resistor is the same as that of the second sampling resistor;
the third current sampling circuit comprises an operational circuit and a third rectifying circuit, wherein the input end of the operational circuit is connected with the input end of the first rectifying circuit and the input end of the second rectifying circuit respectively, the output end of the operational circuit is connected with the input end of the third rectifying circuit, and the output end of the third rectifying circuit is connected with the processing chip.
2. The three-phase three-wire current sampling circuit of claim 1, wherein the first current sampling circuit further comprises a first isolation amplification circuit;
and the input end of the first isolation amplifying circuit is connected with two ends of the first sampling resistor.
3. The three-phase three-wire current sampling circuit of claim 2, wherein the first current sampling circuit further comprises a first differential amplification circuit;
the input end of the first differential amplification circuit is connected with the output end of the first isolation amplification circuit, and the output end of the first differential amplification circuit is connected with the input end of the first rectification circuit.
4. The three-phase three-wire current sampling circuit of claim 1, wherein the first current sampling circuit further comprises a first follower circuit;
the input end of the first following circuit is connected with the output end of the first rectifying circuit, and the output end of the first following circuit is connected with the first port of the processing chip.
5. The three-phase three-wire current sampling circuit of claim 1, wherein the second current sampling circuit further comprises a second isolation amplification circuit;
and the input end of the second isolation amplifying circuit is connected with two ends of the second sampling resistor.
6. The three-phase three-wire current sampling circuit of claim 5, wherein the second current sampling circuit further comprises a second differential amplification circuit;
the input end of the second differential amplification circuit is connected with the output end of the second isolation amplification circuit, and the output end of the second differential amplification circuit is connected with the input end of the second rectification circuit.
7. The three-phase three-wire current sampling circuit of claim 1, wherein the second current sampling circuit further comprises a second follower circuit;
the input end of the second following circuit is connected with the output end of the second rectifying circuit, and the output end of the second following circuit is connected with the second port of the processing chip.
8. The three-phase three-wire current sampling circuit according to claim 1, wherein an input terminal of the first rectifying circuit and an input terminal of the second rectifying circuit are connected to a non-inverting input terminal of the arithmetic circuit, and a voltage output from the arithmetic circuit is in a direction opposite to a current direction of the third electric wire;
or the input end of the first rectifying circuit and the input end of the second rectifying circuit are connected with the inverting input end of the operational circuit, and the direction of the voltage output by the operational circuit is the same as the current direction of the third wire.
9. The three-phase three-wire current sampling circuit of claim 1, wherein the third current sampling circuit further comprises a third follower circuit;
the input end of the third following circuit is connected with the output end of the third rectifying circuit, and the output end of the third following circuit is connected with the third port of the processing chip.
10. A three-phase three-wire system current sampling method, based on an implementation of the three-phase three-wire system current sampling circuit of any one of claims 1 to 9, the method comprising:
the first current sampling circuit obtains voltages at two ends of a first sampling resistor to obtain a first sampling voltage, the first rectifying circuit converts the first sampling voltage into a first direct current pulsating voltage and transmits the first direct current pulsating voltage to the processing chip;
the second current sampling circuit acquires voltages at two ends of a second sampling resistor to obtain a second sampling voltage, and the second rectifying circuit converts the second sampling voltage into a second direct current pulsating voltage and transmits the second direct current pulsating voltage to the processing chip;
the operation circuit adds the first sampling voltage and the second sampling voltage to obtain a third sampling voltage, and a third rectifying circuit converts the third sampling voltage into a third direct current pulsating voltage and transmits the third direct current pulsating voltage to the processing chip;
the processing chip obtains the first direct current ripple voltage, the second direct current ripple voltage and the third direct current ripple voltage, determines the current of the first wire according to the first direct current ripple voltage and the first sampling resistor, determines the current of the second wire according to the second direct current ripple voltage and the second sampling resistor, and determines the current of the third wire according to the third direct current ripple voltage and the resistance value of the first sampling resistor.
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| PCT/CN2020/101314 WO2022006847A1 (en) | 2020-07-10 | 2020-07-10 | Three-phase three-wire system current sampling circuit and method |
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- 2020-07-10 CN CN202080005858.0A patent/CN112930481A/en active Pending
- 2020-07-10 WO PCT/CN2020/101314 patent/WO2022006847A1/en active Application Filing
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| CN102375091A (en) * | 2010-08-18 | 2012-03-14 | 深圳长城开发科技股份有限公司 | Three-phase measurement circuit |
| CN102981042A (en) * | 2012-12-07 | 2013-03-20 | 深圳市安邦信电子有限公司 | Three-phase current detection circuit for frequency converter |
| CN205450229U (en) * | 2015-12-25 | 2016-08-10 | 施耐德万高（天津）电气设备有限公司 | Three -phase AC transfer circuit of sampling |
| CN205786809U (en) * | 2016-05-27 | 2016-12-07 | 浙江正泰电器股份有限公司 | The three-phase output current sampling circuit of converter |
| CN208043902U (en) * | 2018-04-12 | 2018-11-02 | 台安科技(无锡)有限公司 | A kind of output current of frequency converter sample circuit |
| CN209894870U (en) * | 2019-01-30 | 2020-01-03 | 深圳市库马克新技术股份有限公司 | Conversion circuit for sampling output current of three-phase frequency converter |
| CN110208592A (en) * | 2019-05-23 | 2019-09-06 | 淮安中科晶上智能网联研究院有限公司 | A kind of three-phase current method of sampling of three-phase motor |
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| WO2022006847A1 (en) | 2022-01-13 |
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