WO2022006847A1 - Three-phase three-wire system current sampling circuit and method - Google Patents

Abstract

Disclosed are a three-phase three-wire system current sampling circuit and method. The three-phase three-wire system circuit comprises a first sampling resistor, a first current sampling circuit, a second sampling resistor, a second current sampling circuit, a third current sampling circuit, and a processing chip, wherein the first sampling resistor is connected in series in a first wire, and an input end of the first current sampling circuit is connected to the first sampling resistor; the second sampling resistor is connected in series in a second wire, and an input end of the second current sampling circuit is connected to the second sampling resistor; the third current sampling circuit comprises an operational circuit, with the input end of the operational circuit respectively being connected to the first current sampling circuit and the second current sampling circuit; and output ends of the first current sampling circuit, the second current sampling circuit and the third current sampling circuit are connected to the processing chip. On the basis of the three-phase three-wire system current sampling circuit, further provided is the three-phase three-wire system current sampling method. By implementing the present application, the response time for current sampling is short, and the production costs are low.

Description

Three-phase three-wire current sampling circuit and method technical field

The present application relates to the field of electronic technology, in particular to a three-phase three-wire current sampling circuit and method.

Background technique

With the development of switching power supply and motor control technology, three-phase three-wire current sampling is indispensable in switching power supply and three-phase motor control. The three-phase three-wire current affects the power factor of the power supply and the control parameters of the motor. How to collect the current of the three-phase three-wire system, so as to realize the correction of the power factor of the power supply and the configuration of the control parameters of the motor, is a problem that has been studied all the time.

At present, there are two typical three-phase three-wire current sampling methods on the market, one is the current sampling of the Hall current sensor; the other is the current sampling of the current transformer. Among them, the Hall current sensor is a magnetoelectric conversion device made of semiconductor materials. The production process is relatively complicated and the production cost is relatively high; while the current transformer can only measure the sine wave AC current. When the waveform of the sine wave is distorted or the sine wave When the frequency of the wave changes, the response time of the current transformer is relatively long.

SUMMARY OF THE INVENTION

Based on the above-mentioned problems, the present application provides a three-phase three-wire current sampling circuit and method, in which two resistors are connected in series in any two-phase wires, the currents of any two-phase wires are sampled, and the arithmetic circuit is used to obtain the current sampling. The current of one phase is left, so that the current of the three-phase three-wire system can be sampled, and the response time of the current sampling is short and the production cost is low.

The present application provides a three-phase three-wire current sampling circuit. The three-phase three-wire current sampling circuit includes a first sampling resistor, a first current sampling circuit, a second sampling resistor, a second current sampling circuit, and a third current sampling circuit. The circuit and the processing chip, the three wires include a first wire, a second wire and a third wire, wherein:

The first sampling resistor is connected in series with the first wire, the first current sampling circuit includes a first rectifier circuit, the input end of the first rectifier circuit is connected to the first sampling resistor, the first The output end of the rectifier circuit is connected with the processing chip;

The second sampling resistor is connected in series with the second wire, the second current sampling circuit includes a second rectifier circuit, the input end of the second rectifier circuit is connected to the second sampling resistor, the second The output end of the rectifier circuit is connected to the processing chip, wherein the resistance value of the first sampling resistor is the same as the resistance value of the second sampling resistor;

The third current sampling circuit includes an arithmetic circuit and a third rectifier circuit. The input end of the arithmetic circuit is respectively connected to the input end of the first rectifier circuit and the input end of the second rectifier circuit. The arithmetic circuit The output end of the third rectifier circuit is connected to the input end of the third rectifier circuit, and the output end of the third rectifier circuit is connected to the processing chip.

In a possible embodiment, the first current sampling circuit further includes a first isolation amplifier circuit; an input end of the first isolation amplifier circuit is connected to both ends of the first sampling resistor.

Optionally, the first current sampling circuit further includes a first differential amplifier circuit;

The input end of the first differential amplifier circuit is connected to the output end of the first isolation amplifier circuit, and the output end of the first differential amplifier circuit is connected to the input end of the first rectifier circuit.

In a possible embodiment, the first current sampling circuit further includes a first follower circuit;

The input end of the first follower circuit is connected to the output end of the first rectifier circuit, and the output end of the first follower circuit is connected to the first port of the processing chip.

In a possible embodiment, the second current sampling circuit further includes a second isolation amplifier circuit;

The input end of the second isolation amplifier circuit is connected to both ends of the second sampling resistor.

Optionally, the second current sampling circuit further includes a second differential amplifier circuit;

The input terminal of the second differential amplifier circuit is connected to the output terminal of the second isolation amplifier circuit, and the output terminal of the second differential amplifier circuit is connected to the input terminal of the second rectifier circuit.

In a possible embodiment, the second current sampling circuit further includes a second follower circuit;

The input end of the second follower circuit is connected to the output end of the second rectifier circuit, and the output end of the second follower circuit is connected to the second port of the processing chip.

In a possible implementation manner, the input terminal of the first rectifier circuit and the input terminal of the second rectifier circuit are connected to the non-inverting input terminal of the operation circuit, and the voltage direction output by the operation circuit is the same as that of the operation circuit. The current direction of the third wire is opposite;

Or, the input end of the first rectifier circuit and the input end of the second rectifier circuit are connected to the inverting input end of the operation circuit, and the voltage direction output by the operation circuit is the same as the current direction of the third wire same.

In a possible embodiment, the third current sampling circuit further includes a third follower circuit;

The input end of the third follower circuit is connected to the output end of the third rectifier circuit, and the output end of the third follower circuit is connected to the third port of the processing chip.

The present application also provides a three-phase three-wire current sampling method, based on the three-phase three-wire current sampling circuit described above, the method includes:

The first current sampling circuit obtains the voltage across the first sampling resistor to obtain the first sampling voltage, the first rectifier circuit converts the first sampling voltage into a first DC pulsating voltage, and converts the first DC pulsating voltage transmitted to the processing chip;

The second current sampling circuit obtains the voltage across the second sampling resistor to obtain the second sampling voltage, the second rectifier circuit converts the second sampling voltage into a second DC pulsating voltage, and transmits the second DC pulsating voltage to the processing chip;

The arithmetic circuit adds the first sampled voltage and the second sampled voltage to obtain a third sampled voltage, and a third rectifier circuit converts the third sampled voltage into a third DC pulsating voltage, and converts the third sampled voltage into a third DC pulsating voltage. Three DC pulsating voltages are transmitted to the processing chip;

The processing chip acquires the first DC ripple voltage, the second DC ripple voltage and the third DC ripple voltage, and determines the first DC ripple voltage according to the first DC ripple voltage and the first sampling resistor. The current of a wire, the current of the second wire is determined according to the second DC pulsating voltage and the second sampling resistor, and the current of the second wire is determined according to the third DC pulsating voltage and the resistance value of the first sampling resistor The current of the third wire.

The present application uses two sampling resistors to perform current sampling on any two phases of the three-phase three-wire, to obtain the first sampling voltage and the second sampling voltage, and the arithmetic circuit in the third current sampling circuit obtains the first sampling voltage and the second sampling voltage. sampling the voltage and the second sampling voltage, and adding the first sampling voltage and the second sampling voltage to obtain a third sampling voltage; the first rectifier circuit converts the first sampling voltage into the first DC ripple voltage, the second rectifier circuit converts the second sampled voltage into a second DC ripple voltage, the third rectifier circuit converts the third sample voltage into a third DC ripple voltage, so The processing chip collects the first DC pulsating voltage, the second DC pulsating voltage and the third DC pulsating voltage in real time, and obtains the first electric wire according to the first DC pulsating voltage and the first sampling resistance value. The current of the second wire is obtained according to the second DC pulsating voltage and the second sampling resistance value, and the current of the third wire is obtained according to the third DC pulsating voltage and the resistance value of the first sampling resistor. Implement the embodiment of the present application, connect two resistors in series in any two-phase wires, sample the wire currents of any two-phase, and use the arithmetic circuit to obtain the current of the remaining one phase, so as to realize the current sampling of the three-phase three-wire system , the response time of current sampling is short and the production cost is low.

Description of drawings

1 is a circuit block diagram of a three-phase three-wire current sampling circuit provided by an embodiment of the present application;

2 is a circuit block diagram of another three-phase three-wire current sampling circuit provided by an embodiment of the present application;

3 is a circuit schematic diagram of still another three-phase three-wire current sampling circuit provided by an embodiment of the present application;

4 is a schematic waveform diagram of a three-phase three-wire current sampling circuit according to an embodiment of the present application;

FIG. 5 is a schematic flowchart of a three-phase three-wire current sampling method according to an embodiment of the present application.

detailed description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

The implementation of the technical solutions of the present application will be further described in detail below with reference to the accompanying drawings.

Referring first to FIG. 1 , FIG. 1 is a circuit block diagram of a three-phase three-wire current sampling circuit according to an embodiment of the present application. As shown in FIG. 1 , the three-phase three-wire current sampling circuit includes a first sampling resistor 100, a first current sampling circuit 101, a second sampling resistor 110, a second current sampling circuit 111, a third current sampling circuit 121, and a processing Chip 130, the three wires include a first wire, a second wire and a third wire, wherein:

The first sampling resistor 100 is connected in series with the first wire, the first current sampling circuit 101 includes a first rectifier circuit 1010 , and the input end of the first rectifier circuit 1010 is connected to the first sampling resistor 100 , the output end of the first rectifier circuit 1010 is connected to the processing chip 130 . Specifically, since the current of the first wire flows through the first sampling resistor 100 and forms a voltage drop across the resistor, the first current sampling circuit 101 obtains the voltage across the first sampling resistor 100 to obtain The first sampling voltage. The first sampling voltage reflects the current of the first wire. In a possible embodiment, the three-phase three-wire is a mains power supply mode, and the first wire, the second wire and the first wire are If the three wires are AC voltage, the first sampling voltage is also AC voltage. The first rectifier circuit 1010 converts the first sampled voltage into a first DC pulsating voltage, and transmits the first DC pulsating voltage to the processing chip 130 . Since the voltage recognized by the processing chip 130 is a positive voltage, and the first sampling voltage obtained by the first current sampling circuit 101 is an AC voltage, and the AC voltage includes a negative voltage, the first rectifier circuit 1010 converts the A negative voltage in the first sampled voltage is converted into a positive voltage, that is, the first sampled voltage is converted into the first DC pulsating voltage, so as to be recognized by the processing chip 130 . It can be understood that the first DC pulsating voltage may be referred to as a DC voltage, and the voltage value of the first DC pulsating voltage is a positive voltage.

The second sampling resistor 110 is connected in series with the second wire, the second current sampling circuit 111 includes a second rectifier circuit 1110 , and the input end of the second rectifier circuit 1110 is connected to the second sampling resistor 110 , the output end of the second rectifier circuit 1110 is connected to the processing chip 130 , wherein the resistance value of the first sampling resistor 100 is the same as the resistance value of the second sampling resistor 110 . Specifically, since the current of the second wire flows through the second sampling resistor 110 and forms a voltage drop across the resistor, the second current sampling circuit 111 obtains the voltage across the second sampling resistor 110 to obtain The second sampling voltage. The second sampled voltage reflects the current of the second wire. In a possible embodiment, the second sampling voltage is an AC voltage. The second rectifier circuit 1110 converts the second sampled voltage into a second DC pulsating voltage, and transmits the second DC pulsating voltage to the processing chip 130 . Since the voltage identified by the processing chip 130 is a positive voltage, and the second sampling voltage obtained by the second current sampling circuit 111 is an AC voltage, and the AC voltage includes a negative voltage, the second rectifier circuit 1110 converts the A negative voltage in the second sampled voltage is converted into a positive voltage, that is, the second sampled voltage is converted into the second DC pulsating voltage, so as to be recognized by the processing chip 130 . It can be understood that, the second DC pulsating voltage may be referred to as a DC voltage, and the second DC pulsating voltage is a positive voltage.

The third current sampling circuit 121 includes an operation circuit 1210 and a third rectifier circuit 1211 . The input end of the operation circuit 1210 is respectively connected with the input end of the first rectifier circuit 1010 and the input end of the second rectifier circuit 1110 . The output terminal of the arithmetic circuit 1210 is connected to the input terminal of the third rectifier circuit 1211 , and the output terminal of the third rectifier circuit 1211 is connected to the processing chip 130 . Specifically, the operation circuit 1210 adds the first sampling voltage and the second sampling voltage to obtain a third sampling voltage. According to Kirchhoff's current law, in the three-phase three-wire circuit, the sum of the currents of the first wire, the second wire and the third wire is zero. Exemplarily, the current of the first wire is I _a , the current of the second wire is I _b , and the current of the second wire is I _c . According to Kirchhoff’s current law, it can be known that I _a +I _b +I _c =0, then (I _a +I _b +I _c )×R=0 holds, R is the resistance of the first sampling resistor 100 and the second sampling resistor 110 , and I _a ×R It is the voltage drop formed by the current of the first wire flowing through the first sampling resistor 100, that is, the first sampling voltage; in the same way, the I _b ×R is the current flowing through the second wire. The voltage drop formed by the second sampling resistor 110 is the second sampling voltage. The third current sampling circuit 121 includes a third rectification circuit 1211, the third rectification circuit 1211 converts the third sampling voltage into a third DC pulsating voltage, the third current sampling circuit 121 and the processing chip 130 is connected, and the third current sampling circuit 121 transmits the third DC pulsating voltage to the processing chip 130 . Since the third sampling voltage is obtained by adding the first sampling voltage and the second sampling voltage through the operation circuit 1210, that is, the first sampling voltage and the second sampling voltage are AC voltages, then The third sampling voltage is also an AC voltage. The voltage recognized by the processing chip 130 is a positive voltage, and the third sampled voltage obtained by the operation circuit 1210 is an AC voltage, and the AC voltage includes a negative voltage, and the third rectifier circuit 1211 converts the third sampled voltage The third DC pulsating voltage is generated to be recognized by the processing chip 130 . It can be understood that, the third DC pulsating voltage may be referred to as a DC voltage, and the third DC pulsating voltage is a positive voltage.

In a possible implementation manner, the input terminal of the first rectifier circuit 1010 and the input terminal 1110 of the second rectifier circuit 1110 are connected to the non-inverting input terminal of the operation circuit 1210, and the output terminal of the operation circuit 1210 The voltage direction is opposite to the current direction of the third wire. Specifically, the operational circuit 1210 may be a non-inverting adding operational amplifier, the first rectifying circuit 1010 transmits the first sampled voltage to the non-inverting input of the adding operational amplifier, and the second rectifying circuit 1110 The second sampling voltage is transmitted to the non-inverting input terminal of the summing operational amplifier, and the output terminal of the summing operational amplifier is the sum of the first sampling voltage and the second sampling voltage, that is, the third sampling voltage The sampling voltage is I _a ×R+I _b ×R. According to (I _a +I _b +I _c )×R=0, it can be known that I _c ×R=-(I _a ×R+I _b ×R), then the The direction of the third sampling voltage I _a ×R+I _b ×R is opposite to the direction of the current I _{c of the third wire.} Optionally, the processing chip 130 performs further processing according to the direction of the third sampled voltage that is opposite to the direction of the third wire current, and when fitting the current curve according to the third DC pulsating voltage, the The phase is reversed, so that the current curve fitted by the processing chip 130 is the current curve of the third wire.

In another possible implementation manner, the input end of the first rectifier circuit 1010 and the input end of the second rectifier circuit 1110 are connected to the inverting input end of the operation circuit 1210, then the operation circuit 1210 The output voltage direction is the same as the current direction of the third wire. Specifically, the operational circuit 1210 may be an inverting summing operational amplifier, the first rectifying circuit 1010 transmits the first sampled voltage to the inverting input terminal of the summing operational amplifier, and the second rectifying circuit 1110 The second sampling voltage is transmitted to the inverting input terminal of the summing operational amplifier, then the absolute value of the output terminal of the summing operational amplifier is the sum of the first sampling voltage and the second sampling voltage, that is, the sum of the first sampling voltage and the second sampling voltage. The third sampling voltage is -(I _a ×R+I _b ×R), according to (I _a +I _b +I _c )×R=0, it can be known that I _c ×R=-(I _a ×R+I _b ×R), then the third sampling voltage -(I _a ×R+I _b ×R) is in the same direction as _{the current I c of the third wire.} Optionally, the processing chip 130 fits the current curve according to the third sampled voltage without inverting the phase, and the current curve fitted by the processing chip 130 is the current curve of the third wire, Implementing this embodiment can simplify the processing process of the processing chip 130 and save software resources.

Based on the realization effect of the circuit, the current sampling circuit of the three-phase three-wire system may include other circuits in addition to the circuits included in the above embodiments in conjunction with FIG. 1 . The included circuits are described in detail. Referring to FIG. 2 , FIG. 2 is a circuit block diagram of another three-phase three-wire sampling circuit according to an embodiment of the present application. as shown in picture 2:

In a possible embodiment, the first current sampling circuit 101 further includes a first isolation amplifier circuit 1011 ; the input end of the first isolation amplifier circuit 1011 is connected to both ends of the first sampling resistor 100 . Specifically, the first isolation amplifying circuit 1011 amplifies the voltage of the first sampling resistor 100 to obtain the first sampling voltage. The first isolation amplifying circuit 1011 also has the function of isolating its own input port from its own output port, and isolates the electromagnetic interference on the first wire connected to the input end of the first isolation and amplifying circuit 1011 to avoid electromagnetic interference. The electromagnetic interference is transmitted to the processing chip 130 . Optionally, the first isolation amplifier circuit 1011 may be a fully differential isolation amplifier with a model of AMC1200. Optionally, if the resistance value of the first sampling resistor 100 and the second sampling resistor 110 is 5 milliohms, the first isolation amplifying circuit 1011 obtains the amplitude of the voltage across the first sampling resistor 100 . When the value is about several hundred millivolts, the first isolation amplifying circuit 1011 amplifies the voltage across the first sampling resistor 100 . Optionally, the fully differential isolation amplifier superimposes a DC component of 2.5V on the voltage across the first sampling resistor 100 as the first sampling voltage.

Further, the first current sampling circuit 101 further includes a first differential amplifier circuit 1012 .

The input terminal of the first differential amplifier circuit 1012 is connected to the output terminal of the first isolation amplifier circuit 1011 , and the output terminal of the first differential amplifier circuit 1012 is connected to the input terminal of the first rectifier circuit 1010 . Specifically, the first differential amplifier circuit 1012 removes the DC component of the isolated and amplified voltage in the first isolation amplifier circuit 1011, and uses the isolated amplified voltage from which the DC component is removed as the first sampling voltage. Exemplarily, the first differential amplifier circuit 1012 performs a differential operation on the voltage output by the first isolation amplifier circuit 1011, and subtracts the DC voltage signal in the differential voltage output by the first isolation amplifier circuit 1011. , the DC component is subtracted, and the AC component remains, and the isolated amplified voltage from which the DC component is removed is used as the first sampling voltage. Optionally, the first differential amplifier circuit 1012 may be a differential operational amplifier.

Optionally, the first current sampling circuit 101 further includes a first follower circuit 1013 . The input end of the first follower circuit 1013 is connected to the output end of the first rectifier circuit 1010 , and the output end of the first follower circuit 1013 is connected to the first port of the processing chip 130 . Specifically, the magnitude of the output voltage of the first follower circuit 1013 is the same as the magnitude of the voltage input to the first follower circuit 1013 , that is, the output voltage of the first rectifier circuit 1010 and the output of the first follower circuit 1013 voltage is the same. Exemplarily, the first follower circuit 1013 may be a voltage follower, and the voltage follower has the characteristics of high input impedance and low output impedance.

In another possible embodiment, the second current sampling circuit 111 further includes a second isolation amplifier circuit 1111 ; the input end of the second isolation amplifier circuit 1111 is connected to both ends of the second sampling resistor 110 . Specifically, the second isolation amplifying circuit 1111 amplifies the voltage of the second sampling resistor 110 to obtain the second sampling voltage. The second isolation amplifying circuit 1111 also has the function of isolating its own input and output ports from its own output port, and isolates the electromagnetic interference on the second wire connected to the input end of the second isolation amplifying circuit 1111, The electromagnetic interference is prevented from being transmitted to the processing chip 130 . Optionally, the second isolation amplifier circuit 1111 may be a fully differential isolation amplifier with a model of AMC1200. In a possible implementation manner, if the resistance value of the first sampling resistor 100 and the second sampling resistor 110 is 5 milliohms, the second isolation amplifier circuit 1111 obtains the second sampling resistor 110 The amplitude of the voltage at both ends is about several hundred millivolts, and the second isolation amplifying circuit 1111 amplifies the voltage at both ends of the second sampling resistor 110 . Optionally, the fully differential isolation amplifier superimposes a DC component of 2.5V on the voltage across the second sampling resistor 110 as the second sampling voltage.

Further, the second current sampling circuit 111 further includes a second differential amplifier circuit 1112 . The input terminal of the second differential amplifier circuit 1112 is connected to the output terminal of the second isolation amplifier circuit 1111 , and the output terminal of the second differential amplifier circuit 1112 is connected to the input terminal of the second rectifier circuit 1110 . Specifically, the second differential amplifier circuit 1112 removes the DC component of the isolated and amplified voltage in the second isolation amplifier circuit 1111, and uses the isolated amplified voltage from which the DC component is removed as the second sampling voltage. Exemplarily, the second differential amplifier circuit 1112 performs a differential operation on the voltage output by the second isolation amplifier circuit 1111, and subtracts the DC voltage signal in the differential voltage output from the second isolation amplifier circuit 1111. , the DC component is subtracted, and the AC component remains, and the isolated amplified voltage from which the DC component is removed is used as the second sampling voltage. Optionally, the second differential amplifier circuit 1112 may be a differential operational amplifier.

Optionally, the second current sampling circuit 111 further includes a second follower circuit 1113 . The input end of the second follower circuit 1113 is connected to the output end of the second rectifier circuit 1110 , and the output end of the second follower circuit 1113 is connected to the second port of the processing chip 130 . Specifically, the magnitude of the output voltage of the second follower circuit 1113 is the same as the magnitude of the voltage input to the second follower circuit 1113 , that is, the output voltage of the second rectifier circuit 1110 and the output of the second follower circuit 1113 voltage is the same. Exemplarily, the second follower circuit 1113 may be a voltage follower. The voltage follower has the characteristics of high input impedance and low output impedance.

In another possible embodiment, the third current sampling circuit 121 further includes a third follower circuit 1212 . The input terminal of the third follower circuit 1212 is connected to the output terminal of the third rectifier circuit 1211 , and the output terminal of the third follower circuit 1212 is connected to the third port of the processing chip 130 . Specifically, the output voltage of the third follower circuit 1212 is the same as the voltage input to the third follower circuit 1212 , that is, the output voltage of the operation circuit 1210 is the same as the output voltage of the third follower circuit 1212 . Exemplarily, the third follower circuit 1212 may be a voltage follower, and the voltage follower has the characteristics of high input impedance and low output impedance.

In a possible embodiment, the three-phase three-wire is used to provide electric power for the charger 140 . Specifically, the three-phase three-wire comes from the three-phase three-wire in the commercial power supply, and the phases of the three phases differ by 120°, respectively, and provide electrical energy for the three phases of the charger 140 respectively.

The working principle of the three-phase three-wire current sampling circuit is described below with reference to the accompanying drawings, referring to FIG. 3 and FIG. 4 .

Referring first to FIG. 3 , FIG. 3 is a circuit schematic diagram of still another three-phase three-wire current sampling circuit provided by an embodiment of the present application. As shown in FIG. 3 , the three-phase three-wire current sampling circuit includes a first sampling resistor 300, a first current sampling circuit 301, a second sampling resistor 310, a second current sampling circuit 311, a third current sampling circuit 320, and a processing In the chip 330, the three wires include a first wire, a second wire and a third wire, wherein:

The first sampling resistor 300 includes a first resistor R1, which is connected in series with the first wire; the second sampling resistor 310 includes a second resistor R2, which is connected in series with the first wire. in the second wire. Specifically, the resistance values of the first resistor R1 and the second resistor R2 are the same. Optionally, the resistance values of the first resistor R1 and the second resistor R2 are 5 milliohms. The first resistor R1 and the second resistor R2 affect the current sampling accuracy of the three-phase three-wire system. In order to improve the current sampling accuracy, a resistor with high accuracy, small temperature drift and small parasitic parameters should be selected. The cost of the first resistor R1 and the second resistor R2 is relatively high. In this application, Kirchhoff’s current law is used, and two sampling resistors are used to collect the current of the three wires, avoiding the use of Hall current sensors with higher production costs. Performing current sampling further saves the production cost of a sampling resistor and an isolation amplifier.

The first current sampling circuit 301 includes a first rectifier circuit 3011, and the first rectifier circuit 3011 includes a first operational amplifier U1, a second operational amplifier U2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, The sixth resistor R6, the seventh resistor R7, the first diode D1 and the second diode D2, optionally, the first rectifier circuit 3011 may further include an eighth resistor R8 and a ninth resistor R9.

In a possible embodiment, the first current sampling circuit 301 further includes a first isolation amplifier circuit 3012, and the first isolation amplifier circuit 3012 includes a first fully differential isolation amplifier Q1.

Further, the first current sampling circuit 301 further includes a first differential amplifier circuit 3013, and the first differential amplifier circuit 3013 includes a third operational amplifier U3, a tenth resistor R10, an eleventh resistor R11, and a twelfth resistor R12 and a thirteenth resistor R13.

Further, the first current sampling circuit 301 further includes a first follower circuit 3014, and the first follower circuit 3014 includes a fourth operational amplifier U4, wherein:

The first sampling resistor 300 is connected to the first isolation amplifier circuit 3012. Specifically, the first fully differential isolation amplifier Q1 includes 8 ports, the first port and the eighth port are power ports, and the fourth port and the The fifth port is a ground port, the second port and the third port are differential input ports, the sixth port and the seventh port are differential output ports, and both ends of the first resistor R1 are connected to the first fully differential isolation amplifier Q1. The second port and the third port are connected.

To better understand the functional realization of each circuit, reference may be made to FIG. 4 , which is a schematic waveform diagram of a three-phase three-wire current sampling circuit according to an embodiment of the present application. It can be understood that each waveform diagram in FIG. 4 is a schematic waveform for realizing the function of each circuit, and does not represent the relationship between the voltage amplitude and phase output by each circuit.

As shown in FIG. 4 , the schematic diagram of the waveform of the input terminal of the first fully differential isolation amplifier is shown as the sampling voltage 4 a in FIG. 4 . The sampling voltage 4 a is the schematic diagram of the voltage waveform across the first resistor R1 , which reflects the The current of the first wire. After the first fully differential isolation amplifier Q1, the output waveform is as shown in the sampling voltage 4b in FIG. 4. The first fully differential amplifier Q1 isolates and amplifies the voltage across the first sampling resistor 300 as the The first sampled voltage is superimposed with a DC component through the first isolation amplifying circuit 3012. Exemplarily, the amplitude of the DC component is 2.5V.

The first isolation amplifier circuit 3012 is connected to the first differential amplifier circuit 3013. Specifically, the first isolation amplifier circuit 3012 includes a first fully differential isolation amplifier Q1. The sixth port is connected to one end of the tenth resistor R10, the seventh port of the first fully differential isolation amplifier Q1 is connected to one end of the eleventh resistor R11, and the other end of the eleventh resistor R11 is connected to the One end of the twelfth resistor R12 is connected to the non-inverting input end of the third operational amplifier U3, the other end of the twelfth resistor R12 is connected to ground, and the other end of the tenth resistor R10 is connected to the tenth resistor R10. One end of the three resistors R13 is connected to the inverting input end of the third operational amplifier U3, and the other end of the thirteenth resistor R13 is connected to the output end of the third operational amplifier U3. The output waveform of the first differential amplifier circuit 3013 is shown as the sampling voltage 4c in FIG. 4 . The input terminal of the first differential amplifier circuit 3013 is connected to the output terminal of the first isolation amplifier circuit 3012. A differential amplifying circuit 3013 is used to remove the DC component of the isolated and amplified voltage in the first isolation amplifying circuit 3012, and the isolated and amplified voltage from which the DC component has been removed is used as the first sampling voltage. At this time, the first sampling voltage The waveform of the sampling voltage is shown as the sampling voltage 4c.

The first differential amplifier circuit 3013 is connected to the first rectifier circuit 3011. Specifically, the output end of the third operational amplifier U3 in the first differential amplifier circuit 3013 is connected to one end of the fifth resistor R5 and the first end of the fifth resistor R5. One end of the three resistors R3 is connected, and the other end of the third resistor R3 is connected to the inverting input end of the first operational amplifier U1, the cathode of the first diode D1 and one end of the fourth resistor R4 , the anode of the first diode D1 is connected to the cathode of the second diode D2 and the output end of the first operational amplifier U1, and the anode of the second diode D2 is connected to the fourth The other end of the resistor R4 is connected to one end of the sixth resistor R6, and the other end of the sixth resistor R6 is connected to the inverting input end of the second operational amplifier U2 and one end of the seventh resistor R7, so The other end of the seventh resistor R7 is connected to the output end of the second operational amplifier U2. Optionally, the non-inverting input terminal of the first operational amplifier U1 is connected to one end of the eighth resistor R8, and the other end of the eighth resistor R8 is connected to ground, and the eighth resistor R8 can stabilize the first The working state of an operational amplifier U1. Similarly, the non-inverting input end of the second operational amplifier U2 is connected to one end of the ninth resistor R9, and the other end of the ninth resistor R9 is connected to the ground for stabilizing the working state of the second operational amplifier U2. The first rectifier circuit 3011 is used for converting the first sampling voltage into a first DC pulsating voltage, and the first current sampling circuit 301 is connected to the processing chip 330 and is used for converting the first DC pulsating voltage. The pulsating voltage is transmitted to the processing chip 330. Specifically, the first rectifier circuit 3011 converts the first sampled voltage whose waveform is shown as the sampling voltage 4c into the first DC pulsating voltage shown as the DC pulsating voltage 4d.

The first rectifier circuit 3011 is connected to the first follower circuit 3014. Specifically, the output terminal of the second operational amplifier U2 is connected to the non-inverting input terminal of the fourth operational amplifier U4. The fourth operational amplifier The inverting input terminal of U4 is connected to the output terminal of the fourth operational amplifier U4 , and the output terminal of the fourth operational amplifier U4 is connected to the first port of the processing chip 330 . The first follower circuit 3014 transmits the first DC pulse voltage as shown in 4d to the processing chip 330 . The processing chip 330 acquires the first DC ripple voltage, and determines the current of the first wire according to the first DC ripple voltage and the resistance value of the first resistor R1.

In a possible implementation manner, the first operational amplifier U1 , the second operational amplifier U2 , the third operational amplifier U3 and the fourth operational amplifier U4 may be integrated on a chip that integrates operational amplifiers.

The first current sampling circuit 301 may further include a fourteenth resistor R14 and a first capacitor C1, one end of the fourteenth resistor R14 is connected to the output end of the fourth operational amplifier U4 in the first follower circuit 3014, The other end of the fourteenth resistor R14 is connected to one end of the first capacitor C1 and the first port of the processing chip 330 , and the other end of the first capacitor C1 is connected to ground. The fourteenth resistor R14 and the first capacitor C1 form an RC low-pass filter circuit to prevent high-frequency signals from interfering with the processing chip 330 .

The second current sampling circuit 311 includes a second rectifier circuit 3111, and the second rectifier circuit 3111 includes a fifth operational amplifier U5, a sixth operational amplifier U6, a fifteenth resistor R15, a sixteenth resistor R16, and a seventeenth Resistor R17, eighteenth resistor R18, nineteenth resistor R19, third diode D3 and fourth diode D4, optionally, the second rectifier circuit 3111 may further include a twentieth resistor R20 and a fourth diode D4. Twenty-one resistors R21.

In a possible embodiment, the second current sampling circuit 311 further includes a second isolation amplifier circuit 3112, and the second isolation amplifier circuit 3112 includes a second fully differential isolation amplifier Q2.

Further, the second current sampling circuit 311 further includes a second differential amplifier circuit 3113, and the second differential amplifier circuit 3113 includes a seventh operational amplifier U7, a twenty-second resistor R22, a twenty-third resistor R23, and a seventh operational amplifier U7. Twenty-four resistors R24 and twenty-fifth resistors R25.

Further, the second current sampling circuit 311 further includes a second follower circuit 3114, and the second follower circuit 3114 includes an eighth operational amplifier U8, wherein:

The second sampling resistor 310 is connected to the second isolation amplifier circuit 3112. Specifically, the second isolation amplifier circuit 3112 includes a second fully differential isolation amplifier Q2, and the second fully differential isolation amplifier Q2 includes eight ports, the first port and the eighth port are power ports, the fourth port and the fifth port are ground ports, the second port and the third port are differential input ports, the sixth port and the seventh port are differential output ports, the Both ends of the second resistor R2 are connected to the second port and the third port of the second fully differential isolation amplifier Q2.

To better understand the functional realization of each circuit, reference may be made to FIG. 4 , which is a schematic waveform diagram of a three-phase three-wire current sampling circuit according to an embodiment of the present application.

As shown in FIG. 4 , the schematic diagram of the input terminal waveform of the second fully differential isolation amplifier is shown as the sampling voltage 4a in FIG. 4 . The sampling voltage 4a is the schematic diagram of the voltage waveform across the second resistor R2, reflecting the first Two wire currents. After the second fully differential isolation amplifier Q2, the output waveform is as shown in the sampling voltage 4b. The second fully differential amplifier Q2 isolates and amplifies the voltage across the second sampling resistor 310 as the second sampling voltage. voltage, the second sampled voltage is superimposed with a DC component through the second isolation amplifier circuit 3112, exemplarily, the amplitude of the DC component is 2.5V.

The second isolation amplifier circuit 3112 is connected to the second differential amplifier circuit 3113. Specifically, the sixth port of the second fully differential isolation amplifier Q2 is connected to one end of the twenty-second resistor R22. The seventh port of the second fully differential isolation amplifier Q2 is connected to one end of the twenty-third resistor R23, the other end of the twenty-third resistor R23 is connected to one end of the twenty-fourth resistor R24 and the first The non-inverting input end of the seventh operational amplifier U7 is connected, the other end of the twenty-fourth resistor R24 is connected to ground, the other end of the twenty-second resistor R22 is connected to one end of the twenty-fifth resistor R25 and the The inverting input end of the seventh operational amplifier U7 is connected, and the other end of the twenty-fifth resistor R25 is connected to the output end of the seventh operational amplifier U7. The output waveform of the second differential amplifying circuit 3113 is shown as the sampling voltage 4c. The input end of the second differential amplifying circuit 3113 is connected to the output end of the second isolation amplifying circuit 3112, and the second differential amplifying circuit 3112 3113 is used to remove the DC component of the isolated and amplified voltage in the second isolation amplifying circuit 3112, and the isolated and amplified voltage from which the DC component has been removed is used as the second sampling voltage. At this time, the waveform of the second sampling voltage The schematic diagram is shown as sampling voltage 4c.

The second differential amplifier circuit 3113 is connected to the second rectifier circuit 3111. Specifically, the output end of the seventh operational amplifier U7 in the second differential amplifier circuit 3113 is connected to one end of the fifteenth resistor R15 and One end of the seventeenth resistor R17 is connected, and the other end of the fifteenth resistor R15 is connected to the inverting input end of the fifth operational amplifier U5, the cathode of the third diode D3 and the sixteenth resistor One end of R16 is connected, the anode of the third diode D3 is connected to the cathode of the fourth diode D4 and the output end of the fifth operational amplifier U5, the anode of the fourth diode D4 is connected to The other end of the sixteenth resistor R16 and one end of the eighteenth resistor R18 are connected, and the other end of the eighteenth resistor R18 is connected to the inverting input end of the sixth operational amplifier U6 and the tenth One end of the nineteenth resistor R19 is connected, and the other end of the nineteenth resistor R19 is connected to the output end of the sixth operational amplifier U6. Optionally, the non-inverting input end of the fifth operational amplifier U5 is connected to one end of the twentieth resistor R20, the other end of the twentieth resistor R20 is connected to the ground, and the twentieth resistor R20 can be stable. The working state of the fifth operational amplifier U5. Similarly, the non-inverting input end of the sixth operational amplifier U6 is connected to one end of the twenty-first resistor R21, and the other end of the twenty-first resistor R21 is connected to the ground for stabilizing the sixth operational amplifier U6 working status. The second rectifier circuit 3111 is used for converting the second sampling voltage into a second DC pulsating voltage, and the second current sampling circuit 311 is connected to the processing chip 330 and is used for converting the second DC pulsating voltage The data is transmitted to the processing chip 330 . Specifically, the second rectifier circuit 3111 converts the second sampling voltage as shown by the sampling voltage 4c into a second DC pulsating voltage as shown by the DC pulsating voltage 4d.

The second rectifier circuit 3111 is connected to the second follower circuit 3114. Specifically, the output terminal of the sixth operational amplifier U6 is connected to the non-inverting input terminal of the eighth operational amplifier U8. The eighth operational amplifier The inverting input terminal of U8 is connected to the output terminal of the eighth operational amplifier U8 , and the output terminal of the eighth operational amplifier U8 is connected to the second port of the processing chip 330 . The second follower circuit 3114 transmits the second DC pulse voltage as shown by the DC pulse voltage 4d to the processing chip 330 .

Optionally, the fifth operational amplifier U5 , the sixth operational amplifier U6 , the seventh operational amplifier U7 and the eighth operational amplifier U8 may be integrated on a chip that integrates operational amplifiers.

The second current sampling circuit 311 may further include a twenty-sixth resistor R26 and a second capacitor C2. One end of the twenty-sixth resistor R26 is connected to the output end of the eighth operational amplifier U8 in the second follower circuit 3114. connection, the other end of the twenty-sixth resistor R26 is connected to one end of the second capacitor C2 and the second port of the processing chip 330, and the other end of the second capacitor C2 is connected to ground. The twenty-sixth resistor R26 and the second capacitor C2 form an RC low-pass filter circuit to prevent high-frequency signals from interfering with the processing chip 330 .

The third current sampling circuit 320 includes an operation circuit 3201 and a third rectifier circuit 3202. The operation circuit 3201 includes a ninth operational amplifier U9, a twenty-seventh resistor R27, a twenty-eighth resistor R28, and a twenty-ninth resistor. R29 and a thirtieth resistor R30; the third rectifier circuit 3202 includes a tenth operational amplifier U10, an eleventh operational amplifier U11, a thirty-first resistor R31, a thirty-second resistor R32, a thirty-third resistor R33, The thirty-fourth resistor R34, the thirty-fifth resistor R35, the fifth diode D5 and the sixth diode D6, optionally, the third rectifier circuit 3202 may further include the thirty-sixth resistor R36 and the sixth diode D6. Thirty-seven resistors R37.

Optionally, the third current sampling circuit 320 further includes a third follower circuit 3203, and the third follower circuit 3203 includes a twelfth operational amplifier U12, wherein:

The third current sampling circuit 320 is connected to the first current sampling circuit 301 and the second current sampling circuit 311 respectively. Specifically, the first differential amplifier circuit 3013 in the first current sampling circuit 301 is connected to the If the operation circuit 3201 in the third current sampling voltage 320 is connected, the output end of the third operational amplifier U3 is connected to one end of the twenty-seventh resistor R27, and the other end of the twenty-seventh resistor R27 is connected to the The inverting input terminal of the ninth operational amplifier U9 and one terminal of the twenty-ninth resistor R29 are connected; the second differential amplifier circuit 3113 in the second current sampling circuit 311 is connected to the third current sampling circuit 320 connected to the operational circuit 3201, the output end of the seventh operational amplifier U7 is connected to one end of the twenty-eighth resistor R28, and the other end of the twenty-eighth resistor R28 is connected to the ninth operational amplifier U9 The inverting input end and one end of the twenty-ninth resistor R29 are connected. The other end of the twenty-ninth resistor R29 is connected to the output end of the ninth operational amplifier U9, one end of the thirtieth resistor R30 is connected to the non-inverting input end of the ninth operational amplifier U9, and the third The other end of the thirty resistor R30 is connected to the ground. The ninth operational amplifier U9 inverts and adds the first sampling voltage and the second sampling voltage to obtain the third sampling voltage, then the output terminal of the ninth operational amplifier U9 outputs a third wire The voltage waveform of is opposite to the phase of the waveform diagram in the sampled voltage 4a.

The operation circuit 3201 is connected to the third rectifier circuit 3202. Specifically, the output end of the ninth operational amplifier U9 in the operation circuit 3201 is connected to one end of the thirty-first resistor R31 and the thirty-third resistor. One end of R33 is connected, and the other end of the thirty-first resistor R31 is connected to the inverting input terminal of the tenth operational amplifier U10, the cathode of the fifth diode D5 and the third-second resistor R32 one end is connected, the anode of the fifth diode D5 is connected to the cathode of the sixth diode D6 and the output end of the tenth operational amplifier U10, the anode of the sixth diode D6 is connected to the The other end of the thirty-second resistor R32 and one end of the thirty-fourth resistor R34 are connected, and the other end of the thirty-fourth resistor R34 is connected to the inverting input end of the eleventh operational amplifier U11 and the One end of the thirty-fifth resistor R35 is connected, and the other end of the thirty-fifth resistor R35 is connected to the output end of the eleventh operational amplifier U11. Optionally, the non-inverting input terminal of the tenth operational amplifier U10 is connected to one end of the thirty-sixth resistor R36, the other end of the thirty-sixth resistor R36 is connected to ground, and the thirty-sixth resistor R36 is connected to the ground. R36 can stabilize the working state of the tenth operational amplifier U10. Similarly, the non-inverting input end of the eleventh operational amplifier U11 is connected to one end of the thirty-seventh resistor R37, and the other end of the thirty-seventh resistor R37 is connected to the ground for stabilizing the eleventh operation The working state of amplifier U11. The third rectifier circuit 3202 is used for converting the third sampling voltage into a third DC pulsating voltage, and the third current sampling circuit 320 is connected to the processing chip 330 and is used for converting the third DC pulsating voltage It is transmitted to the processing chip 330. Exemplarily, the waveform diagram of the third DC pulsating voltage is shown as the DC pulsating voltage 4d.

The third rectifier circuit 3202 is connected to the third follower circuit 3203. Specifically, the output terminal of the eleventh operational amplifier U11 is connected to the non-inverting input terminal of the twelfth operational amplifier U12. The inverting input terminal of the second operational amplifier U12 is connected to the output terminal of the twelfth operational amplifier U12 , and the output terminal of the twelfth operational amplifier U12 is connected to the third port of the processing chip 330 . The third follower circuit 3203 transmits a third DC pulse voltage as shown by the DC pulse voltage 4d to the processing chip 330 .

In a possible implementation manner, the ninth operational amplifier U9 , the tenth operational amplifier U10 , the eleventh operational amplifier U11 and the twelfth operational amplifier U12 may be integrated on an integrated operational amplifier chip.

The third current sampling circuit 320 may further include a thirty-eighth resistor R38 and a third capacitor C3. One end of the thirty-eighth resistor R38 is connected to the output of the twelfth operational amplifier U12 in the third follower circuit 3203. The other end of the thirty-eighth resistor R38 is connected to one end of the third capacitor C3 and the third port of the processing chip 330, and the other end of the third capacitor C3 is connected to the ground. The thirty-eighth resistor R38 and the third capacitor C3 form an RC low-pass filter circuit to prevent high-frequency signals from interfering with the processing chip 330.

In this embodiment, the first sampling resistor 300 is connected in series with the first wire, and the first isolation amplifier circuit 3012 obtains the voltage across the first sampling resistor 300 and converts the voltage across the first sampling resistor 300 The voltage is isolated and amplified, and transmitted to the first differential operational amplifier circuit 3013 to obtain a first sampled voltage. The first rectifier circuit 3011 converts the first sampled voltage into a first DC pulsating voltage. The processing The chip 330 collects the first DC pulsating voltage in real time, and obtains the current of the first wire according to the first DC pulsating voltage and the resistance value of the first sampling resistor 300; similarly, the second sampling resistor 310 connected in series with the second wire, the second isolation amplifier 3112 circuit obtains the voltage across the second sampling resistor 310, isolates and amplifies the voltage across the second sampling resistor 310, and transmits it to the second sampling resistor 310. The second sampled voltage is obtained in the differential operational amplifier circuit 3113, the second rectifier circuit 3111 converts the second sampled voltage into a second DC pulsating voltage, and the processing chip 330 collects the second DC pulsating voltage in real time, according to The second DC pulsating voltage and the resistance value of the second sampling resistor 310 obtain the current of the second wire; the arithmetic circuit 3201 in the third current sampling circuit 320 obtains the first sampling voltage and the The second sampling voltage is added, and the first sampling voltage and the second sampling voltage are added to obtain a third sampling voltage, and the third sampling voltage is transmitted to the third rectifier circuit 3202, and the third sampling voltage is The third rectifier circuit 3202 converts the third sampled voltage into a third DC pulsating voltage, and transmits it to the processing chip 330 . The processing chip 330 collects the third DC pulsating voltage in real time, according to the third DC pulsating voltage The voltage and the resistance value of the first sampling resistor 300 obtain the current of the third wire. In this embodiment, two resistors are connected in series in any two-phase wire, the current of any two-phase wire is sampled, and the current of the remaining one phase is obtained by using the arithmetic circuit, so as to realize the current sampling of the three-phase three-wire system, and the response time Short and low production cost.

Based on the three-phase three-wire current sampling circuit described above in conjunction with FIG. 1 , an embodiment of the present application further provides a three-phase three-wire current sampling method. Referring to FIG. 5 , FIG. 5 is a three-phase three-wire current sampling method provided by an embodiment of the present application. A schematic flowchart of the three-wire current sampling method is shown in Figure 5. The specific execution steps are as follows:

S500. The first current sampling circuit acquires the voltage across the first sampling resistor to obtain a first sampling voltage, and the first rectifier circuit converts the first sampling voltage into a first DC pulsating voltage, and converts the first DC The pulsating voltage is transmitted to the processing chip.

Specifically, the current of the first wire flows through the first sampling resistor, forming a voltage drop across the resistor, and the first current sampling circuit obtains the voltage across the first sampling resistor to obtain the first sampling voltage , the first sampling voltage reflects the current of the first wire. The first sampling voltage is an AC voltage. The first rectifier circuit converts the first sampled voltage into a first DC pulsating voltage, and transmits the first DC pulsating voltage to the processing chip.

S501. The second current sampling circuit acquires the voltage across the second sampling resistor to obtain a second sampling voltage, and the second rectifier circuit converts the second sampling voltage into a second DC pulsating voltage, and converts the second DC pulsating voltage transmitted to the processing chip.

Specifically, the current of the second wire flows through the second sampling resistor, forming a voltage drop across the resistor, and the second current sampling circuit obtains the voltage across the second sampling resistor to obtain the second sampling voltage , the second sampling voltage reflects the current of the second wire. The second sampling voltage is an AC voltage. The second rectifier circuit converts the second sampled voltage into a second DC pulsating voltage, and transmits the second DC pulsating voltage to the processing chip.

S502. The arithmetic circuit adds the first sampled voltage and the second sampled voltage to obtain a third sampled voltage, and a third rectifier circuit converts the third sampled voltage into a third DC pulsating voltage, and converts the The third DC pulsating voltage is transmitted to the processing chip.

S503. The processing chip acquires the first DC ripple voltage, the second DC ripple voltage, and the third DC ripple voltage, and determines the first DC ripple voltage and the first sampling resistor according to the first DC ripple voltage and the first sampling resistor. The current of the first wire, the current of the second wire is determined according to the second DC pulsating voltage and the second sampling resistor, and the current of the second wire is determined according to the third DC pulsating voltage and the resistance value of the first sampling resistor the current of the third wire.

Specifically, the digital-to-analog conversion module in the processing chip collects in real time the voltage signals output from the first current sampling circuit, the second current sampling circuit and the third current sampling circuit, including the first current sampling circuit. A ripple voltage, a second DC ripple voltage, and a third DC ripple voltage are flowed. The arithmetic module in the processing chip obtains the current of the first sampling resistor according to the first DC pulsating voltage and the resistance value of the first sampling resistor, and the first sampling resistor is connected in series with the first sampling resistor. In the wire, according to the equal current in the series circuit, it can be known that the current of the first sampling resistor is the current of the first wire; similarly, the arithmetic module in the processing chip is based on the second DC pulsating voltage and all The resistance value of the second sampling resistor obtains the current of the second sampling resistor, and the second sampling resistor is connected in series with the second wire, and the current of the second sampling resistor is the current of the second wire The digital-to-analog conversion module in the processing chip can collect the third DC pulsating voltage in real time, and the arithmetic module in the processing chip obtains the third DC pulsating voltage and the resistance value of the first sampling resistor according to the the current in the third wire. Exemplarily, the first DC pulsating voltage collected in real time by the processing chip is U _a , the second DC pulsating voltage is U _b , and the third DC pulsating voltage is U _c , where U _a =I _a ×R, U _b =I _b ×R, U _c =I _c ×R, then the first wire current I _a =U _a /R, the second wire current I _b =U _b /R, the The third wire current I _c =U _c /R.

It should be noted that the processing chip includes a plurality of ports, and the ports through which the first DC pulsating voltage, the second DC pulsating voltage and the third DC pulsating voltage are transmitted to the processing chip are different, so that the The collection accuracy of the first DC pulsating voltage, the second DC pulsating voltage and the third DC pulsating voltage is guaranteed. It can be obtained from this that the processing chip determines the current of the first wire according to the first DC ripple voltage and the first sampling resistor, and determines the current of the first wire according to the second DC ripple voltage and the second sampling resistor For the current of the second wire, the current of the third wire is determined according to the third DC pulsating voltage and the resistance value of the first sampling resistor.

Implementing this embodiment, resistors can be used to sample the current of any two phases in the three-phase three-wire system, and then the current of the remaining one phase can be obtained according to the current sampling circuit, so as to realize the sampling of the current of the three-phase three-wire system and reduce the production cost. .

It should be noted that the above-mentioned terms "first" and "second" are only used for descriptive purposes, and should not be construed as indicating or implying relative importance. It can be understood that the examples corresponding to FIG. 3 and FIG. 4 are only used to explain the embodiments of the present application and should not be construed as limitations. In an optional manner, FIG. 3 and FIG. 4 may also have other implementation manners. The operational amplifier is integrated into an operational amplifier integrated chip, and the waveform schematic diagram of FIG. 4 is subjected to inverting input processing, etc., which are not listed here.

Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be implemented by instructing relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium. During execution, the processes of the embodiments of the above-mentioned methods may be included. The storage medium may be a magnetic disk, an optical disk, a read-only memory (Read-Only Memory, ROM), or a random access memory (Random Access Memory, RAM) or the like.

The above disclosures are only the preferred embodiments of the present application, and of course, the scope of the rights of the present application cannot be limited by this. Therefore, equivalent changes made according to the claims of the present application are still within the scope of the present application.

Claims (10)

1. A three-phase three-wire current sampling circuit, characterized in that the three-phase three-wire current sampling circuit comprises a first sampling resistor, a first current sampling circuit, a second sampling resistor, a second current sampling circuit, and a third current sampling circuit The circuit and the processing chip, the three wires include a first wire, a second wire and a third wire, wherein:

   The first sampling resistor is connected in series with the first wire, the first current sampling circuit includes a first rectifier circuit, the input end of the first rectifier circuit is connected to the first sampling resistor, the first The output end of the rectifier circuit is connected with the processing chip;

   The second sampling resistor is connected in series with the second wire, the second current sampling circuit includes a second rectifier circuit, the input end of the second rectifier circuit is connected to the second sampling resistor, the second The output end of the rectifier circuit is connected to the processing chip, wherein the resistance value of the first sampling resistor is the same as the resistance value of the second sampling resistor;

   The third current sampling circuit includes an arithmetic circuit and a third rectifier circuit. The input end of the arithmetic circuit is respectively connected to the input end of the first rectifier circuit and the input end of the second rectifier circuit. The arithmetic circuit The output end of the third rectifier circuit is connected to the input end of the third rectifier circuit, and the output end of the third rectifier circuit is connected to the processing chip.
2. The three-phase three-wire current sampling circuit according to claim 1, wherein the first current sampling circuit further comprises a first isolation amplifier circuit;

   The input end of the first isolation amplifier circuit is connected to both ends of the first sampling resistor.
3. The three-phase three-wire current sampling circuit according to claim 2, wherein the first current sampling circuit further comprises a first differential amplifier circuit;

   The input end of the first differential amplifier circuit is connected to the output end of the first isolation amplifier circuit, and the output end of the first differential amplifier circuit is connected to the input end of the first rectifier circuit.
4. The three-phase three-wire current sampling circuit according to claim 1, wherein the first current sampling circuit further comprises a first follower circuit;

   The input end of the first follower circuit is connected to the output end of the first rectifier circuit, and the output end of the first follower circuit is connected to the first port of the processing chip.
5. The three-phase three-wire current sampling circuit according to claim 1, wherein the second current sampling circuit further comprises a second isolation amplifier circuit;

   The input end of the second isolation amplifier circuit is connected to both ends of the second sampling resistor.
6. The three-phase three-wire current sampling circuit according to claim 5, wherein the second current sampling circuit further comprises a second differential amplifier circuit;

   The input terminal of the second differential amplifier circuit is connected to the output terminal of the second isolation amplifier circuit, and the output terminal of the second differential amplifier circuit is connected to the input terminal of the second rectifier circuit.
7. The three-phase three-wire current sampling circuit according to claim 1, wherein the second current sampling circuit further comprises a second follower circuit;

   The input end of the second follower circuit is connected to the output end of the second rectifier circuit, and the output end of the second follower circuit is connected to the second port of the processing chip.
8. The three-phase three-wire current sampling circuit according to claim 1, wherein the input terminal of the first rectifier circuit and the input terminal of the second rectifier circuit are connected to the non-inverting input terminal of the arithmetic circuit, and the The direction of the voltage output by the operation circuit is opposite to the direction of the current of the third wire;

   Or, the input end of the first rectifier circuit and the input end of the second rectifier circuit are connected to the inverting input end of the operation circuit, and the voltage direction output by the operation circuit is the same as the current direction of the third wire same.
9. The three-phase three-wire current sampling circuit according to claim 1, wherein the third current sampling circuit further comprises a third follower circuit;

   The input end of the third follower circuit is connected to the output end of the third rectifier circuit, and the output end of the third follower circuit is connected to the third port of the processing chip.
10. A three-phase three-wire current sampling method, characterized in that, based on the realization of the three-phase three-wire current sampling circuit according to any one of claims 1-9, the method comprises:

    The first current sampling circuit obtains the voltage across the first sampling resistor to obtain the first sampling voltage, the first rectifier circuit converts the first sampling voltage into a first DC pulsating voltage, and converts the first DC pulsating voltage transmitted to the processing chip;

    The second current sampling circuit obtains the voltage across the second sampling resistor to obtain the second sampling voltage, the second rectifier circuit converts the second sampling voltage into a second DC pulsating voltage, and transmits the second DC pulsating voltage to the processing chip;

    The arithmetic circuit adds the first sampled voltage and the second sampled voltage to obtain a third sampled voltage, and a third rectifier circuit converts the third sampled voltage into a third DC pulsating voltage, and converts the third sampled voltage into a third DC pulsating voltage. Three DC pulsating voltages are transmitted to the processing chip;

    The processing chip acquires the first DC ripple voltage, the second DC ripple voltage and the third DC ripple voltage, and determines the first DC ripple voltage according to the first DC ripple voltage and the first sampling resistor. The current of a wire, the current of the second wire is determined according to the second DC pulsating voltage and the second sampling resistor, and the current of the second wire is determined according to the third DC pulsating voltage and the resistance value of the first sampling resistor The current of the third wire.

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