CN109946540B - Detection circuit and detection method of sine and cosine resolver - Google Patents
Detection circuit and detection method of sine and cosine resolver Download PDFInfo
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- CN109946540B CN109946540B CN201910219251.1A CN201910219251A CN109946540B CN 109946540 B CN109946540 B CN 109946540B CN 201910219251 A CN201910219251 A CN 201910219251A CN 109946540 B CN109946540 B CN 109946540B
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Abstract
The embodiment of the invention provides a detection circuit and a detection method of a sine-cosine resolver, wherein the detection circuit comprises: the precise full-wave rectification summing circuit is used for receiving the output signals of the sine and cosine rotary transformer, respectively rectifying sine signals and cosine signals in the output signals of the sine and cosine rotary transformer into sine half-cycle steamed bread waves and cosine half-cycle steamed bread waves, and summing the sine half-cycle steamed bread waves and the cosine half-cycle steamed bread waves; and the filter circuit is connected with the output of the precise full-wave rectification summing circuit and is used for filtering the alternating current analog signal output by the precise full-wave rectification summing circuit into a direct current analog signal. Therefore, the complexity of the detection circuit of the sine-cosine resolver is reduced.
Description
Technical Field
The invention relates to the technical field of detection, in particular to a detection circuit and a detection method of a sine-cosine resolver.
Background
The sine-cosine resolver is a transformer capable of converting a rotation angle into an electric signal according to a sine function relationship and a cosine function relationship and outputting the electric signal, and is widely applied to an automatic control system, so that it is important to detect whether the sine-cosine resolver fails or not.
Two groups of alternating current differential signals are output by the sine and cosine resolver, the alternating current differential signals comprise sine signals and cosine signals, and the envelope of the sine signals and the envelope of the cosine signals are in an orthogonal characteristic. The detection circuit of sine-cosine resolver in the prior art is based on' SIN2+COS2The method comprises the steps of 1' respectively filtering sine signals and cosine signals, extracting envelopes of the sine signals and the cosine signals through filtering, then respectively carrying out square operation on the envelopes of the sine signals and the cosine signals by using a multiplier chip, building a summing circuit by using operational amplifiers, summing input summing circuits of the sine signals and the cosine signals after the square operation to obtain direct-current analog signals, and if the amplitude change of the direct-current analog signals is within a preset range, enabling a sine-cosine resolver to have no fault, otherwise, enabling the sine-cosine resolver to have the fault.
In the prior art, when the detection circuit of the sine and cosine resolver needs to use a multiplier chip to perform square operation on sine signals and cosine signals respectively, the complexity of the internal circuit of the multiplier chip is high, so that the complexity of the detection circuit of the sine and cosine resolver in the prior art is high.
Disclosure of Invention
The embodiment of the invention aims to provide a detection circuit and a detection method of a sine-cosine resolver, which are used for detecting whether the sine-cosine resolver fails or not. The specific technical scheme is as follows:
in a first aspect, an embodiment of the present invention provides a detection circuit for a sine-cosine resolver, including: a precise full-wave rectification summing circuit and a filter circuit,
the precise full-wave rectification summing circuit is used for receiving the output signals of the sine and cosine rotary transformer, respectively rectifying sine signals and cosine signals in the output signals of the sine and cosine rotary transformer into sine half-cycle steamed bread waves and cosine half-cycle steamed bread waves, and summing the sine half-cycle steamed bread waves and the cosine half-cycle steamed bread waves to obtain alternating current analog signals;
and the filter circuit is connected with the output of the precise full-wave rectification summing circuit and is used for filtering the alternating current analog signal output by the precise full-wave rectification summing circuit into a direct current analog signal.
The precise full-wave rectification summing circuit provided by the embodiment of the first aspect of the invention comprises:
a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first operational amplifier N1B, a first diode V1, a second diode V2, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a second operational amplifier N1C, a third diode V3, a fourth diode V4, an eleventh resistor R11, a twelfth resistor R12, and a third operational amplifier N1A;
wherein, the first end of the first resistor R1 is connected to the output of the sine-cosine resolver to receive the sine signal of the sine-cosine resolver output signal, the first end of the first resistor R1 is further connected to the first end of the fourth resistor R4, the second end of the first resistor R1 is connected to the first end of the third resistor R3, the cathode of the first diode V1 and the reverse input end of the first operational amplifier N1B, the first end of the second resistor R2 is connected to the analog power ground, the second end of the second resistor R2 is connected to the same-direction input end of the first operational amplifier N1B, the second end of the third resistor R3 is connected to the anode of the second diode V2 and the first end of the fifth resistor R5, the anodes of the first diode V1 are connected to the output end of the first operational amplifier N1B and the cathode of the second diode V2, the positive end of the first operational amplifier N1B is connected to the positive end of the power supply, the negative end of the first operational amplifier N1 is connected to the negative end of the power supply N1B, a second end of the fifth resistor R5 is connected to a second end of the fourth resistor R4, a second end of the ninth resistor R9, a second end of the tenth resistor R10, a first end of the twelfth resistor R12, and an inverting input terminal of the third operational amplifier N1A, respectively;
a first end of the sixth resistor R6 is connected to an output end of the sine-cosine resolver to receive a cosine signal of an output signal of the sine-cosine resolver, a first end of the sixth resistor R6 is further connected to a first end of the ninth resistor R9, a second end of the sixth resistor R6 is connected to a first end of the eighth resistor R8, the negative electrode of the third diode V3 is connected with the reverse input end of the second operational amplifier N1C, the first end of the seventh resistor R7 is connected with the analog power ground, the second end of the seventh resistor R7 is connected with the same-direction input end of the second operational amplifier N1C, the second end of the eighth resistor R8 is connected with the positive electrode of the fourth diode V4 and the first end of the tenth resistor R10, the positive electrode of the third diode V3 is connected with the output end of the second operational amplifier N1C and the negative electrode of the fourth diode V4, the positive end of the second operational amplifier N1C is connected with the positive end of the power supply, and the negative end of the second operational amplifier N1C is connected with the negative end of the power supply;
the first end of an eleventh resistor R11 is connected with the analog power ground, the second end of an eleventh resistor R11 is connected with the equidirectional input end of a third operational amplifier N1A, the second end of a twelfth resistor R12 is connected with the output end of a third operational amplifier N1A, the positive end of the third operational amplifier N1A is connected with the positive end of a power supply, the negative end of the third operational amplifier N1A is connected with the negative end of the power supply, the output end of the third operational amplifier N1A is connected with a filter circuit, and the output end of the third operational amplifier N1A outputs an alternating current analog signal and inputs the alternating current analog signal to the filter circuit.
An embodiment of a first aspect of the present invention provides a filter circuit, including:
a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a fourth operational amplifier N1D, a first capacitor C1 and a second capacitor C2,
wherein, a first end of a fourteenth resistor R14 is connected to the output end of the third operational amplifier N1A, a first end of a fourteenth resistor R14 receives the ac analog signal output by the output end of the third operational amplifier N1A, a first end of a thirteenth resistor R13 is connected to the analog power ground, a second end of a thirteenth resistor R13 is connected to the inverting input end of the fourth operational amplifier N1D and the first end of a fifteenth resistor R15, respectively, a first end of a fourteenth resistor R14 is further connected to the second end of a twelfth resistor R12 and the first end of a first capacitor C1, respectively, a second end of a fourteenth resistor R14 is connected to the non-inverting input end of the fourth operational amplifier N1D and the first end of a second capacitor C2, a second end of the second capacitor C2 is connected to the analog power ground, a second end of a fifteenth resistor R15 is connected to the second end of a first capacitor C1, the first end of a sixteenth resistor R16 and the output end of the fourth operational amplifier N1D, a second end of the sixteenth resistor R16 outputs a dc analog signal.
In the embodiment of the present invention, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a fourth operational amplifier N1D, a first capacitor C1, and a second capacitor C2 collectively form a filter circuit, and the filter circuit in the embodiment of the present invention may adopt, but is not limited to, a second-order butterworth filter to filter an ac analog signal.
The precise full-wave rectification summing circuit adopted by the embodiment of the invention is a general circuit, the calculation is simple, the types of matching resistors are less, the gain adjustable range is larger than 1 or smaller than 1, and the application range is wider. The filter circuit in the embodiment of the invention has independent functions and flexible parameter adjustment, improves the precision of filtering the alternating current analog signal, and simultaneously optimizes the time domain and frequency characteristics of the alternating current analog signal.
In a second aspect, a method for detecting a sine-cosine resolver provided in an embodiment of the present invention is applied to a detection circuit of a sine-cosine resolver in the first aspect, and includes:
receiving an output signal of a sine-cosine resolver, rectifying a sine signal and a cosine signal in the output signal of the sine-cosine resolver into a sine half-cycle steamed bread wave and a cosine half-cycle steamed bread wave respectively, and summing the sine half-cycle steamed bread wave and the cosine half-cycle steamed bread wave to obtain an alternating current analog signal;
the output signal of the sine-cosine resolver is an alternating current differential signal, and before the sine signal and the cosine signal in the output signal of the sine-cosine resolver are rectified, a differential-to-single-ended circuit is needed to convert the alternating current differential signal into single-ended signals of the sine signal and the cosine signal respectively.
Filtering the alternating current analog signal into a direct current analog signal;
the maximum amplitude of the alternating current analog signal is the sum of the amplitude of the sine positive half-cycle steamed bread wave and the amplitude of the cosine positive half-cycle steamed bread wave at the intersection;
the minimum amplitude of the alternating current analog signal is the sum of the amplitude of the sine positive half-cycle steamed bread wave and the amplitude of the cosine positive half-cycle steamed bread wave at the zero point, and the amplitude of the sine positive half-cycle steamed bread wave and the amplitude of the cosine positive half-cycle steamed bread wave.
In the detection circuit of the sine-cosine resolver provided by the embodiment of the invention, the precise full-wave rectification summing circuit is used for receiving the output signal of the sine-cosine resolver, respectively rectifying the sine signal and the cosine signal in the output signal of the sine-cosine resolver into a sine half-cycle steamed bread wave and a cosine half-cycle steamed bread wave, and summing the sine half-cycle steamed bread wave and the cosine half-cycle steamed bread wave; and the filter circuit is connected with the output of the precise full-wave rectification summing circuit and is used for filtering the alternating current analog signal output by the precise full-wave rectification summing circuit into a direct current analog signal. Compared with the prior art that the multiplier chip is used for performing square operation on the envelopes of sine signals and cosine signals respectively, the detection circuit in the embodiment does not need square summation operation, and compared with the multiplier chip, the detection circuit is simple in structure and directly obtains direct-current analog signals, so that whether faults exist in the sine-cosine resolver or not is determined. Therefore, the complexity of the detection circuit of the sine-cosine resolver is reduced.
According to the detection method of the sine and cosine resolver, alternating current analog signals output by a precise full-wave rectification summing circuit are input to a filter circuit, and direct current analog signals are obtained through the filter circuit; and determining whether the sine and cosine resolver has faults or not through the amplitude of the direct current analog signal. Compared with the prior art, the embodiment of the invention has the advantages that the square summation operation is not needed, the calculation process is simple, the amplitude variation range of the summation signal output by the summation circuit is smaller, the direct-current analog signal is finally obtained, and the existence of the fault of the sine-cosine resolver is detected according to whether the amplitude of the direct-current analog signal is in the preset normal range or not. Therefore, the efficiency of detecting whether the sine-cosine resolver has a fault can be improved.
Of course, not all of the advantages described above need to be achieved at the same time in the practice of any one product or method of the invention.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below.
Fig. 1 is a schematic structural diagram of a detection circuit of a sine-cosine resolver according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a precise full-wave rectification summing circuit according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a filter circuit according to an embodiment of the present invention;
fig. 4 is a flowchart of a detection method of a sine-cosine resolver according to an embodiment of the present invention.
Description of reference numerals:
11-precision full-wave rectification summing circuit; 12-a filter circuit; r1 — first resistance; r2 second resistance; r3 — third resistance; r4-fourth resistor; r5-fifth resistor; N1B — first operational amplifier; v1 — first diode; v2 — second diode; r6-sixth resistance; r7 — seventh resistor; r8 — eighth resistance; r9 — ninth resistor; r10 — tenth resistance; N1C — second operational amplifier; v3 — third diode; v4 — fourth diode; r11 — eleventh resistor; r12 — twelfth resistor; N1A-third operational amplifier.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1, an embodiment of the present invention provides a detection circuit for a sine-cosine resolver, including: a precision full-wave rectification summing circuit 11 and a filter circuit 12,
the precise full-wave rectification summing circuit 11 is used for receiving an output signal of the sine-cosine resolver, respectively rectifying a sine signal and a cosine signal in the output signal of the sine-cosine resolver into a sine positive half-cycle steamed bread wave and a cosine positive half-cycle steamed bread wave, and summing the sine positive half-cycle steamed bread wave and the cosine positive half-cycle steamed bread wave to obtain an alternating current analog signal;
and the filter circuit 12 is connected with the output of the precision full-wave rectification summing circuit 11 and is used for filtering the alternating current analog signal output by the precision full-wave rectification summing circuit 11 into a direct current analog signal.
The detection circuit of the sine-cosine resolver provided by the embodiment of the invention can be applied to a detector to realize fault detection of the sine-cosine resolver.
Referring to fig. 1, as shown in fig. 2, a precision full-wave rectification summing circuit 11 according to an embodiment of the present invention includes:
a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first operational amplifier N1B, a first diode V1, a second diode V2, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a second operational amplifier N1C, a third diode V3, a fourth diode V4, an eleventh resistor R11, a twelfth resistor R12, and a third operational amplifier N1A;
wherein, the first end of the first resistor R1 is connected to the output of the sine-cosine resolver to receive the sine signal of the sine-cosine resolver output signal, the first end of the first resistor R1 is further connected to the first end of the fourth resistor R4, the second end of the first resistor R1 is connected to the first end of the third resistor R3, the cathode of the first diode V1 and the reverse input end of the first operational amplifier N1B, the first end of the second resistor R2 is connected to the analog power ground, the second end of the second resistor R2 is connected to the same-direction input end of the first operational amplifier N1B, the second end of the third resistor R3 is connected to the anode of the second diode V2 and the first end of the fifth resistor R5, the anodes of the first diode V1 are connected to the output end of the first operational amplifier N1B and the cathode of the second diode V2, the positive end of the first operational amplifier N1B is connected to the positive end of the power supply, the negative end of the first operational amplifier N1 is connected to the negative end of the power supply N1B, a second end of the fifth resistor R5 is connected to a second end of the fourth resistor R4, a second end of the ninth resistor R9, a second end of the tenth resistor R10, a first end of the twelfth resistor R12, and an inverting input terminal of the third operational amplifier N1A, respectively;
a first end of the sixth resistor R6 is connected to an output end of the sine-cosine resolver to receive a cosine signal of an output signal of the sine-cosine resolver, a first end of the sixth resistor R6 is further connected to a first end of the ninth resistor R9, a second end of the sixth resistor R6 is connected to a first end of the eighth resistor R8, the negative electrode of the third diode V3 is connected with the reverse input end of the second operational amplifier N1C, the first end of the seventh resistor R7 is connected with the analog power ground, the second end of the seventh resistor R7 is connected with the same-direction input end of the second operational amplifier N1C, the second end of the eighth resistor R8 is connected with the positive electrode of the fourth diode V4 and the first end of the tenth resistor R10, the positive electrode of the third diode V3 is connected with the output end of the second operational amplifier N1C and the negative electrode of the fourth diode V4, the positive end of the second operational amplifier N1C is connected with the positive end of the power supply, and the negative end of the second operational amplifier N1C is connected with the negative end of the power supply;
the first end of an eleventh resistor R11 is connected with the analog power ground, the second end of an eleventh resistor R11 is connected with the equidirectional input end of a third operational amplifier N1A, the second end of a twelfth resistor R12 is connected with the output end of a third operational amplifier N1A, the positive end of the third operational amplifier N1A is connected with the positive end of a power supply, the negative end of the third operational amplifier N1A is connected with the negative end of the power supply, the output end of the third operational amplifier N1A is connected with a filter circuit, and the output end of the third operational amplifier N1A outputs an alternating current analog signal and inputs the alternating current analog signal to the filter circuit.
Referring to the region surrounded by the dotted line B in fig. 2, when the sine signal SIN in the output signal of the sine-cosine resolver is greater than 0, the output end of the first operational amplifier N1B outputs a low level, the first diode V1 is turned off, the second diode V2 is turned on, and the first resistor R1, the third resistor R3 and the first operational amplifier N1B form an amplifier with an amplification factor of-1; the third operational amplifier N1A, the twelfth resistor R12, the fifth resistor R5 and the fourth resistor R4 constitute an inverse adder, after the output signal of the first operational amplifier N1B passes through the fifth resistor R5 and the twelfth resistor R12, the output signal at the output end of the third operational amplifier N1A is a sinusoidal signal 2 SIN; after the sinusoidal signal SIN passes through the fourth resistor R4 and the twelfth resistor R12, the output signal at the output terminal of the third operational amplifier N1A is-SIN, and according to the superposition principle, the output signal at the output terminal of the third operational amplifier N1A is 2SIN + (-SIN) ═ SIN. When the sine signal SIN in the output signals of the sine-cosine resolver is less than 0, the output end of the first operational amplifier N1B outputs high level, the first diode V1 is turned on, the second diode V2 is turned off according to the virtual short, the first end of the R3 and the second end of the R5 are both equivalent to "ground", and the potentials are equal, so no current flows through the third resistor R3 and the fifth resistor R5, and the current is not considered. At this time, the fourth resistor R4, the twelfth resistor R12 and the third operational amplifier N1A constitute an amplifier with an amplification factor of-1, and the output of the output end of the third operational amplifier N1A is-SIN, so that the effects of keeping the amplitude of the positive half cycle of the sinusoidal signal unchanged and turning the amplitude of the negative half cycle are realized, and the sinusoidal signal is rectified into a sinusoidal head wave of the positive half cycle.
Referring to the region surrounded by the dotted line a in fig. 2, when the cosine signal COS in the output signal of the sine-cosine resolver is greater than 0, the output terminal of the second operational amplifier N1C outputs a low level, the third diode V3 is turned off, and the fourth diode V4 is turned on; the sixth resistor R6, the eighth resistor R8 and the second operational amplifier N1C form an amplifier with the amplification factor of-1; the third operational amplifier N1A, the twelfth resistor R12, the tenth resistor R10, and the ninth resistor R9 constitute an inverse adder. After the output signal of the second operational amplifier N1C passes through the tenth resistor R10 and the twelfth resistor R12, the output signal of the output terminal of the third operational amplifier N1A is 2 COS; after the cosine signal COS passes through the ninth resistor R9 and the twelfth resistor R12, the output signal of the third operational amplifier N1A is the cosine signal-COS, and according to the superposition principle, the output signal of the output terminal of the third operational amplifier N1A is 2COS + (-COS) ═ COS; when the cosine signal COS in the output signal of the sine-cosine resolver is less than 0, the output terminal of the second operational amplifier N1C outputs a high level, the third diode V3 is turned on, the fourth diode V4 is turned off, and according to the virtual short, the first terminal of the eighth resistor R8 and the second terminal of the tenth resistor R10 are both equivalent to "ground", and the potentials are equal, so that no current flows through the eighth resistor R8 and the tenth resistor R10, and therefore the current is not considered. At this time, the ninth resistor R9, the twelfth resistor R12 and the third operational amplifier N1A constitute an amplifier with an amplification factor of-1, and the output signal of the output end of the third operational amplifier N1A is a cosine signal-COS, so that the effects of keeping the amplitude of the positive half cycle of the cosine signal unchanged and turning the amplitude of the negative half cycle are realized according to the above analysis, and the cosine signal is rectified into a steamed bread wave of the cosine positive half cycle.
Referring to the area surrounded by the dotted line C in fig. 3, the positive half-cycle sine steamed bun waves and the positive half-cycle cosine steamed bun waves output from the output end of the third operational amplifier N1A are fed back by the twelfth resistor and input to the inverting input end of the third operational amplifier N1A for summation, and the output end of the third operational amplifier N1A outputs an alternating current analog signal, which is a signal obtained by summing the positive half-cycle sine steamed bun waves and the positive half-cycle cosine steamed bun waves.
Referring to fig. 1 and 2, as shown in fig. 3, a filter circuit 12 according to an embodiment of the present invention includes:
a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a fourth operational amplifier N1D, a first capacitor C1 and a second capacitor C2,
wherein, a first end of a fourteenth resistor R14 is connected to the output end of the third operational amplifier N1A, a first end of a fourteenth resistor R14 receives the ac analog signal output by the output end of the third operational amplifier N1A, a first end of a thirteenth resistor R13 is connected to the analog power ground, a second end of a thirteenth resistor R13 is connected to the inverting input end of the fourth operational amplifier N1D and the first end of a fifteenth resistor R15, respectively, a first end of a fourteenth resistor R14 is further connected to the second end of a twelfth resistor R12 and the first end of a first capacitor C1, respectively, a second end of a fourteenth resistor R14 is connected to the non-inverting input end of the fourth operational amplifier N1D and the first end of a second capacitor C2, a second end of the second capacitor C2 is connected to the analog power ground, a second end of a fifteenth resistor R15 is connected to the second end of a first capacitor C1, the first end of a sixteenth resistor R16 and the output end of the fourth operational amplifier N1D, a second end of the sixteenth resistor R16 outputs a dc analog signal.
In the embodiment of the present invention, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a fourth operational amplifier N1D, a first capacitor C1, and a second capacitor C2 collectively form a filter circuit, and the filter circuit in the embodiment of the present invention may adopt, but is not limited to, a second-order butterworth filter to filter an ac analog signal.
The precise full-wave rectification summing circuit adopted by the embodiment of the invention is a general circuit, the calculation is simple, the types of matching resistors are less, the gain adjustable range is larger than 1 or smaller than 1, and the application range is wider. The filter circuit in the embodiment of the invention has independent functions and flexible parameter adjustment, improves the precision of filtering the alternating current analog signal, and simultaneously optimizes the time domain and frequency characteristics of the alternating current analog signal.
As shown in fig. 4, a method for detecting a sine-cosine resolver according to an embodiment of the present invention is applied to a detection circuit of a sine-cosine resolver in fig. 1 to 3, and includes:
s401, receiving an output signal of a sine and cosine resolver, rectifying a sine signal and a cosine signal in the output signal of the sine and cosine resolver into a sine half-cycle steamed bread wave and a cosine half-cycle steamed bread wave respectively, and summing the sine half-cycle steamed bread wave and the cosine half-cycle steamed bread wave to obtain an alternating current analog signal;
the output signal of the sine-cosine resolver is an alternating current differential signal, and before the sine signal and the cosine signal in the output signal of the sine-cosine resolver are rectified, a differential-to-single-ended circuit is needed to convert the alternating current differential signal into single-ended signals of the sine signal and the cosine signal respectively.
S402, filtering the alternating current analog signal into a direct current analog signal;
the maximum amplitude of the alternating current analog signal is the sum of the amplitude of the sine positive half-cycle steamed bread wave and the amplitude of the cosine positive half-cycle steamed bread wave at the intersection;
the minimum amplitude of the alternating current analog signal is the sum of the amplitude of the sine positive half-cycle steamed bread wave and the amplitude of the cosine positive half-cycle steamed bread wave at the zero point, and the amplitude of the sine positive half-cycle steamed bread wave and the amplitude of the cosine positive half-cycle steamed bread wave.
It is understood that the filtering circuit of the embodiment of the present invention may be, but is not limited to, a second-order butterworth filter, and the butterworth filter is characterized in that the frequency response curve in the pass band is flat to the maximum extent, has no fluctuation, and gradually drops to zero in the stop band. On the bode plot of the logarithm of the amplitude against the angular frequency, starting from a certain boundary angular frequency, the amplitude decreases gradually with increasing angular frequency, tending to minus infinity. And filtering the alternating current analog signal to obtain a direct current analog signal, wherein the maximum amplitude and the minimum amplitude of the direct current analog signal respectively correspond to the maximum amplitude and the minimum amplitude of the alternating current analog signal.
Because the multiplier chip is used for carrying out square operation on the envelopes of the sine signal and the cosine signal respectively, the amplitude range of the obtained alternating current analog signal is large. According to the embodiment of the invention, square operation is not needed in the process of obtaining the alternating current analog signal, and the amplitude range of the alternating current analog signal is smaller, so that the alternating current analog signal is obtained without complex operation, and the efficiency of obtaining the alternating current analog signal is higher.
And S403, determining whether the sine and cosine resolver has faults or not according to the amplitude range of the direct current analog signal.
In practical situations, the range of the amplitude of the dc analog signal may vary according to the size of the resistor and the capacitor in the filter circuit. In the test, the amplitude range of the dc analog signal may be, but is not limited to, 5V ± 0.2V.
According to the detection method of the sine and cosine resolver, alternating current analog signals output by a precise full-wave rectification summing circuit are input to a filter circuit, and direct current analog signals are obtained through the filter circuit; and determining whether the sine and cosine resolver has faults or not through the amplitude of the direct current analog signal. Compared with the prior art, the embodiment of the invention has the advantages that before the output signal of the sine-cosine resolver is reversely rectified, the envelope of the output signal is not required to be extracted, the square summation operation is also not required, the calculation process is simple, the amplitude variation range of the alternating current analog signal output by the precise full-wave rectification summation circuit is smaller, the envelope of the alternating current analog signal with the orthogonal envelope is extracted through the filter circuit and is in orthogonal variation, the direct current analog signal is finally obtained, and the fault of the sine-cosine resolver is detected according to whether the amplitude of the direct current analog signal is in the preset normal range or not. Therefore, the efficiency of detecting whether the sine-cosine resolver has a fault can be improved.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, as for the method embodiment, since it is applied to the apparatus embodiment, the description is relatively simple, and for the relevant points, reference may be made to the partial description of the apparatus embodiment.
The above description is only for the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention shall fall within the protection scope of the present invention.
Claims (5)
1. A detection circuit for a sine-cosine resolver, the detection circuit comprising: a precise full-wave rectification summing circuit and a filter circuit,
the precise full-wave rectification summing circuit is used for receiving an output signal of a sine-cosine rotary transformer, respectively rectifying a sine signal and a cosine signal in the output signal of the sine-cosine rotary transformer into a sine positive half-cycle steamed bread wave and a cosine positive half-cycle steamed bread wave, and summing the sine positive half-cycle steamed bread wave and the cosine positive half-cycle steamed bread wave to obtain an alternating current analog signal;
and the filter circuit is connected with the output of the precise full-wave rectification summing circuit and is used for filtering the alternating current analog signal output by the precise full-wave rectification summing circuit into a direct current analog signal.
2. The detection circuit of claim 1, wherein the precision full-wave rectification summing circuit comprises:
a first resistor (R1), a second resistor (R2), a third resistor (R3), a fourth resistor (R4), a fifth resistor (R5), a first operational amplifier (N1B), a first diode (V1), a second diode (V2), a sixth resistor (R6), a seventh resistor (R7), an eighth resistor (R8), a ninth resistor (R9), a tenth resistor (R10), a second operational amplifier (N1C), a third diode (V3), a fourth diode (V4), an eleventh resistor (R11), a twelfth resistor (R12), and a third operational amplifier (N1A);
wherein a first end of the first resistor (R1) is connected to an output of the sine-cosine resolver to receive a sine signal in an output signal of the sine-cosine resolver, a first end of the first resistor (R1) is further connected to a first end of the fourth resistor (R4), a second end of the first resistor (R1) is connected to a first end of the third resistor (R3), a cathode of the first diode (V1) and an inverting input terminal of the first operational amplifier (N1B), a first end of the second resistor (R2) is connected to an analog power ground, a second end of the second resistor (R2) is connected to a unidirectional input terminal of the first operational amplifier (N7371 3), a second end of the third resistor (R3) is connected to an anode of the second diode (V2) and a first end of the fifth resistor (R5), and a positive electrode of the first diode (V1) is connected to an output terminal of the first operational amplifier (N851) and a first output terminal of the second operational amplifier (N8536) ) The positive terminal of the first operational amplifier (N1B) is connected to the positive terminal of a power supply, the negative terminal of the first operational amplifier (N1B) is connected to the negative terminal of the power supply, and the second terminal of the fifth resistor (R5) is connected to the second terminal of the fourth resistor (R4), the second terminal of the ninth resistor (R9), the second terminal of the tenth resistor (R10), the first terminal of the twelfth resistor (R12), and the inverting input terminal of the third operational amplifier (N1A), respectively;
a first end of the sixth resistor (R6) is connected to an output end of the sine-cosine resolver to receive a cosine signal in an output signal of the sine-cosine resolver, a first end of the sixth resistor (R6) is further connected to a first end of the ninth resistor (R9), a second end of the sixth resistor (R6) is connected to a first end of the eighth resistor (R8), a negative electrode of the third diode (V3), and a reverse input end of the second operational amplifier (N1C), respectively, a first end of the seventh resistor (R7) is connected to an analog power ground, a second end of the seventh resistor (R7) is connected to a same-direction input end of the second operational amplifier (N1C), a second end of the eighth resistor (R8) is connected to a positive electrode of the fourth diode (V4) and a first end of the tenth resistor (R10), respectively, and a positive electrode of the third diode (V3) is connected to a positive electrode of the second operational amplifier (N1C) and a first end of the fourth operational amplifier (N1) (V4), the positive terminal of the second operational amplifier (N1C) being connected to the positive terminal of the power supply, the negative terminal of the second operational amplifier (N1C) being connected to the negative terminal of the power supply;
a first end of the eleventh resistor (R11) is connected to the analog power ground, a second end of the eleventh resistor (R11) is connected to a unidirectional input end of the third operational amplifier (N1A), a second end of the twelfth resistor (R12) is connected to an output end of the third operational amplifier (N1A), a positive end of the third operational amplifier (N1A) is connected to a positive end of a power supply, a negative end of the third operational amplifier (N1A) is connected to a negative end of the power supply, an output end of the third operational amplifier (N1A) is connected to the filter circuit, and an output end of the third operational amplifier (N1A) outputs the ac analog signal and inputs the ac analog signal to the filter circuit.
3. The detection circuit of claim 2, wherein the filtering circuit comprises:
a thirteenth resistor (R13), a fourteenth resistor (R14), a fifteenth resistor (R15), a sixteenth resistor (R16), a fourth operational amplifier (N1D), a first capacitor (C1) and a second capacitor (C2),
wherein a first end of the fourteenth resistor (R14) is connected to the output end of the third operational amplifier (N1A), a first end of the fourteenth resistor (R14) receives the ac analog signal output from the output end of the third operational amplifier (N1A), a first end of the thirteenth resistor (R13) is connected to the analog power ground, a second end of the thirteenth resistor (R13) is connected to the inverting input end of the fourth operational amplifier (N1D) and the first end of the fifteenth resistor (R15), a first end of the fourteenth resistor (R14) is further connected to the second end of the twelfth resistor (R12) and the first end of the first capacitor (C1), and a second end of the fourteenth resistor (R14) is connected to the non-inverting input end of the fourth operational amplifier (N1D) and the first end of the second capacitor (C2), a second end of the second capacitor (C2) is connected to the analog power ground, a second end of the fifteenth resistor (R15) is connected to the second end of the first capacitor (C1), a first end of the sixteenth resistor (R16) and an output end of the fourth operational amplifier (N1D), respectively, and a second end of the sixteenth resistor (R16) outputs the dc analog signal.
4. A detection method of a sine-cosine resolver, applied to a detection circuit of a sine-cosine resolver according to any one of claims 1 to 3, the method comprising:
receiving an output signal of a sine-cosine resolver, rectifying a sine signal and a cosine signal in the output signal of the sine-cosine resolver into a sine half-cycle steamed bread wave and a cosine half-cycle steamed bread wave respectively, and summing the sine half-cycle steamed bread wave and the cosine half-cycle steamed bread wave to obtain an alternating current analog signal;
filtering the alternating current analog signal into a direct current analog signal;
and determining whether the sine and cosine resolver has a fault or not according to the amplitude range of the direct current analog signal.
5. The method of claim 4, wherein the maximum amplitude of the AC analog signal is the sum of the amplitude of the steamed bread wave of the sine positive half cycle and the amplitude of the steamed bread wave of the cosine positive half cycle at the intersection;
the minimum amplitude of the alternating current analog signal is the sum of the amplitude of the steamed bread wave of the sine positive half cycle and the amplitude of the steamed bread wave of the cosine positive half cycle at the zero point.
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| CN112485652B (en) * | 2020-12-09 | 2021-09-14 | 电子科技大学 | Analog circuit single fault diagnosis method based on improved sine and cosine algorithm |
| CN113310396B (en) * | 2021-05-20 | 2022-04-19 | 西安电子科技大学 | Sine and cosine signal amplitude calculation circuit with double sampling structure |
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| US6205009B1 (en) * | 1999-07-22 | 2001-03-20 | General Electric Company | Method and apparatus for detecting faults in a resolver |
| JP2006078392A (en) * | 2004-09-10 | 2006-03-23 | Tamagawa Seiki Co Ltd | Fault detection method for resolver signal |
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