CN112927747B - Method for solving chip failure caused by routing of embedded memory chip - Google Patents
Method for solving chip failure caused by routing of embedded memory chip Download PDFInfo
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- CN112927747B CN112927747B CN202110438264.5A CN202110438264A CN112927747B CN 112927747 B CN112927747 B CN 112927747B CN 202110438264 A CN202110438264 A CN 202110438264A CN 112927747 B CN112927747 B CN 112927747B
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- chip
- definition data
- efuse module
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
Abstract
The invention discloses a method for solving the problem of chip failure caused by routing of an embedded memory chip, which comprises the steps of burning an efuse module to enable the efuse module to have a correct chip pin definition data file; the efuse module can be used for burning for three times, so that the efuse module has three chip pin definition data files; detecting whether the PIN of the efuse module is valid, if so, reading front 64bit data of the efuse module, and if no file exists or the first file and the second file are both wrong, skipping NAND BOOT, entering EP0INIT, and entering a main control chip main loop; if not, reading a pad configuration table of the ROM; if the file has the error or the first file and the second file have no error, finding out correct configuration information; if the configuration information is correct, configuring pins according to the efuse module information, reading a pad configuration table of the ROM if the configuration information is not correct and the efuse module has three files which are all wrong; entering a pad configuration flow and carrying out NAND BOOT; entering a main cycle of a main control chip; entering a vendor effect module programming command flow and waiting for a host command; the problem that the chip pin function needs to be redefined due to chip failure caused by routing deviation is solved.
Description
Technical Field
The invention relates to the field of semiconductor chip design, in particular to a method for solving chip failure caused by routing of an embedded memory chip.
Background
The embedded memory chip is widely applied to electronic products needing data storage, such as mobile phones, flat panels, televisions and the like, and most of the embedded memory chip exists in the form of chips such as eMMC, UFS, uMCP, UDP and the like; an embedded memory chip is generally composed of three parts, namely a main control chip, a Flash memory chip (Nand Flash) and a substrate, wherein the main control chip belongs to the field of ASIC (application Specific Integrated circuit) chips, is an application Specific Integrated circuit, is designed according to the requirements of users, has low cost, small area and high speed, and can be produced in batch. An ASIC memory main control chip can carry flash memory chips with different capacities and specifications of different manufacturers, is fixedly connected on a substrate which is customized in advance through gold wires, and is packaged finally to form a complete embedded memory chip; however, the Flash memory chip (Nand Flash) has many different models from different manufacturers on the market, and besides different chip pin definitions, even the same type of Flash memory chip has many different quality grades, each type of wire bonding mode is different, and many terminal customers often have deviation on wire bonding during batch use and production, which results in low yield and even direct failure of the chip.
If the memory chip of the client finds the wire bonding problem of the chip or the production yield is not high, because the memory chip of the client encapsulates the main control chip and the flash memory chip in one chip at the moment, the problem can be solved only by burning a new pin definition file into the efuse module again.
Disclosure of Invention
The invention aims to solve the defects in the prior art, and provides a method for solving the problem of chip failure caused by wire bonding of an embedded memory chip.
In order to achieve the purpose, the invention adopts the following technical scheme:
a solution for chip failure caused by routing of an embedded memory chip comprises a main control chip, wherein an efuse module is arranged on the main control chip; the method is characterized by comprising the following steps:
burning, in a step Q1, after a memory chip of a client is powered on for the first time, automatically writing a first chip pin definition data file into the efuse module of the main control chip according to the flash memory particle model provided by a user;
step Q2, the memory chip of the client is powered on again, and the efuse module is detected firstly;
step Q3, if the chip pin definition data file is correct and the verification is correct, the chip pin definition data file is directly used, and the efuse module is not burned again;
step Q4, if the result is incorrect, recording the efuse module again;
the efuse module can be burned for three times, so that the efuse module can have three chip pin definition data files;
detecting, in step S1, whether the efuse module PIN is valid, if so, executing step S2, otherwise, executing step S7;
step S2, reading the front 64bit data of the efuse module, detecting whether a chip pin definition data file or a first chip pin definition data file and a second chip pin definition data file in the efuse module are all wrong, if the chip pin definition data file or the first chip pin definition data file and the second chip pin definition data file are all wrong, executing step S3, and if the chip pin definition data file or the first chip pin definition data file and the second chip pin definition data file are all wrong, executing step S4;
step S3, skipping NAND BOOT into EP0INIT, and executing step S9;
step S4, finding the correct configuration information, if the configuration information is correct, executing step S6, if the configuration information is incorrect, executing step S5;
step S5, the definition data files of the efuse module three chip pins are all wrong, if yes, step S7 is executed, and if not, step S8 is executed;
step S6, configuring pins according to the efuse module information, and executing step S8;
step S7, reading the pad configuration table of the ROM; and performs step S8;
step S8, entering the pad configuration flow and performing the NAND BOOT;
step S9, entering the main control chip main loop;
step S10, enter the vendor effect module program command flow and wait for the host command.
Preferably, each efuse module has 64 bits of data, and stores 16 pad configurations, and each pad occupies 4 bits.
Compared with the prior art, the invention has the beneficial effects that:
the invention designs a solution to the chip failure caused by wire bonding of an embedded memory chip,
when the first chip pin definition in the efuse module is inconsistent with the routing in the actual chip, a client can have 2 chances of changing, and if three parts of the chip pin definition are wrong, the default configuration of a chip pin reserved in advance in a Read-Only Memory (ROM) program can be used; when the main control chip is designed, the efuse module is added in the chip, the process code defined by the pin of the main control chip is changed repeatedly is added, the bottleneck and the difficulty that the pin function of the chip needs to be redefined due to the fact that the embedded storage chip is invalid or the production yield is not high caused by routing deviation can be effectively solved, and the economic loss of a client who meets the problems is greatly reduced.
Drawings
FIG. 1 is a flowchart illustrating an operation of an efuse module of a main control chip according to the present invention;
FIG. 2 is a flowchart illustrating an efuse module burning process according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention; the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance; furthermore, unless expressly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, as they may be fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Referring to fig. 1 to 2, it is to be understood that any person skilled in the art may substitute or change the technical solution of the present invention and its inventive concept within the technical scope of the present invention. A solution for chip failure caused by routing of an embedded memory chip comprises a main control chip, wherein an efuse module is arranged on the main control chip; the method comprises the following steps:
burning, in a step Q1, after a memory chip of a client is powered on for the first time, automatically writing a first chip pin definition data file into an efuse module of a main control chip according to the flash memory particle model provided by a user; step Q2, the memory chip of the client is powered on again, and the efuse module is detected firstly; step Q3, if the correct chip pin definition data file exists and the verification is correct, the chip pin definition data file is directly used, and the efuse module is not burned again; step Q4, if the result is incorrect, recording the efuse module again; the efuse module can be burned for three times, so that the efuse module can have three chip pin definition data files;
detecting whether the PIN of the efuse module is valid or not, if so, executing a step S2, otherwise, executing a step S7, in a step S1; step S2, reading front 64bit data of the efuse module, detecting whether a chip pin definition data file or a first chip pin definition data file and a second chip pin definition data file in the efuse module are all wrong, executing step S3 if the chip pin definition data file or the first chip pin definition data file and the second chip pin definition data file are all wrong, and executing step S4 if the chip pin definition data file or the first chip pin definition data file and the second chip pin definition data file are all wrong; step S3, skipping NAND BOOT into EP0INIT, and executing step S9; step S4, finding the correct configuration information, if the configuration information is correct, executing step S6, if the configuration information is incorrect, executing step S5; step S5, if the definition data files of the efuse module three chip pins are all wrong, executing step S7, and if not, executing step S8; step S6, configuring pins according to the efuse module information, and executing step S8; step S7, reading the pad configuration table of the ROM; and performs step S8; step S8, entering a pad configuration flow and carrying out NAND BOOT; step S9, entering a main control chip main loop; step S10, enter the vendor effect module program command flow and wait for the host command.
Wherein, each efuse module data is 64 bits, 16 pad configurations are stored, and each pad occupies 4 bits; the first 3 bits are checksum and the last 1bit is 5/6 address selection.
When the first chip pin definition in the efuse module is inconsistent with the routing in the actual chip, a client can have 2 chances to change, and if three parts of the chip pin definitions are wrong, the default configuration of a chip pin reserved in advance in a ROM program can be used; when the main control chip is designed, the efuse module is added in the chip, the process code defined by the pin of the main control chip is changed repeatedly is added, the bottleneck and the difficulty that the pin function of the chip needs to be redefined due to the fact that the embedded storage chip is invalid or the production yield is not high caused by routing deviation can be effectively solved, and the economic loss of a client who meets the problems is greatly reduced.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art should be able to cover the technical scope of the present invention and the equivalent alternatives or modifications according to the technical solution and the inventive concept of the present invention within the technical scope of the present invention.
Claims (2)
1. A solution for chip failure caused by routing of an embedded memory chip comprises a main control chip, wherein an efuse module is arranged on the main control chip; the method is characterized by comprising the following steps:
burning, in a step Q1, after a memory chip of a client is powered on for the first time, automatically writing a first chip pin definition data file into the efuse module of the main control chip according to the flash memory particle model provided by a user;
step Q2, the memory chip of the client is powered on again, and the efuse module is detected firstly;
step Q3, if the correct chip pin definition data file exists and the verification is correct, the chip pin definition data file is directly used, and the efuse module is not burned again;
step Q4, if the result is incorrect, recording the efuse module again;
the efuse module can be burned for three times, so that the efuse module can have three chip pin definition data files;
detecting, in step S1, whether the efuse module PIN is valid, if so, executing step S2, otherwise, executing step S7;
step S2, reading the front 64bit data of the efuse module, detecting whether a chip pin definition data file or a first chip pin definition data file and a second chip pin definition data file in the efuse module are all wrong, if the chip pin definition data file or the first chip pin definition data file and the second chip pin definition data file are all wrong, executing step S3, and if the chip pin definition data file or the first chip pin definition data file and the second chip pin definition data file are all wrong, executing step S4;
step S3, skipping NAND BOOT into EP0INIT, and executing step S9;
step S4, finding the correct configuration information, if the configuration information is correct, executing step S6, if the configuration information is incorrect, executing step S5;
step S5, the definition data files of the efuse module three chip pins are all wrong, if yes, step S7 is executed, and if not, step S8 is executed;
step S6, configuring pins according to the efuse module information, and executing step S8;
step S7, reading the pad configuration table of the ROM; and performs step S8;
step S8, entering the pad configuration flow and performing the NAND BOOT;
step S9, entering the main control chip main loop;
step S10, enter the vendor effect module program command flow and wait for the host command.
2. The method as claimed in claim 1, wherein the data of each efuse module is 64 bits, 16 pad configurations are stored, and each pad occupies 4 bits.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5614761A (en) * | 1991-02-28 | 1997-03-25 | Hitachi, Ltd. | Electronic circuit package including plural semiconductor chips formed on a wiring substrate |
| US7170179B1 (en) * | 2002-04-29 | 2007-01-30 | Cypress Semiconductor Corp. | Chip select method through double bonding |
| CN103187095A (en) * | 2011-12-30 | 2013-07-03 | 联芯科技有限公司 | Efuse module control method and chip with efuse module |
| CN105717829A (en) * | 2015-11-16 | 2016-06-29 | 深圳市芯海科技有限公司 | Method for solving chip pin compatibility problem |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5614761A (en) * | 1991-02-28 | 1997-03-25 | Hitachi, Ltd. | Electronic circuit package including plural semiconductor chips formed on a wiring substrate |
| US7170179B1 (en) * | 2002-04-29 | 2007-01-30 | Cypress Semiconductor Corp. | Chip select method through double bonding |
| CN103187095A (en) * | 2011-12-30 | 2013-07-03 | 联芯科技有限公司 | Efuse module control method and chip with efuse module |
| CN105717829A (en) * | 2015-11-16 | 2016-06-29 | 深圳市芯海科技有限公司 | Method for solving chip pin compatibility problem |
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