CN112910455B - Output circuit - Google Patents

Abstract

The output circuit of the embodiment comprises 1 st to 3 rd power lines, a bonding pad (50), 1 st to 2 nd transistors and a 1 st circuit. The 1 st terminal of the 1 st transistor (TR 7) is connected to the 1 st power line, and the 2 nd terminal is connected to the pad. The 1 st terminal of the 2 nd transistor (TR 8) is connected to the 2 nd power line, and the 2 nd terminal is connected to the pad (50). The 1 st circuit is connected to each of the 3 rd power line and the gate of the 1 st transistor. The 1 st Voltage (VCCQ) is applied to the 1 st power line. A 2 nd Voltage (VSS) lower than the 1 st voltage is applied to the 2 nd power line. A3 rd voltage (VDD 1) different from both the 1 st voltage and the 2 nd voltage is applied to the 3 rd power supply line. In case 1, the 1 st circuit applies the 4 th voltage (VDD 1) to the gate of the 1 st transistor. In case 2, the 1 st circuit electrically connects the 3 rd power line to the gate of the 1 st transistor.

Description

Output circuit

[ related application ]

The present application enjoys priority over Japanese patent application No. 2019-219580 (application date: 12/4/2019). This application contains the entire contents of the basic application by reference to this basic application.

Technical Field

Embodiments relate generally to an output circuit.

Background

An output circuit for outputting a signal is known.

Disclosure of Invention

The embodiment provides an output circuit capable of suppressing power consumption in a standby state.

The output circuit of the embodiment includes a 1 st power line, a 2 nd power line, a 3 rd power line, a pad, a 1 st transistor, a 2 nd transistor, and a 1 st circuit. The 1 st end of the 1 st transistor is connected to the 1 st power line, and the 2 nd end is connected to the welding pad. The 1 st end of the 2 nd transistor is connected to the 2 nd power line, and the 2 nd end is connected to the welding pad. The 1 st circuit is connected to each of the 3 rd power line and the gate of the 1 st transistor. The 1 st voltage is applied to the 1 st power line. A 2 nd voltage lower than the 1 st voltage is applied to the 2 nd power line. A3 rd voltage different from the 1 st voltage and the 2 nd voltage is applied to the 3 rd power supply line. In the 1 st case, the 1 st circuit applies the 4 th voltage to the gate of the 1 st transistor. In case 2, the 1 st circuit electrically connects the 3 rd power line to the gate of the 1 st transistor.

Drawings

Fig. 1 is a block diagram showing an example of the configuration of a memory system including the semiconductor memory device of embodiment 1.

Fig. 2 is a block diagram showing an example of the structure of the semiconductor memory device according to embodiment 1.

Fig. 3 is a block diagram showing an example of the configuration of a power supply circuit included in the semiconductor memory device according to embodiment 1.

Fig. 4 is a block diagram showing an example of the configuration of an input/output module included in the semiconductor memory device according to embodiment 1.

Fig. 5 is a block diagram showing a configuration example of an input/output module included in the semiconductor memory device according to embodiment 1.

Fig. 6 is a circuit diagram showing an example of the configuration of an output circuit included in an input/output module included in the semiconductor memory device according to embodiment 1.

Fig. 7 is a block diagram showing an example of the configuration of an input/output control circuit included in an input/output module included in the semiconductor memory device according to embodiment 1.

Fig. 8 is a timing chart showing an example of various signals transmitted and received by the semiconductor memory device according to embodiment 1.

Fig. 9 is a table showing the relationship between logic levels and voltages of various signals in the semiconductor memory device according to embodiment 1.

Fig. 10 is a circuit diagram showing an example of the operation in the 1 st state of the output circuit included in the semiconductor memory device according to embodiment 1.

Fig. 11 is a circuit diagram showing an example of the operation of the output circuit included in the semiconductor memory device according to embodiment 1 in the 2 nd state.

Fig. 12 is a circuit diagram showing an example of the operation of the output circuit included in the semiconductor memory device according to embodiment 1 in the 2 nd state.

Fig. 13 is a circuit diagram showing an example of the configuration of an output circuit included in the semiconductor memory device according to the modification of embodiment 1.

Fig. 14 is a block diagram showing an example of the configuration of a power supply circuit included in the semiconductor memory device according to embodiment 2.

Fig. 15 is a circuit diagram showing an example of the configuration of an output circuit included in the semiconductor memory device according to embodiment 2.

Fig. 16 is a block diagram showing an example of the configuration of an input/output control circuit included in the semiconductor memory device according to embodiment 2.

Fig. 17 is a table showing the relationship between logic levels and voltages of various signals in the semiconductor memory devices according to embodiment 2 and embodiment 7.

Fig. 18 is a circuit diagram showing an example of the configuration of an output circuit included in the semiconductor memory device according to embodiment 3.

Fig. 19 is a block diagram showing an example of the configuration of an input/output control circuit included in the semiconductor memory device according to embodiment 3.

Fig. 20 is a table showing the relationship between logic levels and voltages of various signals in the semiconductor memory device according to embodiment 3.

Fig. 21 is a circuit diagram showing an example of the configuration of an output circuit included in the semiconductor memory device according to embodiment 4.

Fig. 22 is a block diagram showing an example of the configuration of an input/output control circuit included in the semiconductor memory device according to embodiment 4.

Fig. 23 is a table showing the relationship between logic levels and voltages of various signals in the semiconductor memory device according to embodiment 4.

Fig. 24 is a circuit diagram showing an example of the configuration of an output circuit included in the semiconductor memory device according to embodiment 5.

Fig. 25 is a circuit diagram showing an example of the configuration of an output circuit included in the semiconductor memory device according to embodiment 6.

Fig. 26 is a circuit diagram showing an example of the configuration of a main driver included in the semiconductor memory device according to the modification of embodiment 1.

Fig. 27 is a circuit diagram showing an example of the configuration of a predriver included in the semiconductor memory device according to the modification of embodiment 1.

Fig. 28 is a block diagram showing an example of the configuration of an output circuit included in the semiconductor memory device according to the modification of embodiment 1.

Fig. 29 is a circuit diagram showing an example of the configuration of an output circuit included in the semiconductor memory device according to the modification of embodiment 3.

Fig. 30 is a circuit diagram showing an example of the configuration of an output circuit included in the semiconductor memory device according to the modification of embodiment 4.

Fig. 31 is a diagram showing an example of a cross-sectional structure of a pre-driver included in the semiconductor memory device according to embodiment 2.

Fig. 32 is a diagram showing an example of a cross-sectional structure of a pre-driver included in the semiconductor memory device according to embodiment 2.

Fig. 33 is a circuit diagram showing an example of the configuration of an output circuit included in the semiconductor memory device according to embodiment 7.

Fig. 34 is a graph showing the output waveform of the output circuit of embodiment 7 and the output waveform of the output circuit of embodiment 2.

Fig. 35 is a circuit diagram showing an example of the configuration of an output circuit included in the semiconductor memory device according to the modification of embodiment 7.

Detailed Description

Hereinafter, embodiments will be described with reference to the drawings. The embodiments illustrate apparatuses or methods for embodying the technical ideas of the invention. The drawings are schematic or conceptual drawings, and the dimensions, ratios, etc. of the drawings are not necessarily the same as actual ones. The technical idea of the present invention is not specified by the shape, structure, arrangement, etc. of the constituent elements.

In the following description, the same reference numerals are given to constituent elements having substantially the same functions and configurations. Numerals after characters constituting the reference numerals are referred to by the reference numerals including the same characters, and are used to distinguish elements having the same constitution from each other. In the case where it is not necessary to distinguish elements represented by reference numerals containing the same characters from each other, the elements are referred to by reference numerals containing only characters.

[1] Embodiment 1

Hereinafter, the semiconductor memory device 1 of embodiment 1 will be described.

[1-1] constitution

Fig. 1 shows an example of a configuration of a memory system SYS including a semiconductor memory device 1 according to embodiment 1. As shown in fig. 1, the memory system SYS includes a semiconductor memory device 1 and a memory controller 2. The semiconductor memory device 1 is, for example, a NAND (Not AND) flash memory. The storage system SYS is connected to an external host device, not shown, and performs operations such as data storage and data reading in response to a command from the host device.

The semiconductor memory device 1 is connected to the memory controller 2 via, for example, a NAND bus. The communication using the NAND bus includes signals DQ0 to 7, DQS,/CE, CLE, ALE,/WE, RE,/WP, and/RB, for example.

The signals DQ0 to 7 are, for example, 8-bit signals, and are transmitted and received between the semiconductor memory device 1 and the memory controller 2. The signals DQ0 to 7 are entities of data transmitted and received between the semiconductor memory device 1 and the memory controller 2, and may include any of instructions, addresses, and data.

The signals DQS and/DQS are transmitted and received between the semiconductor memory device 1 and the memory controller 2. The DQS signals and/DQS are used to control the timing of operations when the control signals DQ 0-7 are received.

A signal/CE is sent from the memory controller 2 to the semiconductor memory apparatus 1. The signal/CE is a signal for setting the semiconductor memory apparatus 1 to a selected state or a non-selected state. For example, when a plurality of semiconductor memory devices are connected to the memory controller, the memory controller 2 may select the semiconductor memory device to be operated using the signal/CE. When the signal/CE is at the "H" level, the memory controller 2 sets the semiconductor memory device 1 to the non-selected state. When the signal/CE is at the "L" level, the memory controller 2 sets the semiconductor memory device 1 to the selected state.

Each of the signals CLE, ALE,/WE, RE,/RE, and/WP is transmitted from the memory controller 2 to the semiconductor memory device 1. The signal CLE is a signal notifying that the signals DQ0 to 7 are commands. The signal ALE is a signal notifying that the signals DQ0 to 7 are addresses. The signal/WE is a signal indicating that the semiconductor memory apparatus 1 captures signals DQ0 through 7. The signals RE and/or RE are signals instructing the semiconductor memory apparatus 1 to output the signals DQ0 to 7. The signals RE and/RE control the operation timing of the semiconductor memory device 1 when the signals DQ0 to 7 are outputted. The signal WP is a signal for prohibiting the writing and erasing operations of the semiconductor memory device 1.

The signal/RB is transmitted from the semiconductor storage device 1 to the memory controller 2. The signal/RB is a signal indicating whether the semiconductor storage device 1 is in a ready state (a state in which a command from the outside is received) or in a busy state (a state in which a command from the outside is not received).

Fig. 2 shows an exemplary configuration of the semiconductor memory device 1. As shown in fig. 2, the semiconductor memory device 1 operates using voltages VCC, VCCQ, and VSS supplied from the outside. VCC is, for example, a voltage of about 2.5V. VCCQ is, for example, a voltage of about 1.2V. In this embodiment, VCC is a voltage higher than VCCQ. VSS is, for example, a ground voltage of 0V. The semiconductor memory device 1 further includes an input/output module 10, a logic control circuit 11, a register 12, a sequencer 13, a memory cell array 14, a row decoder 15, a sense amplifier 16, a driver group 17, and a power supply circuit 18. The voltage VCC (voltages VDD, VDD1, and VDD2 described below, which are generated by the voltage VCC) is supplied to, for example, the logic control circuit 11, the register 12, the sequencer 13, the memory cell array 14, the row decoder 15, the sense amplifier 16, the driver group 17, and the power supply circuit 18. The voltage VCCQ is supplied to at least a part of the input-output module 10, for example.

The input/output module 10 transmits/receives signals DQ0 to 7, a signal DQs, and a signal/DQs. The input-output module 10 is connected to a data bus. The data bus is a collection of wirings for transmitting and receiving data in the semiconductor memory device 1, and is connected to, for example, the input/output module 10, the register 12, and the sense amplifier 16. The input/output module 10 transfers the instruction and address in the signals DQ0 to 7 to the register 12. The input/output module 10 transmits/receives write data and read data to/from the sense amplifier 16. The input-output module 10 generates signals DQS and/DQS based on the signals RE and/RE.

The logic control circuit 11 receives signals/CE, CLE, ALE,/WE, RE,/RE and/WP and transmits signals/RB. The logic control circuit 11 transmits a signal based on the received signal to the input/output module 10 and the sequencer 13.

The register 12 temporarily holds instructions and addresses received via the input-output module 10. Register 12 transmits the address to row decoder 15 and sense amplifier 16. In addition, the register 12 transfers instructions to the sequencer 13.

The sequencer 13 controls the operation of the entire semiconductor memory device 1. For example, the sequencer 13 receives an instruction from the register 12, and executes a read operation or the like based on the received instruction. The sequencer 13 controls the input/output module 10 based on the control of the logic control circuit 11.

The memory cell array 14 holds data in a nonvolatile manner. The memory cell array 14 includes a plurality of bit lines BL, a plurality of word lines WL, and a plurality of memory cells MC. The plurality of memory cells MC are arranged in a row direction and a column direction, for example. The bit lines BL are provided in the column direction and connected to the memory cells MC corresponding to the same column. The plurality of word lines WL are provided in correspondence with each other in the row direction, and are connected to the plurality of memory cells MC corresponding to the same row.

The row decoder 15 receives a row address of the addresses from the register 12, and selects a memory cell MC of a row based on the row address. The voltage from the driver group 17 is transmitted to the memory cells MC in the selected row via the row decoder 15.

The sense amplifier 16 senses the read data read from the memory cell MC to the bit line BL and transmits the sensed read data to the input-output module 10 when the data is read. The sense amplifier 16 transfers the written data to the memory cell MC via the bit line BL when writing the data. In addition, the sense amplifier 16 receives a column address among addresses from the register 12, and outputs data of a column based on the column address.

The driver group 17 generates voltages for the operations of the memory cell array 14, the row decoder 15, and the sense amplifier 16.

The power supply circuit 18 generates a power supply voltage used in the semiconductor memory device 1. For example, the power supply circuit 18 uses the voltage VCC to generate various voltages used in the input-output module 10.

Fig. 3 shows an exemplary configuration of the power supply circuit 18. As shown in fig. 3, the power supply circuit 18 includes a regulator 20, a regulator 21, and a regulator 22. Regulator 20 generates voltage VDD from voltage VCC. Regulator 21 generates voltage VDD1 from voltage VCC. Regulator 22 generates voltage VDD2 from voltage VCC. Details of voltages VDD, VDD1 and VDD2 will be described below.

Fig. 4 shows an example of the configuration of the input/output module 10. As shown in fig. 4, the input-output module 10 includes input-output components 30-0 to 30-9, an input-output control circuit 40, and pads 50-0 to 50-9. Each of the input-output components 30 is connected to a corresponding pad 50. The input-output components 30-0 to 30-7 correspond to the signals DQ0 to DQ7, respectively. The input output component 30-8 corresponds to the signal DQS. The input output components 30-9 correspond to signals/DQS. The input-output components 30-0 to 30-7 are connected to a data bus. The input/output components 30-8 and 30-9 are connected to the logic control circuit 11. The input-output control circuit 40 receives the signal STBY from the logic control circuit 11. The signal STBY is a signal based on signal/CE. The input-output control circuit 40 controls the input-output components 30-0 to 30-9 based on the signal STBY.

Fig. 5 shows an example of the structure of the input/output module 30. As shown in fig. 5, the input-output device 30 includes an input circuit 31 and an output circuit 32. The input circuit 31 and the output circuit 32 are connected in parallel between the pad 50 and the data bus. In the case of inputting a signal to the pad 50, the input circuit 31 receives the signal input to the pad 50 and transmits the received signal to the data bus. In the case of outputting a signal from the pad 50, the output circuit 32 receives a signal of the data bus and outputs the received signal to the pad 50. Each of the input circuit 31 and the output circuit 32 is controlled by an input-output control circuit 40.

Fig. 6 shows an exemplary configuration of the output circuit 32. As shown in fig. 6, the output circuit 32 includes a logic unit 60, a pre-driver 70, and a main driver 80.

The logic unit 60 outputs a signal or standby voltage input to the output circuit 32 to the pre-driver 70 based on the signal STBY. The logic portion 60 includes an AND gate 61 AND an OR gate 62. The AND gate 61 performs an AND operation on the signal SP AND the signal/STBY, AND outputs the operation result to the node N2. The OR gate 62 performs an OR operation on the signal SN and the signal STBY, and outputs the operation result to the node N4. The signals SP and SN are, for example, signals input from the data bus to the output circuit 32.

The pre-driver 70 outputs a signal or standby voltage input from the logic section 60 to the main driver 80 based on the signal STBY. The pre-driver 70 includes transistors TR1 to TR6. The transistors TR1, TR4, and TR5 are, for example, P-type MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistor, metal-Oxide-semiconductor field effect transistors) (PMOS (P-channel Metal Oxide semiconductor, P-type Metal Oxide semiconductor)). The transistors TR2, TR3, and TR6 are, for example, N-type MOSFETs (NMOS (N-channel metal oxide semiconductor, N-type metal oxide semiconductor)).

A voltage VCCQ is applied to each of the source and back gates of the transistor TR 1. The gate of the transistor TR1 is connected to the node N2. The drain of the transistor TR2 is connected to the drain of the transistor TR 1. The source of the transistor TR2 is connected to the node N1. The back gate of the transistor TR2 is grounded. The signal S2 is applied to the gate of the transistor TR 2. Each of the source and the back gate of the transistor TR3 is grounded. The drain of the transistor TR3 is connected to the node N1. The gate of the transistor TR3 is connected to the node N2. The voltage VDD1 is applied to each of the source and back gate of the transistor TR 4. The drain of the transistor TR4 is connected to the node N1. The signal S1 is applied to the gate of the transistor TR 4.

A voltage VCCQ is applied to each of the source and back gates of the transistor TR 5. The drain of the transistor TR5 is connected to the node N3. The gate of the transistor TR5 is connected to the node N4. The source and back gate of transistor TR6 are grounded. The drain of the transistor TR6 is connected to the node N3. The gate of the transistor TR6 is connected to the node N4.

The main driver 80 outputs a voltage to the pad 50 based on the output of the pre-driver, or sets the output node of the main driver 80 in a high impedance state. The main driver 80 includes a transistor TR7 and a transistor TR8. A voltage VCCQ is applied to each of the source and back gates of the transistor TR 7. The drain of transistor TR7 is connected to pad 50. The gate of the transistor TR7 is connected to the node N1. Each of the source and back gate of the transistor TR8 is grounded. The drain of transistor TR8 is connected to pad 50. The gate of the transistor TR8 is connected to the node N3. The drain of transistor TR7 and the drain of transistor TR8 are also output nodes of the main driver 80. The output impedance of the main driver 80 is based on the on-resistance of the transistor TR7 or the transistor TR8. The output impedance of the output circuit 32 is based on the output impedance of the main driver 80.

A plurality of voltages are supplied to the output circuit 32. The voltage VDD is supplied to the logic unit 60. The pre-driver 70 is supplied with the voltage VCCQ and a voltage different from the voltage VCCQ. The voltage different from the voltage VCCQ is, for example, the voltage VDD1. The voltage VCCQ is supplied to the main driver 80. The signals STBY,/STBY, S1 and S2 are signals output by the input/output control circuit 40. Further, the signal STBY may be input to the input-output component 30 without via the input-output control circuit 40.

Fig. 7 shows a configuration of the input/output control circuit 40. As shown in fig. 7, the input/output control circuit 40 includes an inverter 41, a level shifter 42, and a level shifter 43. The inverter 41 outputs a signal/STBY in which the signal STBY is logically inverted. The level shifter 42 outputs a signal S1 in which the "H" level voltage of the signal/STBY is converted into the voltage VDD 1. The level shifter 43 outputs a signal S2 in which the "H" level voltage of the signal/STBY is converted into the voltage VDD 2.

[1-2] action

Next, the operation of the semiconductor memory device 1 according to embodiment 1 will be described. In embodiment 1, it is assumed that voltage VCC is greater than voltages VDD, VDD1 and VDD2, voltage VDD1 is greater than voltage VDD, voltage VDD2 is greater than voltages VDD and VDD1, and voltage VDD2 is equal to or greater than the sum of voltage VCCQ and the threshold voltage of transistor TR 2. The output circuit 32 included in the semiconductor memory device 1 of embodiment 1 operates differently according to the logic level of the signal STBY. The details of the various signals and the operation of the output circuit 32 will be described in order.

Fig. 8 is a timing chart showing an example of various signals transmitted and received by the semiconductor memory device 1 according to embodiment 1. Fig. 8 shows an example of the operations of the signals DQS,/DQS, DQ0 to 7,/CE,/RE, and RE when the plurality of output circuits 32 output signals to the memory controller 2. At time t0, signal/CE is at "H" level, and semiconductor memory device 1 is in a non-selected state. The signal STBY is at the "H" level, and the output nodes of the output circuits 32 are in a high impedance state. At time t1, the memory controller 2 transitions the signal/CE from the "H" level to the "L" level. The signal/CE becomes the "L" level, and the semiconductor memory device 1 becomes the selected state. Thereafter, at time t2, the logic control circuit 11 of the semiconductor memory apparatus 1 in the selected state transitions the signal STBY from the "H" level to the "L" level based on the signal/CE. By the signal STBY transitioning to the "L" level, each of the output circuits 32 becomes a state in which a signal can be output. Thereafter, based on the signals RE and/or RE received from the memory controller 2, the signals DQS,/DQS and DQ0 to 7 are sequentially outputted from the plurality of output circuits 32. Thereafter, when the semiconductor memory apparatus 1 completes data output, the memory controller 2 transitions the signal/CE to the "H" level at time t 3. Based on the signal/CE becoming the "H" level, the logic control circuit 11 transitions the signal STBY to the "H" level at time t 4. When the signal STBY transitions to the "H" level, the output node of the output circuit 32 becomes a high impedance state. Details of this operation will be described below.

Thus, the semiconductor memory device 1 according to embodiment 1 transmits the signals DQS,/DQS and the signals DQ0 to 7 while the signal STBY is at the "L" level. In addition, the semiconductor memory device 1 sets the output node of each output circuit 32 corresponding to the signals DQS,/DQS and the signals DQ0 to 7 to a high impedance state during the period in which the signal STBY is at the "H" level.

Fig. 9 shows the relationship between the logic levels and voltages of various signals in the semiconductor memory device 1 according to embodiment 1. Further, the signal STBY is a signal based on the chip enable signal/CE. As shown in fig. 9, the semiconductor memory device 1 of embodiment 1 can be set to the 1 st state and the 2 nd state.

In the 1 st state, the signals STBY,/STBY, S1 and S2 are controlled to the "H" level, "L" level and "L" level, respectively. At this time, the output node of the output circuit 32 is in a high impedance state. Hereinafter, the 1 st state is referred to as a standby state of the output circuit 32. That is, when the signal STBY is at the "H" level, the output circuit 32 is in the standby state.

In the 2 nd state, the signals STBY,/STBY, S1 and S2 are controlled to the "L" level, the "H" level and the "H" level, respectively. At this time, the output circuit 32 is in a state capable of outputting signals based on the signals SP and SN. Hereinafter, the 2 nd state is referred to as an active state of the output circuit 32. That is, when the signal STBY is at the "L" level, the output circuit 32 is in the active state.

As described above, each output circuit 32 in the input-output module 10 can be controlled to a standby state or an active state by the signal STBY. Further, the "H" level of the signal STBY corresponds to the voltage VDD. The "L" level of the signal STBY corresponds to the voltage VSS. The "H" level of the signal/STBY corresponds to the voltage VSS. The "L" level of the signal/STBY corresponds to the voltage VDD. The "H" level of the signal S1 corresponds to the voltage VDD 1. The "L" level of the signal S1 corresponds to the voltage VSS. The "H" level of the signal S2 corresponds to the voltage VDD 2. The "L" level of the signal S2 corresponds to the voltage VSS.

Fig. 10 shows an example of the operation in the 1 st state of the output circuit 32 included in the semiconductor memory device 1 according to embodiment 1. In the 1 st state, the signal STBY is at the "H" level, and therefore, the output circuit 32 is in the standby state. The logic unit 60, the pre-driver 70, and the main driver 80 will be described in order with respect to the output circuit 32 in the standby state.

The operation of the logic unit 60 will be described. The signal/STBY of the "L" level is input to the AND gate 61. Thus, the AND gate 61 outputs an "L" level to the node N2 regardless of the logic level of the signal SP. The "L" level output by the AND gate 61 is, for example, the voltage VSS. The signal STBY of the "H" level is input to the OR gate 62. Thus, OR gate 62 outputs an "H" level to node N4 regardless of the logic level of signal SN. The "H" level output by OR gate 62 is, for example, voltage VCCQ.

The operation of the pre-driver 70 will be described. The PMOS transistor TR4 is turned on by the signal S1 of the voltage VSS applied to the gate. The NMOS transistor TR3 is turned off because the node N2 applies an "L" level to the gate. The NMOS transistor TR2 is turned off by the signal S2 of the voltage VSS applied to the gate. The PMOS transistor TR1 is turned on by applying an "L" level to the gate of the node N2, but the transistor TR2 connected to the drain is turned off and current does not flow, so that it is actually turned off. As a result, the voltage of the node N1 is determined as the voltage VDD1 by the transistor TR4 in the on state. The PMOS transistor TR5 is turned off because the node N4 applies an "H" level to the gate. The NMOS transistor TR6 is turned on by applying an "H" level to the gate of the node N4. As a result, the voltage of the node N3 is determined as the voltage VSS by the transistor TR6 in the on state.

The operation of the main driver 80 will be described. The PMOS transistor TR7 is turned off by applying the voltage VDD1 to the gate of the node N1. The NMOS transistor TR8 is turned off because the voltage VSS is applied to the gate of the node N3. As a result, the output node of the output circuit 32 becomes a high impedance state.

Thus, the transistors TR7 and TR8 of the output circuit 32 in the standby state are turned off, and the output node of the output circuit 32 is in a high impedance state. At this time, the voltage VDD1 is applied to the gate of the PMOS transistor TR 7.

Fig. 11 shows an example of the operation in the 2 nd state of the output circuit 32 included in the semiconductor memory device 1 according to embodiment 1. In the 2 nd state, the signal STBY is at the "L" level, and therefore, the output circuit 32 is in the active state. In the example shown in fig. 10, the active state output circuit 32 outputs an "L" level. The logic unit 60, the predriver 70, and the main driver 80 are described in order.

The operation of the logic unit 60 will be described. In the 2 nd state, the signal STBY is at the "L" level, and the signal/STBY is at the "H" level. The AND gate 61 performs an AND operation on the logic level of the signal SP AND the "H" level of the signal/STBY, AND outputs the operation result to the node N2. In the example shown in fig. 10, the signal SP is at the "L" level, AND therefore the AND gate 61 outputs the "L" level to the node N2. The "L" level output by the AND gate 61 is, for example, the voltage VSS. The OR gate 62 performs an OR operation on the logic level of the signal SN and the "L" level of the signal STBY, and outputs the operation result to the node N4. In the example shown in fig. 10, the signal SN is at the "L" level, and therefore, the OR gate 62 outputs the "L" level to the node N4. The "L" level output by the OR gate 62 is, for example, the voltage VSS.

The operation of the pre-driver 70 will be described. The PMOS transistor TR4 is turned off by the signal S1 of the voltage VDD1 applied to the gate. The PMOS transistor TR1 is turned on by applying an "L" level to the gate of the node N2. The signal S2 of the voltage VDD2 is applied to the gate of the NMOS transistor TR2, and thus the NMOS transistor TR2 is turned on. The PMOS transistor TR31 is turned off because the node N2 applies an "L" level to the gate. As a result, the voltage VCCQ is transferred to the node N1 via the PMOS transistor TR1 and the NMOS transistor TR2 in the on state. Here, the voltage VDD2 applied to the gate of the NMOS transistor TR2 is greater than the sum of the threshold voltage of the transistor TR2 and the voltage VCCQ. Therefore, the voltage VCCQ supplied from the source of the PMOS transistor TR1 is not lowered by the threshold lowering (Vth drop) of the NMOS transistor TR2, but is directly transferred to the node N1. The PMOS transistor TR5 is turned on because the node N4 applies an "L" level to the gate and the gate-source voltage is greater than the threshold voltage. The NMOS transistor TR6 is turned off because the node N4 applies an "L" level to the gate and the gate-source voltage is approximately 0V. As a result, the voltage VCCQ is applied to the node N3 via the PMOS transistor TR5 in the on state.

The operation of the main driver 80 will be described. The PMOS transistor TR7 is turned off because the voltage VCCQ is applied to the gate at the node N1 and the gate-source voltage is substantially 0V. The NMOS transistor TR8 is turned on because the voltage VCCQ is applied to the gate of the node N3 and the gate-source voltage is greater than the threshold voltage. As a result, the voltage VSS is applied to the pad 50 via the transistor TR8 in the on state.

Fig. 12 shows an example of the operation in the 2 nd state of the output circuit 32 included in the semiconductor memory device 1 according to embodiment 1. In the example shown in fig. 11, the active state output circuit 32 outputs an "H" level. The logic unit 60, the predriver 70, and the main driver 80 are described in order.

The operation of the logic unit 60 will be described. In the 2 nd state, the signal STBY is at the "L" level, and the signal/STBY is at the "H" level. The AND gate 61 performs an AND operation on the logic level of the signal SP AND the "H" level of the signal/STBY, AND outputs the operation result to the node N2. In the example shown in fig. 11, the signal SP is at the "H" level, AND therefore the AND gate 61 outputs the "H" level to the node N2. The "H" level output by the AND gate 61 is, for example, the voltage VCCQ. The OR gate 62 performs an OR operation on the logic level of the signal SN and the "L" level of the signal STBY, and outputs the operation result to the node N4. In the example shown in fig. 11, the signal SN is at the "H" level, and therefore, the OR gate 62 outputs the "H" level to the node N4. The "H" level output by OR gate 62 is, for example, voltage VCCQ.

The operation of the pre-driver 70 will be described. The transistor TR4 is turned off by the signal S1 of the voltage VDD1 applied to the gate. Since the gate-source voltage of the transistor TR1 is substantially 0V, the transistor TR1 is turned off. A voltage VDD2, which is a voltage greater than the sum of the threshold voltage of the transistor TR2 and the voltage VCCQ, is applied to the gate of the transistor TR 2. However, since the transistor TR1 is in an off state, the transistor TR2 does not apply a voltage to the node N1. The transistor TR3 is turned on because the gate-source voltage is greater than the threshold voltage. As a result, the voltage VSS is supplied to the node N1 via the transistor TR3 in the on state. The transistor TR5 is turned off because the gate-source voltage is substantially 0V. The transistor TR6 is turned on because the gate-source voltage is greater than the threshold voltage. As a result, the voltage VSS is applied to the node N3 via the transistor TR6 in the on state.

The operation of the main driver 80 will be described. The transistor TR7 is turned on because the gate-source voltage is greater than the threshold voltage. The transistor TR8 is turned off because the gate-source voltage is substantially 0V. As a result, the voltage VCCQ is applied to the pad 50 via the transistor TR7 in the on state.

As described with reference to fig. 11 and 12, the output circuit 32 included in the semiconductor memory device 1 according to embodiment 1 can control the voltage of the node N1 to be the voltage VCCQ or the voltage VSS in the active state, and output the "H" level or the "L" level to the output node.

[1-3] effects of embodiment 1

According to the semiconductor memory device 1 of embodiment 1 described above, leakage current in the standby state can be suppressed. The following describes the detailed effects of the semiconductor memory device 1 according to embodiment 1.

When a signal is transmitted from a semiconductor memory device to a memory controller, impedance matching is performed in order to maintain signal quality. Specifically, each of the output circuit, the transmission line, and the reception circuit is provided in such a manner that the output impedance of the output circuit, the characteristic impedance of the transmission line, and the input impedance of the reception circuit are each equal. For high-speed communication, impedance matching with a low impedance is preferable.

In order to reduce the output impedance of the output circuit, a method of improving the current supply capability of the main driver is conceived. Specifically, for example, it is conceivable to use a transistor having a larger size for the main driver. However, if the size of the transistor is enlarged, the area occupied by the transistor on the semiconductor substrate may be increased, and the leakage current of the transistor may be increased. As another method for improving the current supply capability of the main driver, it is also conceivable to use a transistor having a lower threshold voltage for the main driver. Transistors with lower threshold voltages have a larger current supply capability than transistors with higher threshold voltages, even if the transistors are the same size. Therefore, by using a transistor having a low threshold voltage for the main driver, an increase in area can be suppressed and current supply capability can be improved. However, if a transistor having a lower threshold voltage is used, there is a case where leakage current increases as compared with a case where a transistor having a higher threshold voltage is used.

In addition, the leakage current of the transistor may vary according to the characteristics of the transistor and the bias state of the transistor. The characteristics of the transistor vary, for example, due to the manufacturing process. The bias condition with the smallest leakage current depends on the characteristics of the transistor, and is one of the case where the reverse bias is strong, the case where the reverse bias is weak, the case where the zero bias is weak, and the case where the forward bias is weak. For example, if the transistor TR7 becomes a reverse bias state, the leakage current becomes smaller than that in the zero bias state.

Therefore, in the semiconductor memory device 1 of embodiment 1, the voltage VDD1 is applied to the node N1 in the standby state. The voltage VDD1 is a voltage higher than the voltage VCCQ. Accordingly, the PMOS transistor TR7 is in a reverse bias state because the voltage VCCQ is applied to the source and the voltage VDD1 higher than the voltage VCCQ is applied to the gate. As a result, in the semiconductor memory device 1 of embodiment 1, the leakage current of the transistor TR7 can be suppressed in the standby state. By suppressing the leakage current of the transistor TR7, power consumption of the semiconductor memory device 1 can be suppressed.

Further, as a method for suppressing an increase in leakage current, it is also conceivable to insert a transistor switch excellent in current interruption capability in a current path through which the leakage current flows. Specifically, for example, a method of applying the voltage VCCQ to the source of the transistor TR7 via a transistor switch is conceivable. By turning off the transistor switch in the standby state, the leakage current can be suppressed from flowing. However, when a transistor switch is provided between the power supply voltage and the output circuit, the output impedance of the output circuit is the sum of the on-resistance of the transistor switch and the output resistance of the main driver. A transistor switch having excellent current interruption capability may have an on-resistance larger than that of a general transistor. If a transistor switch having excellent current breaking capability is provided so that the on-resistance becomes small, a large area may be occupied.

In contrast, in the semiconductor memory device 1 according to embodiment 1, the gate voltages of the PMOS transistor TR7 and the PMOS transistor TR7 out of the NMOS transistor TR8 constituting the main driver 80 are controlled in the standby state, so that an increase in leakage current is suppressed. Specifically, the voltage of the node N1 in the standby state is controlled by controlling the transistor TR2 and the transistor TR 4. The transistor TR4 is set to a size capable of applying the voltage VDD1 to the node N1 at the time of standby. The transistor TR2 is set to a size that enables the voltage of the node N1 to be the voltage VCCQ or the voltage VSS based on the signal SP in an active state. The transistors TR2 and TR4 can be set to a smaller size than in the case where a switch is provided between the power supply voltage VCCQ and the main driver 80. That is, an increase in circuit area due to the addition of a circuit for suppressing leakage current can be suppressed.

In the semiconductor memory device 1 according to embodiment 1, the voltage VDD1 is supplied to the node N1 in response to the transistor TR1 being turned on during standby, and the transistor TR2 is controlled to be turned off.

In the case where a transistor is provided over a semiconductor substrate, a diffusion region functioning as a source or a drain is provided in a well region, for example. For example, in the case of a P-type MOSFET, a diffusion region functioning as a source or a drain is P-type, and a well region provided with a diffusion region is N-type. The PN junction existing between the diffusion region and the well region is turned on when a voltage difference higher than a threshold voltage of the PN junction is applied, and functions as a current path.

In the semiconductor memory device 1 of embodiment 1, in the standby state, the transistor TR2 is controlled to be in the off state, whereby the voltage VDD1 is controlled to be applied to the drain of the transistor TR 1. Thus, even when the voltage VDD1 is larger than the sum of the voltages VCCQ and the threshold voltage of the PN junction, the PN junction existing in the diffusion region functioning as the drain of the transistor TR1 is suppressed from being turned on, and a current flows.

In the semiconductor memory device 1 according to embodiment 1, when the NMOS transistor TR2 is controlled to be in the on state in the active state, a voltage VDD2 greater than the sum of the voltage VCCQ and the threshold voltage of the transistor TR2 is applied to the gate. The NMOS transistor TR2 can directly transfer the voltage VCCQ supplied to the drain via the transistor TR1 to the node N1 connected to the source without so-called threshold lowering (Vth drop) by applying the voltage VDD2 to the gate thereof. Thus, the transistors TR1, TR2, and TR3 can operate as an inverter of the output voltage VCCQ or the voltage VSS while the transistor TR2 is controlled to be in the on state.

[1-4] variation of embodiment 1

In the semiconductor memory device 1 of embodiment 1, the level of the voltages VCCQ, VDD, VDD and VDD2 can be appropriately changed according to the characteristics of the transistors. The signal may also be used as a signal according to the relationship between the voltages. The gate voltage at which the leakage current of the transistor becomes small is thought of in various cases depending on the characteristics of the transistor. For example, in the case where the leakage current can be suppressed by setting the reverse bias state to be strong, the value of the voltage VDD1 may be determined so as to be in the strong reverse bias state.

In addition, for example, when a transistor has a characteristic of GIDL (Gate-Induced Drain Leakage) which is large, if the transistor is in a strong reverse bias state, the leakage current may be increased as compared with the weak reverse bias state. In this case, the value of the voltage VDD1 may be determined so as to be in a weak reverse bias state. In addition, for example, when a transistor has a characteristic of GIDL, a leakage current in a weak forward bias state may be smaller than that in a reverse bias state and a zero bias state. In this case, the value of the voltage VDD1 may be determined so as to be in a weak forward bias state.

Examples are given for each of these various cases. For example, in the case of a strong reverse bias state, the voltage VDD1 is set to a voltage higher than the voltage VDD, for example. For example, in the case of a weak reverse bias state, the voltage VDD1 is set to a voltage lower than the voltage VDD and higher than the voltage VCCQ. For example, in the case of setting to a weak forward bias state, the voltage VDD1 is set to a voltage lower than the voltage VCCQ and the difference between the voltage VDD1 and the voltage VCCQ is smaller than the threshold voltage of the transistor TR7, for example.

Thus, the voltage VDD1 can be set to various magnitudes. The signal S1 may also be a signal having a voltage equal to or higher than the voltage VDD1 at the "H" level. For example, when the voltage VDD1 is equal to or lower than the voltage VDD, the signal/STBY may be used instead of the signal S1. In addition, for example, when the voltage VDD1 is equal to or lower than the voltage VDD2, the signal S2 may be used instead of the signal S1. In the case where a signal other than the signal S1 is used as the signal S1, the level shifter 42 may be omitted. In the case where signals other than the signal S1 are used as the signal S1 and the voltage VDD1 is equal to the voltage VDD, the regulator 21 may be omitted.

The voltage VDD2 and the signal S2 may be appropriately changed according to the characteristics of the transistor and the relationship between the voltages. The voltage VDD2 may be a voltage greater than the sum of the voltage VCCQ and the threshold voltage of the transistor TR 2. For example, when the voltage VDD is equal to or higher than the sum of the voltage VCCQ and the threshold voltage of the transistor TR2, the signal/STBY may be used instead of the signal S2. For example, when the voltage VDD1 is equal to or higher than the sum of the voltage VCCQ and the threshold voltage of the transistor TR2, the signal S1 may be used instead of the signal S2. In the case where the signal S2 is replaced with a signal other than the signal S2, the regulator 22 and the level shifter 43 may be omitted.

Fig. 13 shows a configuration of an output circuit 32 included in the semiconductor memory device according to a modification of embodiment 1. The output circuit 32 of the modification uses the voltage VDD instead of the voltage VDD1 and uses the signal/STBY instead of the signals S1 and S2, compared with the output circuit 32 of embodiment 1. In the semiconductor memory device according to the modification, the regulator 21 and the regulator 22 and the level shifters 42 and 43 can be omitted as compared with the semiconductor memory device 1 according to embodiment 1. This can further suppress an increase in area due to the provision of the circuit for suppressing leakage current.

[2] Embodiment 2

The semiconductor memory device 1 of embodiment 2 is different from the semiconductor memory device 1 of embodiment 1 in the configuration of the power supply circuit 18, the pre-driver 71, and the input/output control circuit 40. Hereinafter, the semiconductor memory device 1 according to embodiment 2 will be described with respect to the differences from embodiment 1.

[2-1] constitution

Fig. 14 shows an example of the configuration of the power supply circuit 18 included in the semiconductor memory device 1 according to embodiment 2. As shown in fig. 14, the power supply circuit 18 of embodiment 2 has a configuration in which the regulators 21 and 22 in the power supply circuit 18 of embodiment 1 are replaced with negative charge pumps 23 and 24, respectively.

The negative charge pump 23 generates a voltage VSS1 from the voltage VCC. The negative charge pump 24 generates a voltage VSS2 from the voltage VCC. Each of the voltages VSS1 and VSS2 is a negative voltage lower than VSS.

Fig. 15 shows an example of the configuration of output circuit 32 according to embodiment 2. As shown in fig. 15, in the output circuit 32 of embodiment 2, the pre-driver 71 includes transistors TR11 to TR16. The transistors TR11, TR13 and TR14 are, for example, P-type MOSFETs. The transistors TR12, TR15, and TR16 are, for example, N-type MOSFETs.

A voltage VCCQ is applied to each of the source and back gates of the transistor TR 11. The gate of the transistor TR11 is connected to the node N2. The drain of the transistor TR11 is connected to the node N1. Each of the source and back gate of the transistor TR12 is grounded. The gate of the transistor TR12 is connected to the node N2. The drain of the transistor TR12 is connected to the node N1.

A voltage VCCQ is applied to each of the source and back gates of the transistor TR 13. The gate of the transistor TR13 is connected to the node N4. The drain of the transistor TR13 is connected to the node N3. The source of the transistor TR14 is connected to the node N3. The voltage VCCQ is applied to the back gate of the transistor TR 14. A signal S4 is applied to the gate of the transistor TR 14. The signal S4 is a signal output by the input/output control circuit 40.

The drain of the transistor TR15 is connected to the drain of the transistor TR 14. Each of the source and back gate of the transistor TR15 is grounded. The gate of the transistor TR15 is connected to the node N4. The voltage VSS1 is applied to each of the source and back gates of the transistor TR 16. A signal S3 is applied to the gate of the transistor TR 16. The signal S3 is a signal output by the input/output control circuit 40. The drain of the transistor TR16 is connected to the node N3.

Fig. 16 shows an example of the configuration of the input/output control circuit 40 according to embodiment 2. As shown in fig. 16, the input/output control circuit 40 according to embodiment 2 has a configuration in which level shifters 42 and 43 in the input/output control circuit 40 according to embodiment 1 are replaced with level shifters 44 and 45, respectively.

The level shifter 44 outputs a signal S3 in which the voltage of the "L" level of the signal STBY is converted into the voltage VSS1. The level shifter 45 outputs a signal S4 in which the voltage of the "L" level of the signal STBY is converted into the voltage VSS 2. Other configurations of the semiconductor memory device 1 of embodiment 2 are the same as those of embodiment 1.

[2-2] operation of output Circuit 32

Next, an operation of the output circuit 32 in the semiconductor memory device 1 according to embodiment 2 will be described. In embodiment 2, it is assumed that the voltages VSS1 and VSS2 are negative voltages lower than the voltage VSS, the absolute value of the voltage VSS2 is larger than the absolute value of the voltage VSS1, and the absolute value of the voltage VSS2 is equal to or larger than the absolute value of the threshold voltage of the transistor TR 14.

Fig. 17 shows the relationship between the logic level and the voltage of various signals in the semiconductor memory device 1 according to embodiment 2. The "H" level of the signal S3 corresponds to the voltage VDD. The "L" level of the signal S3 corresponds to the voltage VSS1. The "H" level of the signal S4 corresponds to the voltage VDD. The "L" level of the signal S4 corresponds to the voltage VSS 2.

First, the operation of the pre-driver 71 according to embodiment 2 in the 1 st state will be described. In the 1 st state, the output circuit 32 is in a standby state, the logic level of the node N2 is at the "L" level, and the logic level of the node N4 is at the "H" level.

The transistor TR11 is turned on by the application of the "L" level to the gate. The transistor TR12 is turned off because the gate is applied with the "L" level. As a result, the voltage of the node N1 is determined as the voltage VCCQ by the transistor TR11 in the on state.

The transistor TR16 is turned on by the signal S3 of the voltage VDD applied to the gate. The transistor TR13 is turned off because the "H" level is applied to the gate. The transistor TR14 is turned off by the signal S4 of the voltage VDD applied to the gate. The transistor TR15 is turned off because the transistors TR13 and TR14 are turned off. As a result, the voltage of the node N3 is determined as the voltage VSS1 by the transistor TR16 in the on state.

As a result of the operation of the pre-driver 71, in the 1 st state, each of the transistors TR7 and TR8 of the main driver 80 is turned off, and the output node of the output circuit 32 is turned into a high impedance state. At this time, the voltage VSS1 is applied to the gate of the transistor TR 8.

Next, the operation of the predriver 71 according to embodiment 2 in the 2 nd state will be described in order of the case where the output circuit 32 outputs the "L" level and the case where the output circuit 32 outputs the "H" level.

In state 2, the output circuit 32 is active, the logic level of the node N2 is equal to the logic level of the signal SP, and the logic level of the node N4 is equal to the logic level of the signal SN. First, a case will be described in which the logic level of the node N2 is the "L" level, and the logic level of the node N4 is the "L" level.

The transistor TR11 is turned on by the application of the "L" level to the gate. The transistor TR12 is turned off because the gate is applied with the "L" level. As a result, the voltage of the node N1 is determined as the voltage VCCQ by TR11 in the on state.

The transistor TR16 is turned off by the signal S3 of the voltage VSS1 applied to the gate. The transistor TR13 is turned on by the application of the "L" level to the gate. The transistor TR15 is turned off because the gate is applied with the "L" level. A signal S4 of a voltage VSS2, which is a voltage equal to or higher than the threshold voltage of the transistor TR14 lower than the voltage VSS, is applied to the gate of the transistor TR 14. However, since the transistor TR15 is in an off state, the transistor TR14 does not apply a voltage to the node N3. As a result, the voltage of the node N3 is determined as the voltage VCCQ by the transistor TR13 in the on state.

As a result of the operation of the pre-driver 71, in the 2 nd state, the transistor TR7 of the main driver 80 is turned off, the transistor TR8 of the main driver 80 is turned on, and the output circuit 32 can output the "L" level of the voltage VSS.

Next, a case will be described in which the logic level of the node N2 is "H" level and the logic level of the node N4 is "H" level in the 2 nd state.

The transistor TR11 is turned off because the "H" level is applied to the gate. The transistor TR12 is turned on by the application of the "H" level to the gate. As a result, the voltage of the node N1 is determined as the voltage VSS by the transistor TR12 in the on state.

The transistor TR16 is turned off by the signal S3 of the voltage VSS1 applied to the gate. The transistor TR13 is turned off by the signal of "H" level applied to the gate. A signal S4 of a voltage VSS2, which is a voltage equal to or higher than the threshold voltage of the transistor TR14 lower than the voltage VSS, is applied to the gate of the transistor TR 14. An "H" level is applied to the gate of the transistor TR 15. Accordingly, the transistors TR14 and TR15 are turned on. As a result, the voltage of the node N3 is determined as the voltage VSS by the transistors TR14 and TR15 in the on state.

As a result of the operation of the pre-driver 71, in the 2 nd state, the transistor TR7 of the main driver 80 is turned on, the transistor TR8 of the main driver 80 is turned off, and the output circuit 32 can output the "H" level of the voltage VCCQ.

As described above, the output circuit 32 in the semiconductor memory device 1 according to embodiment 2 can control the voltage of the node N3 to the voltage VSS or the voltage VCCQ in the active state, and output the "L" level or the "H" level to the output node.

[2-3] Effect of embodiment 2

As described above, in the semiconductor memory device 1 according to embodiment 2, the negative voltage VSS1 is applied to the node N3 in the standby state. In this way, in the semiconductor memory device 1 according to embodiment 2, the transistor TR8 in the standby state is in the reverse bias state, and the leakage current of the transistor TR8 can be suppressed. As a result, the semiconductor memory device 1 of embodiment 2 can suppress power consumption of the semiconductor memory device 1 in the standby state, as in embodiment 1.

In the semiconductor memory device 1 according to embodiment 2, the level of the voltages VSS1 and VSS2 can be changed appropriately according to the characteristics of the transistors. The signal may also be used as a signal according to the relationship between the voltages. For example, the voltage VSS1 may be set to a voltage higher than the voltage VSS and lower than the threshold voltage of the transistor TR8 so that the transistor TR8 is biased in a weak forward direction. In this case, a regulator may also be used instead of the negative charge pump 23 to generate the voltage VSS1. In addition, in this case, the signal STBY or the signal S4 may be used instead of the signal S3.

[3] Embodiment 3

The semiconductor memory device 1 of embodiment 3 is different from the semiconductor memory device 1 of embodiment 1 in the configuration of the predriver 72 and the input/output control circuit 40. Hereinafter, the semiconductor memory device 1 according to embodiment 3 will be described with respect to the differences from embodiment 1.

[3-1] constitution

Fig. 18 shows an example of the configuration of output circuit 32 according to embodiment 3. As shown in fig. 18, in the output circuit 32 of embodiment 3, the pre-driver 72 has a configuration in which the transistor TR4 in the pre-driver 70 of embodiment 1 is replaced with a current source CS1, a resistor R1, and a transistor TR 9.

The voltage VDD1 is applied to the current source CS1, and a current is supplied to the node N1 based on the signal STBY. One end of the resistor R1 is connected to the node N1. The drain of the transistor TR9 is connected to the other end of the resistor R1. Each of the source and the back gate of the transistor TR9 is grounded. A signal S5 is applied to the gate of the transistor TR 9. The signal S5 is a signal output by the input/output control circuit 40.

Fig. 19 shows an example of the configuration of the input/output control circuit 40 according to embodiment 3. As shown in fig. 19, the input/output control circuit 40 according to embodiment 3 has a configuration in which an inverter 46 is added to the input/output control circuit 40 according to embodiment 1. Inverter 46 outputs a signal S5 in which signal S1 is logically inverted. Other configurations of the semiconductor memory device 1 of embodiment 3 are the same as those of embodiment 1.

Operation of the output circuit 32

Next, an operation of the output circuit 32 in the semiconductor memory device 1 according to embodiment 3 will be described. Note that in embodiment 3, as in the description of embodiment 1, it is assumed that voltage VCC is larger than voltages VDD, VDD1, and VDD2, voltage VDD1 is larger than voltage VDD, voltage VDD2 is larger than voltages VDD and VDD1, and voltage VDD2 is equal to or larger than the sum of voltage VCCQ and the threshold voltage of transistor TR 2.

Fig. 20 shows the relationship between the logic level and the voltage of various signals in the semiconductor memory device 1 according to embodiment 3. The "H" level of the signal S5 corresponds to the voltage VDD 1. The "L" level of the signal S5 corresponds to the voltage VSS.

In addition, when the signal STBY is at the "H" level, the current source CS1 supplies a current to the node N1. When the signal STBY is at the "L" level, the current source CS1 does not supply current to the node N1, and is not electrically connected to the node N1.

The operation of the pre-driver 72 according to embodiment 3 in the 1 st state will be described. In the 1 st state, the output circuit 32 is in a standby state, the transistors TR1, TR2, TR3, and TR5 are in an off state, and the transistor TR6 is in an on state.

Since the signal STBY is at the "H" level, the current source CS1 supplies a current from the voltage VDD1 to the node N1. The transistor TR9 is turned on by the signal S5 of the voltage VDD1 applied to the gate. As a result, the current supplied from the voltage VDD1 by the current source CS1 flows to the voltage VSS via the resistor R1 and the transistor TR 9. A voltage difference is generated across the resistor R1 by passing a current through the resistor R1. The voltage at the node N1 becomes, for example, a voltage VDD3 which is a voltage greater than the voltage VCCQ and equal to or lower than the voltage VDD1 by the voltage difference generated across the resistor R1. The voltage at the node N3 is determined as the voltage VSS by the transistor TR6 in the on state.

As a result of the operation of the pre-driver 72, in the 1 st state, each of the transistors TR7 and TR8 of the main driver 80 is turned off, and the output node of the output circuit 32 is turned into a high impedance state. At this time, the voltage VDD3 is applied to the gate of the transistor TR 7.

Next, the operation of the predriver 72 according to embodiment 3 in the 2 nd state will be described. In state 2, the output circuit 32 is active.

Since the signal STBY is at the "L" level, the current source CS1 does not supply current to the node N1, and is not electrically connected to the node N1. The transistor TR9 is turned off by the signal S5 of the voltage VSS applied to the gate. As a result, the voltage of the node N1 is determined by the transistors TR1, TR2, and TR3, and the voltage of the node N3 is determined by the transistors TR5 and TR 6. That is, in the 2 nd state, the pre-driver 72 of the 3 rd embodiment operates in the same manner as the pre-driver 70 of the 1 st embodiment in the 2 nd state.

For example, in the 2 nd state, when the logic level of the node N2 is the "L" level and the logic level of the node N4 is the "L" level, the transistors TR1, TR2, and TR5 are turned on, and the transistors TR3 and TR6 are turned off. As a result, the voltage of the node N1 becomes the voltage VCCQ, and the voltage of the node N3 becomes the voltage VCCQ. In addition, for example, in the 2 nd state, when the logic level of the node N2 is "H" level and the logic level of the node N4 is "H" level, the transistors TR1, TR2, and TR5 are turned off, and the transistors TR3 and TR6 are turned on. As a result, the voltage at the node N1 becomes the voltage VSS, and the voltage at the node N3 becomes the voltage VSS.

In this way, the output circuit 32 in the semiconductor memory device 1 according to embodiment 3 can control the voltage at the node N1 to the voltage VCCQ or the voltage VSS in the active state, and output the "L" level or the "H" level to the output node.

[3-3] Effect of embodiment 3

As described above, in the semiconductor memory device 1 according to embodiment 3, the voltage VDD3 equal to or higher than the voltage VCCQ is applied to the node N1 in the standby state. In the semiconductor memory device 1 according to embodiment 3, the transistor TR7 in the standby state is in the reverse bias state, and the leakage current of the transistor TR7 can be suppressed. As a result, the semiconductor memory device 1 of embodiment 3 can suppress power consumption of the semiconductor memory device 1 in the standby state, as in embodiment 1.

In the semiconductor memory device 1 according to embodiment 3, the level of the voltages VDD1, VDD2, and VDD3 can be appropriately changed according to the characteristics of the transistors. The amount of current supplied from the current source CS1 and the resistance value of the resistor R1 may be appropriately changed according to the characteristics of the transistor. The signal may also be used as a signal according to the relationship between the voltages.

For example, the voltage VDD3 may be set to a voltage lower than the voltage VCCQ so that the transistor TR7 is biased in a weak forward direction. In this case, in order to set the voltage VDD3, for example, the amount of current supplied from the current source CS1 may be changed, the resistance value of the resistor R1 may be changed, or the magnitude of the voltage VDD1 may be changed together with the amount of current of the current source CS1 and the resistance value of the resistor R1.

[4] Embodiment 4

The semiconductor memory device 1 of embodiment 4 is different from the semiconductor memory device 1 of embodiment 2 in the configuration of the predriver 73 and the input/output control circuit 40. Hereinafter, the semiconductor memory device 1 according to embodiment 3 will be described with respect to the differences from embodiment 2.

[4-1] constitution

Fig. 21 shows an example of the configuration of output circuit 32 according to embodiment 4. As shown in fig. 21, in the output circuit 32 of embodiment 4, the pre-driver 73 has a configuration in which the transistor TR16 in the pre-driver 71 of embodiment 2 is replaced with a current source CS2, a resistor R2, and a transistor TR 17.

The voltage VSS1 is applied to the current source CS2, and a current is supplied from the node N3 to the voltage VSS1 based on the signal STBY. One end of the resistor R2 is connected to the node N3. The drain of the transistor TR17 is connected to the other end of the resistor R2. A voltage VCCQ is applied to each of the source and back gates of the transistor TR 17. A signal S6 is applied to the gate of the transistor TR 17. The signal S6 is a signal output by the input/output control circuit 40.

Fig. 22 shows an example of the configuration of the input/output control circuit 40 according to embodiment 4. As shown in fig. 22, the input/output control circuit 40 according to embodiment 4 has a configuration in which an inverter 47 is added to the input/output control circuit 40 according to embodiment 2. Inverter 47 outputs signal S6 in which signal S3 is logically inverted. Other configurations of the semiconductor memory device 1 of embodiment 4 are the same as those of embodiment 2.

[4-2] operation of output Circuit 32

Next, an operation of the output circuit 32 in the semiconductor memory device 1 according to embodiment 4 will be described. Note that in embodiment 4, as in the case of embodiment 2, voltages VSS1 and VSS2 are negative voltages lower than voltage VSS, the absolute value of voltage VSS2 is larger than the absolute value of voltage VSS1, and the absolute value of voltage VSS2 is equal to or larger than the absolute value of the threshold voltage of transistor TR 14.

Fig. 23 shows the relationship between the logic level and the voltage of various signals in the semiconductor memory device 1 according to embodiment 4. The "L" level of the signal S6 corresponds to the voltage VSS 1. The "H" level of the signal S6 corresponds to the voltage VDD.

When the signal STBY is at the "H" level, the current source CS2 supplies a current from the node N3 to the voltage VSS 1. When the signal STBY is at the "L" level, the current source CS2 is not supplied with current from the node N3 to the voltage VSS1, and is not electrically connected to the node N3.

First, the operation of the pre-driver 73 according to embodiment 4 in the 1 st state will be described. In the 1 st state, the output circuit 32 is in a standby state, the transistor TR11 is in an on state, and the transistors TR12, TR13, TR14, and TR15 are in an off state.

Since the signal STBY is at the "H" level, the current source CS2 supplies a current from the node N3 to the voltage VSS1. The transistor TR17 is turned on by the signal S6 of the voltage VSS1 applied to the gate. As a result, the current flowing from the voltage VCCQ to the node N3 through the transistor TR17 and the resistor R2 is supplied from the node N3 to the voltage VSS1 by the current source CS 2. A voltage difference is generated across the resistor R2 by passing a current through the resistor R2. The voltage at the node N3 is a negative voltage due to the voltage difference generated across the resistor R2, and becomes a voltage VSS3 higher than the voltage VSS1. In addition, the voltage of the node N1 is determined as the voltage VCCQ by the transistor TR11 in the on state.

As a result of the operation of the pre-driver 73, in the 1 st state, each of the transistors TR7 and TR8 of the main driver 80 is turned off, and the output node of the output circuit 32 is turned into a high impedance state. At this time, the voltage VSS3 is applied to the gate of the transistor TR 8.

Next, the operation of the pre-driver 73 of embodiment 4 in the 2 nd state will be described. In state 2, the output circuit 32 is active.

Since the signal STBY is at the "L" level, the current source CS2 is not supplied with current from the node N3 to the voltage VSS1, and is not electrically connected to the node N3. The transistor TR17 is turned off by the signal S6 of the voltage VDD applied to the gate. As a result, the voltage of the node N3 is determined by the transistors TR13, TR14, and TR 15. That is, in the 2 nd state, the pre-driver 73 of the 4 th embodiment operates in the same manner as the pre-driver 71 of the 2 nd embodiment in the 2 nd state.

For example, in the 2 nd state, when the logic level of the node N2 is the "L" level and the logic level of the node N4 is the "L" level, the transistors TR11 and TR13 are turned on, and the transistors TR12, TR14 and TR15 are turned off. As a result, the voltage of the node N1 becomes the voltage VCCQ, and the voltage of the node N3 becomes the voltage VCCQ. In addition, for example, in the 2 nd state, when the logic level of the node N2 is "H" level and the logic level of the node N4 is "H" level, the transistors TR11 and TR13 are turned off, and the transistors TR12, TR14 and TR15 are turned on. As a result, the voltage at the node N1 becomes the voltage VSS, and the voltage at the node N3 becomes the voltage VSS.

In this way, the output circuit 32 in the semiconductor memory device 1 according to embodiment 4 can control the voltage at the node N3 to the voltage VCCQ or the voltage VSS in the active state, and output the "L" level or the "H" level to the output node.

[4-3] Effect of embodiment 4

As described above, in the semiconductor memory device 1 according to embodiment 4, the voltage VDD3, which is a negative voltage, is applied to the node N3 in the standby state. In the semiconductor memory device 1 according to embodiment 4, the transistor TR8 in the standby state is in the reverse bias state, and the leakage current of the transistor TR8 can be suppressed. As a result, the semiconductor memory device 1 of embodiment 4 can suppress power consumption of the semiconductor memory device 1 in the standby state, as in embodiment 2.

In the semiconductor memory device 1 according to embodiment 4, the voltages VSS1, VSS2, and VSS3 may be appropriately changed according to the characteristics of the transistors. The amount of current supplied from the current source CS2 and the resistance value of the resistor R2 may be appropriately changed according to the characteristics of the transistor. The signal may also be used as a signal according to the relationship between the voltages.

For example, the voltage VSS3 may be set to a voltage higher than the voltage VSS so that the transistor TR8 is biased in a weak forward direction. In this case, in order to set the voltage VSS3, for example, the amount of current supplied from the current source CS2 may be changed, the resistance value of the resistor R2 may be changed, or the magnitude of the voltage VSS1 may be changed together with the amount of current from the current source CS2 and the resistance value of the resistor R2.

[5] Embodiment 5

The semiconductor memory device 1 of embodiment 5 is different from the semiconductor memory device 1 of embodiment 1 in the configuration of the power supply circuit 18, the pre-driver 74, and the input/output control circuit 40. Hereinafter, the semiconductor memory device 1 according to embodiment 5 will be described with respect to the differences from embodiment 1.

[5-1] constitution

The power supply circuit 18 included in the semiconductor memory device 1 of embodiment 5 has a configuration in which the regulator 22 is omitted from the power supply circuit 18 included in the semiconductor memory device 1 of embodiment 1.

Fig. 24 shows an example of the configuration of output circuit 32 according to embodiment 5. As shown in fig. 24, in the output circuit 32 of embodiment 5, the pre-driver 74 includes transistors TR21 to TR24 and a level shifter 91. The transistors TR21 and TR23 are, for example, P-type MOSFETs. The transistors TR22 and TR24 are, for example, N-type MOSFETs.

The voltage VDD1 is applied to each of the source and back gate of the transistor TR 21. The drain of the transistor TR21 is connected to the node N1. Each of the source and the back gate of the transistor TR22 is grounded. The drain of the transistor TR22 is connected to the node N1. The level shifter 91 applies a signal based on the logic level of the node N2 to the gate of the transistor TR21 and the gate of the transistor TR 22. A voltage VCCQ is applied to each of the source and back gates of the transistor TR 23. The gate of the transistor TR23 is connected to the node N4. The drain of the transistor TR23 is connected to the node N3. Each of the source and back gate of the transistor TR24 is grounded. The gate of the transistor TR24 is connected to the node N4. The drain of the transistor TR24 is connected to the node N3.

The input/output control circuit 40 included in the semiconductor memory device 1 of embodiment 5 has a configuration in which the level shifters 42 and 43 are omitted from the input/output control circuit 40 included in the semiconductor memory device 1 of embodiment 1. Other configurations of the semiconductor memory device 1 of embodiment 5 are the same as those of embodiment 1.

[5-2] operation of output Circuit 32

Next, an operation of the output circuit 32 in the semiconductor memory device 1 according to embodiment 5 will be described. In embodiment 5, it is assumed that voltage VDD1 is higher than voltage VCCQ.

First, the operation of the predriver 74 according to embodiment 5 in the 1 st state will be described. In the 1 st state, the output circuit 32 is in a standby state, the logic level of the node N2 is at the "L" level, and the logic level of the node N4 is at the "H" level.

The level shifter 91 outputs the "L" level of the voltage VSS to the gate of the transistor TR21 and the gate of the transistor TR22 based on the "L" level of the node N2. The transistor TR21 is turned on by the application of the "L" level to the gate. The transistor TR22 is turned off because the gate is applied with the "L" level. As a result, the voltage of the node N1 is determined as the voltage VDD1 by the transistor TR21 in the on state.

The transistor TR23 is turned off because the "H" level is applied to the gate. The transistor TR24 is turned on by the application of the "H" level to the gate. As a result, the voltage of the node N3 is determined as the voltage VSS by the transistor TR24 in the on state.

As a result of the operation of the pre-driver 74, in the 1 st state, each of the transistors TR7 and TR8 of the main driver 80 is turned off, and the output node of the output circuit 32 is turned into a high impedance state. At this time, the voltage VDD1 is applied to the gate of the transistor TR 7.

Next, the operation of the predriver 74 in the 2 nd state of embodiment 5 will be described in order of the case where the output circuit 32 outputs the "L" level and the case where the output circuit 32 outputs the "H" level.

In state 2, the output circuit 32 is active, the logic level of the node N2 is equal to the logic level of the signal SP, and the logic level of the node N4 is equal to the logic level of the signal SN. First, a case will be described in which the logic level of the node N2 is the "L" level, and the logic level of the node N4 is the "L" level.

The level shifter 91 outputs the "L" level of the voltage VSS to the gate of the transistor TR21 and the gate of the transistor TR22 based on the "L" level of the node N2. The transistor TR21 is turned on by the application of the "L" level to the gate. The transistor TR22 is turned off because the gate is applied with the "L" level. As a result, the voltage of the node N1 is determined as the voltage VDD1 by the transistor TR21 in the on state.

The transistor TR23 is turned on by the application of the "L" level to the gate. The transistor TR24 is turned off because the gate is applied with the "L" level. As a result, the voltage of the node N3 is determined as the voltage VCCQ by the transistor TR23 in the on state.

As a result of the operation of the pre-driver 74, in the 2 nd state, the transistor TR7 of the main driver 80 is turned off, the transistor TR8 of the main driver 80 is turned on, and the output circuit 32 can output the "L" level of the voltage VSS.

Next, a case will be described in which the logic level of the node N2 is the "H" level, and the logic level of the node N4 is the "H" level.

The level shifter 91 outputs the "H" level of the voltage VDD1 to the gate of the transistor TR21 and the gate of the transistor TR22 based on the "H" level of the node N2. The transistor TR21 is turned off because the "H" level is applied to the gate. The transistor TR22 is turned on by the application of the "H" level to the gate. As a result, the voltage of the node N1 is determined as the voltage VSS by the transistor TR22 in the on state.

The transistor TR23 is turned off because the "H" level is applied to the gate. The transistor TR24 is turned on by the application of the "H" level to the gate. As a result, the voltage of the node N3 is determined as the voltage VSS by the transistor TR24 in the on state.

As a result of the operation of the pre-driver 74, in the 2 nd state, the transistor TR7 of the main driver 80 is turned on, the transistor TR8 of the main driver 80 is turned off, and the output circuit 32 can output the "H" level of the voltage VCCQ.

As described above, the output circuit 32 in the semiconductor memory device 1 according to embodiment 5 can control the voltage of the node N1 to be the voltage VSS or the voltage VDD1 in the active state, and output the "L" level or the "H" level to the output node.

[5-3] Effect of embodiment 5

As described above, in the semiconductor memory device 1 according to embodiment 5, the voltage VDD1 equal to or higher than the voltage VCCQ is applied to the node N1 in the standby state. In the semiconductor memory device 1 according to embodiment 5, the transistor TR7 in the standby state is in the reverse bias state, and the leakage current of the transistor TR7 can be suppressed. As a result, the semiconductor memory device 1 of embodiment 5 can suppress power consumption of the semiconductor memory device 1 in the standby state, as in embodiment 1.

The level of the voltage VDD1 may be appropriately changed according to the characteristics of the transistor. For example, the voltage VDD1 may be set to a voltage lower than the voltage VCCQ so that the transistor TR7 is biased in a weak forward direction.

[6] Embodiment 6

The semiconductor memory device 1 according to embodiment 6 is different from the semiconductor memory device 1 according to embodiment 2 in the configuration of the power supply circuit 18, the pre-driver 75, and the input/output control circuit 40. Hereinafter, the semiconductor memory device 1 according to embodiment 6 will be described with respect to the differences from embodiment 2.

[6-1] constitution

The power supply circuit 18 included in the semiconductor memory device 1 according to embodiment 6 has a configuration in which the negative charge pump 24 is omitted from the power supply circuit 18 included in the semiconductor memory device 1 according to embodiment 2.

Fig. 25 shows an example of the configuration of output circuit 32 according to embodiment 6. As shown in fig. 25, in the output circuit 32 of embodiment 6, the pre-driver 75 includes transistors TR25 to TR28 and a level shifter 92. The transistors TR25 and TR27 are, for example, P-type MOSFETs. The transistors TR26 and TR28 are, for example, N-type MOSFETs.

A voltage VCCQ is applied to each of the source and back gates of the transistor TR 25. The gate of the transistor TR25 is connected to the node N2. The drain of the transistor TR25 is connected to the node N1. Each of the source and back gate of the transistor TR26 is grounded. The gate of the transistor TR26 is connected to the node N2. The drain of the transistor TR24 is connected to the node N1. A voltage VCCQ is applied to each of the source and back gates of the transistor TR 27. The drain of the transistor TR27 is connected to the node N3. The voltage VSS1 is applied to each of the source and back gates of the transistor TR 28. The drain of the transistor TR28 is connected to the node N3. The level shifter 92 applies a signal based on the logic level of the node N4 to the gate of the transistor TR27 and the gate of the transistor TR 28.

The input/output control circuit 40 included in the semiconductor memory device 1 according to embodiment 6 has a configuration in which level shifters 44 and 45 are omitted from the input/output control circuit 40 included in the semiconductor memory device 1 according to embodiment 2. Other configurations of the semiconductor memory device 1 of embodiment 6 are the same as those of embodiment 2.

[6-2] operation of output Circuit 32

Next, an operation of the output circuit 32 in the semiconductor memory device 1 according to embodiment 6 will be described. In embodiment 6, the voltage VSS1 is assumed to be a negative voltage.

First, the operation of the pre-driver 75 according to embodiment 6 in the 1 st state will be described. In the 1 st state, the output circuit 32 is in a standby state, the logic level of the node N2 is at the "L" level, and the logic level of the node N4 is at the "H" level.

The transistor TR25 is turned on by the application of the "L" level to the gate. The transistor TR26 is turned off because the gate is applied with the "L" level. As a result, the voltage of the node N1 is determined as the voltage VCCQ by the transistor TR25 in the on state.

The level shifter 92 outputs the "H" level of the voltage VCCQ to the gate of the transistor TR27 and the gate of the transistor TR28 based on the "H" level of the node N4. The transistor TR27 is turned off because the "H" level is applied to the gate. The transistor TR28 is turned on by the application of the "H" level to the gate. As a result, the voltage of the node N3 is determined as the voltage VSS1 by the transistor TR28 in the on state.

As a result of the operation of the pre-driver 75, in the 1 st state, each of the transistors TR7 and TR8 of the main driver 80 is turned off, and the output node of the output circuit 32 is turned into a high impedance state. At this time, the voltage VSS1 is applied to the gate of the transistor TR 8.

Next, the operation of the predriver 75 according to embodiment 6 in the 2 nd state will be described in order of the case where the output circuit 32 outputs the "L" level and the case where the output circuit 32 outputs the "H" level.

In state 2, the output circuit 32 is active, the logic level of the node N2 is equal to the logic level of the signal SP, and the logic level of the node N4 is equal to the logic level of the signal SN. First, a case will be described in which the logic level of the node N2 is the "L" level, and the logic level of the node N4 is the "L" level.

The transistor TR25 is turned on by the application of the "L" level to the gate. The transistor TR26 is turned off because the gate is applied with the "L" level. As a result, the voltage of the node N1 is determined as the voltage VCCQ by the transistor TR25 in the on state.

The level shifter 92 outputs the "L" level of the voltage VSS1 to the gate of the transistor TR27 and the gate of the transistor TR28 based on the "L" level of the node N4. The transistor TR27 is turned on by the application of the "L" level to the gate. The transistor TR28 is turned off because the gate is applied with the "L" level. As a result, the voltage of the node N1 is determined as the voltage VCCQ by the transistor TR27 in the on state.

As a result of the operation of the pre-driver 75, in the 2 nd state, the transistor TR7 of the main driver 80 is turned off, the transistor TR8 of the main driver 80 is turned on, and the output circuit 32 can output the "L" level of the voltage VSS.

Next, a case will be described in which the logic level of the node N2 is the "H" level, and the logic level of the node N4 is the "H" level.

The transistor TR25 is turned off because the "H" level is applied to the gate. The transistor TR26 is turned on by the application of the "H" level to the gate. As a result, the voltage of the node N1 is determined as the voltage VSS by the transistor TR26 in the on state.

The level shifter 92 outputs the "H" level of the voltage VCCQ to the gate of the transistor TR27 and the gate of the transistor TR28 based on the "H" level of the node N4. The transistor TR27 is turned off because the "H" level is applied to the gate. The transistor TR28 is turned on by the application of the "H" level to the gate. As a result, the voltage of the node N1 is determined as the voltage VSS1 by the transistor TR28 in the on state.

As a result of the operation of the pre-driver 75 in this way, in the 2 nd state, the transistor TR7 of the main driver 80 is turned on, the transistor TR8 of the main driver 80 is turned off, and the output circuit 32 can output the "H" level of the voltage VCCQ.

As described above, the output circuit 32 in the semiconductor memory device 1 according to embodiment 6 can control the voltage of the node N3 to be VSS1 or VCCQ in the active state, and output the "L" level or "H" level to the output node.

[6-3] Effect of embodiment 6

As described above, in the semiconductor memory device 1 according to embodiment 6, the negative voltage VSS1 is applied to the node N3 in the standby state. In the semiconductor memory device 1 according to embodiment 6, the transistor TR8 in the standby state is in the reverse bias state, and the leakage current of the transistor TR8 can be suppressed. As a result, the semiconductor memory device 1 of embodiment 6 can suppress power consumption of the semiconductor memory device 1 in the standby state, as in embodiment 2.

The level of the voltage VSS1 may be changed as appropriate according to the characteristics of the transistor. For example, the voltage VSS1 may be set to a positive voltage so that the transistor TR8 is biased in a weak forward direction.

[7] Other variations and the like

In the above embodiment, the case where the output circuit 32 can take the standby state and the active state 2 states is exemplified, but the operation state of the output circuit 32 is not limited to these. The output circuit 32 may be in a state different from the standby state and the active state. In the above embodiment, the case where the output circuit 32 is controlled by the signal STBY based on the signal/CE is exemplified, but the signal controlling the output circuit 32 is not limited to the signal STBY. The output circuit 32 may operate based on a signal other than the signal STBY, for example.

In the above embodiment, the case where the semiconductor memory device 1 operates using the voltage supplied from the outside and the input/output module 10 operates using the voltage generated by the power supply circuit 18 is exemplified. These voltages may also be supplied to the respective circuit blocks through wiring lines called, for example, power supply lines. For example, the semiconductor memory device 1 may include a power supply line of the voltage VCCQ, a power supply line of the voltage VSS, a power supply line of the voltage VDD1, a power supply line of the voltage VDD2, and the like. For example, a plurality of circuits that operate using the voltage VCCQ may be connected to a power supply line that supplies the voltage VCCQ.

In the embodiment, a case where the pre-driver 70 includes a transistor capable of suppressing the PN junction from being turned on is exemplified. Each of the transistor TR2 included in the semiconductor memory device 1 of embodiment 1 and the transistor TR14 included in the semiconductor memory device 1 of embodiment 2 is an example of a transistor that suppresses the PN junction from being turned on. The configuration of the pre-driver 70 is not limited to the configuration including the transistor that suppresses the PN junction from being turned on. For example, when the transistors included in the main driver 80 are set to the forward bias state in the standby state, the transistors that suppress the PN junction from being turned on may be omitted to construct the pre-driver 70.

In the above embodiment, the case where the main driver 80 includes the transistors TR7 and TR8 is exemplified, but the configuration of the main driver 80 is not limited to this. Fig. 26 shows an example of the configuration of a main driver 80 included in the semiconductor memory device 1 according to the modification of embodiment 1. As shown in fig. 26, the main driver 80 included in the semiconductor memory device 1 according to the modification of embodiment 1 further includes resistors R3 and R4 with respect to the main driver 80 included in the semiconductor memory device 1 according to embodiment 1. Resistor R3 is disposed between the drain of transistor TR7 and the output node of main driver 80. Resistor R4 is provided between the drain of transistor TR8 and the output node of main driver 80. With this configuration, the output impedance of the main driver 80 included in the semiconductor memory device 1 according to the variation of embodiment 1 is based on the on-resistance of the transistor TR7 and the resistance value of the resistor R3 or the on-resistance of the transistor TR8 and the resistance value of the resistor R4.

The on-resistance of the transistor may vary depending on the operating state of the transistor, such as the drain-source voltage or the gate-source voltage. The resistance value of the resistor is less susceptible to the magnitude of the voltage difference applied across the resistor than the on-resistance of the transistor. Thus, by determining the output impedance from the transistor and the resistor, it is possible to suppress the fluctuation of the output impedance caused by the change of the operation state of the transistor. The master drive 80 included in embodiment 1 can be modified in this way. The master drive 80 included in the other embodiments may be similarly modified.

The pre-driver 70 illustrated in the embodiment may further include a plurality of inverters, for example. Fig. 27 shows an example of the configuration of a predriver 76 included in the semiconductor memory device 1 according to the modification of embodiment 1. As shown in fig. 27, the predriver 76 included in the semiconductor memory device 1 of the modification of embodiment 1 further includes transistors TR31 to TR38, with respect to the predriver 70 included in embodiment 1. Each of the transistors TR31, TR33, TR35, and TR37 is, for example, a P-type MOSFET. Each of the transistors TR32, TR34, TR36, and TR38 is, for example, an N-type MOSFET.

The voltage VCCQ is applied to the source and back gate of the transistor TR 31. The source and back gate of the transistor TR32 are grounded. The gate of the transistor TR31 and the gate of the transistor TR32 are each connected to the node N2. The voltage VCCQ is applied to the source and back gate of the transistor TR 33. The source and back gate of transistor TR34 are grounded. Each of the gate of the transistor TR33 and the gate of the transistor TR34 is connected to each of the drain of the transistor TR31 and the drain of the transistor TR 32. The drain of the transistor TR33 and the drain of the transistor TR34 are each connected to the gate of the transistor TR1 and the gate of the transistor TR 3.

The voltage VCCQ is applied to the source and back gate of the transistor TR 35. The source and back gate of transistor TR36 are grounded. The gate of the transistor TR35 and the gate of the transistor TR36 are each connected to the node N4. A voltage VCCQ is applied to the source and back gate of the transistor TR 37. The source and back gate of transistor TR38 are grounded. Each of the gate of the transistor TR37 and the gate of the transistor TR38 is connected to each of the drain of the transistor TR35 and the drain of the transistor TR 36. The drain of the transistor TR37 and the drain of the transistor TR38 are each connected to the gate of the transistor TR5 and the gate of the transistor TR 6.

The configuration of the pre-driver 76 may be modified to be a configuration in which an inverter is added to the pre-driver 70 included in embodiment 1. Specifically, the transistors TR31 and TR32 constitute an inverter. The transistors TR33 and TR34 constitute an inverter. The transistors TR35 and TR36 constitute an inverter. The transistors TR37 and TR38 constitute an inverter. 2 inverters are provided in series between the output of the AND gate 61 AND the gates of the transistors TR1 AND TR 3. 2 inverters are provided in series between the output of the OR gate 62 and the gates of the transistors TR5 and TR 6.

By configuring the pre-driver 76 in this way, the ability to control the voltage at the node N1 and the voltage at the node N3 can be improved in the active state. For example, the signal passes through a plurality of inverters connected in series, whereby the rising and falling of the signal can be adjusted. Further, for example, by providing a plurality of inverters in such a manner that the driving force of the inverters is increased stepwise, the size of the transistors constituting the inverters becomes larger as the transistors are transferred from the logic unit 60 side to the main driver 80 side. By increasing the driving force of the inverter stepwise, for example, even when the size of the transistors TR7 and TR8 of the main driver 80 is large and the parasitic capacitance is large, the voltage of the node N1 and the voltage of the node N3 can be controlled.

The output circuit 32 shown in the embodiment may also include a plurality of logic sections, a set of pre-drivers and a main driver. Fig. 28 shows an example of the configuration of the output circuit 32 included in the semiconductor memory device 1 according to the modification of embodiment 1. The output circuit 32 included in the modification of embodiment 1 includes: a group of logic units 60-0, predriver 70-0, and main driver 80-0; a group of logic units 60-1, predriver 70-1, and main driver 80-1; a set of logic 60-2, predriver 70-2, and main driver 80-2; and a set of logic 60-3, pre-driver 70-3, and main driver 80-3. The output node of the main driver 80-0, the output node of the main driver 80-1, the output node of the main driver 80-2, and the output node of the main driver 80-3 are each commonly connected to the pad 50. The output impedance of the output circuit 32 may be controlled by changing the number of active groups of the logic unit, the pre-driver, and the main driver, for example.

In the above embodiment, the case where the semiconductor memory device 1 is a NAND flash memory has been described as an example, but the present invention is not limited thereto. The output circuit 32 described in the embodiment is applicable to all devices having a configuration for outputting a signal.

In the above embodiment, the description has been made of the case where the power consumption can be suppressed in the standby state. The power consumption can be suppressed by, for example, a predriver. For example, when transistors TR7 and TR8 of the main driver 80 are used with transistors having a low threshold voltage, the size of the transistors can be reduced as compared with transistors having a high threshold voltage, and parasitic capacitance in the gates of the transistors can be reduced. The transistors constituting the pre-driver are set to a size capable of controlling the gate voltages of the transistors TR7 and TR8 of the main driver 80, respectively. In the case where the size of the transistors TR7 and TR8 is small, the size of the transistors constituting the pre-driver can be reduced. If the size of the transistor constituting the pre-driver becomes small, power consumed in transmitting a signal can be suppressed as compared with the case of being constituted by a transistor having a large size.

In the embodiment, a case where the leakage current increases due to GIDL is exemplified. GIDL is a current generated due to band-to-band tunneling in a region where a gate electrode and a drain electrode of a transistor are disposed to overlap. GIDL sometimes becomes apparent, for example, with a reverse bias applied between the gate and drain. The phenomenon related to the leakage current of the transistor is not limited to GIDL.

In this specification, a state in which the gate-source voltage of the transistor exceeds the threshold voltage is described as the transistor being in an "on state". In addition, the on state may be modified to be a "stronger forward bias state". A state in which the gate-source voltage of the transistor is less than the threshold voltage is described as the transistor being in a "weaker forward bias state". The state where the gate-source voltage of the transistor is approximately 0V is described as the transistor being in a "zero bias state". The transistor is described as being in a "reverse bias state" when the gate-source voltage of the transistor is applied with a polarity opposite to the threshold voltage. The "stronger reverse bias state" and the "weaker reverse bias state" can also be described relatively according to the magnitude of the reverse bias. In each of the weaker forward bias state, zero bias state and reverse bias state, the transistor is in an off state.

Here, a case where 1.8V is applied to the source will be described as an example of a P-type MOSFET having a threshold voltage of-0.6V. When the voltage of the gate is 0V, the gate-source voltage is-1.8V, and the gate is turned on, and the gate is in a strong forward bias state. In the case where the gate voltage is 1.5V, the gate-source voltage is-0.3V, which is a weak forward bias state. In the case where the voltage of the gate is 1.8V, the gate-source voltage is 0V, and the bias state is zero. When the voltage of the gate is 2.1V, the gate-source voltage is 0.3V, and the reverse bias state is established. When the voltage of the gate is 3.6V, the gate-source voltage is 1.8V, and the reverse bias state is established. The situation in which the voltage of the gate is 3.6V may be described as a stronger reverse bias state and the situation in which the voltage of the gate is 2.1V may be described as a reverse bias state by comparing the situation in which the voltage of the gate is 3.6V with the situation in which the voltage of the gate is 2.1V.

Here, an N-type MOSFET having a threshold voltage of 0.6V will be described by taking a case where the source is grounded as an example. When the voltage of the gate is 1.8V, the gate-source voltage is 1.8V, and the on state is a strong forward bias state. In the case where the voltage of the gate is 0.3V, the gate-source voltage is 0.3V, and the forward bias state is weak. When the voltage of the gate is 0V, the gate-source voltage is 0V, and the bias state is zero. When the voltage of the gate is-0.3V, the gate-source voltage is-0.3V, and the reverse bias state is established. When the voltage of the gate is-1.8V, the gate-source voltage is-1.8V, and the reverse bias state is established. The situation where the voltage of the gate is-1.8V is described as a stronger reverse bias state and the situation where the voltage of the gate is-0.3V is described as a weaker reverse bias state by comparing the situation where the voltage of the gate is-0.3V with the situation where the voltage of the gate is-1.8V.

In this specification, when the transistor is in an off state, a current flowing between a source and a drain of the transistor is referred to as a leakage current. For example, the current flowing between the source and the drain of the transistor is referred to as leakage current in the case where the transistor is in a weak forward bias state, in the case where the transistor is in a zero bias state, in the case where the transistor is in a weak reverse bias state, and in the case where the transistor is in a strong reverse bias state.

In this specification, "connected" means electrically connected, except for the case where other elements are interposed, for example. In addition, the insulating body may be interposed as long as the "electrical connection" can be operated in the same manner as the electrical connection.

In this specification, each of the source and drain of a transistor may also be referred to as a terminal of the transistor. For example, the 1 st terminal of the transistor is a source or drain, and the 2 nd terminal of the transistor is a drain or source.

In the above embodiment, an example in which the output circuit 32 is controlled by various signals is described. The signal of the control output circuit 32 is not limited to the example shown in the embodiment. For example, the signal S5 of embodiment 3 may be replaced with the signal STBY. For example, the signal S6 of embodiment 4 may be replaced with a signal/STBY.

In embodiment 3 and embodiment 4, an example in which a voltage used in a standby state is generated by a circuit using a current source is described. The configuration of the circuit using the current source is not limited to the examples shown in embodiment 3 and embodiment 4.

Fig. 29 shows an example of the configuration of an output circuit 32 according to a modification of embodiment 3. As shown in fig. 29, the pre-driver 72a included in the modification of embodiment 3 has a structure in which the transistor TR9, the resistor R1, and the current source CS1 are replaced with the transistor TR9a, the resistor R1a, and the current source CS1a with respect to the pre-driver 72 included in embodiment 3. The transistor TR9a is, for example, a P-type MOSFET.

The voltage VDD1 is applied to the source and back gate of the transistor TR9 a. The signal S1 is applied to the gate of the transistor TR9 a. The drain of the transistor TR9a is connected to one end of the resistor R1 a. The other end of the resistor R1a is connected to the node N1. The voltage VSS is applied to the current source CS1a, and a current is supplied from the node N1 to the voltage VSS based on the signal STBY. Other configurations of the semiconductor memory device 1 according to the modification of embodiment 3 are the same as those of embodiment 3. The semiconductor memory device 1 according to the modification of embodiment 3 can operate in the same manner as the semiconductor memory device 1 according to embodiment 3. Embodiment 3 and the variation of embodiment 3 can also be described as a circuit including a transistor, a resistor, and a current source arranged in series between the voltage VDD1 and the voltage VSS. Thus, the arrangement of transistors, resistors and current sources arranged in series between the voltages VDD1 and VSS can be suitably exchanged.

Fig. 30 shows an example of the configuration of an output circuit 32 according to a modification of embodiment 4. As shown in fig. 30, the pre-driver 73a included in the modification of embodiment 4 has a structure in which the transistor TR17, the resistor R2, and the current source CS2 are replaced with the transistor TR17a, the resistor R2a, and the current source CS2a with respect to the pre-driver 73 included in embodiment 4. The transistor TR17a is, for example, an N-type MOSFET.

The voltage VSS1 is applied to the source and back gates of the transistor TR17 a. A signal S3 is applied to the gate of the transistor TR17 a. The drain of the transistor TR17a is connected to one end of the resistor R2 a. The other end of resistor R2a is connected to node N3. The voltage VCCQ is applied to the current source CS2a, and a current is supplied from the voltage VCCQ to the node N3 based on the signal STBY. Other configurations of the semiconductor memory device 1 according to the modification of embodiment 4 are the same as those of embodiment 4. The semiconductor memory device 1 according to the modification of embodiment 4 can operate in the same manner as the semiconductor memory device 1 according to embodiment 4. The 4 th embodiment and the variation of the 4 th embodiment may be described as a circuit including a transistor, a resistor, and a current source arranged in series between the voltage VCCQ and the voltage VSS1. In this way, the arrangement of transistors, resistors and current sources arranged in series between the voltage VCCQ and the voltage VSS1 can be properly exchanged.

In embodiment 2, embodiment 4 and embodiment 6, the case where the voltage VSS1 is lower than the voltage VSS is described as an example. The configuration of the N-type MOSFET including the voltage VSS1 lower than the voltage VSS will be described by taking the transistors TR13 to TR16 included in the predriver 71 of embodiment 2 as an example.

Fig. 31 shows an example of a cross-sectional structure of the pre-driver 71 according to embodiment 2. Fig. 31 is a view showing a cross-sectional structure of a semiconductor substrate in which the predriver 71 of embodiment 2 is provided, with the regions including the transistors TR13 to TR16 being selected. The region shown in fig. 31 includes a semiconductor substrate 400, N-type well regions 201 and 202, P-type well regions 301, N-type diffusion regions 101 to 106, P-type diffusion regions 111 to 116, insulators 121 to 124, and conductors 131 to 134.

In fig. 31, a plane defined by the X direction and the Y direction corresponds to the surface of the semiconductor substrate 400 on which the semiconductor memory device 1 is formed, and the Z direction corresponds to a direction perpendicular to the surface of the semiconductor substrate 400 on which the semiconductor memory device 1 is formed. In addition, electrical connection by means of contacts or wiring is represented by lines in a simplified manner.

The semiconductor substrate 400 comprises P-type silicon. The N-type well region 201 is formed inside the semiconductor substrate 400, and the upper end thereof is connected to the upper surface of the semiconductor substrate 400. An N-type diffusion region 101 and P-type diffusion regions 111 to 114 are sequentially disposed in the X direction inside the N-type well region 201. The upper ends of the N-type diffusion regions 101 and the P-type diffusion regions 111 to 114 are connected to the upper surface of the semiconductor substrate 400. The N-type diffusion region 101 is electrically connected to the N-type well region 201. The P-type diffusion region 111 functions as a source of the transistor TR 13. P-type diffusion region 112 functions as the drain of transistor TR 13. The P-type diffusion region 113 functions as a source of the transistor TR 14. The P-type diffusion region 114 functions as the drain of the transistor TR 14. Insulators 121 and 122 are disposed on N-type well region 201. The insulator 121 functions as a gate insulating film of the transistor TR 13. The insulator 122 functions as a gate insulating film of the transistor TR 14. The conductor 131 is disposed on the insulator 121. The conductor 131 functions as a gate electrode of the transistor TR 13. The conductor 132 is disposed on the insulator 122. The conductor 132 functions as a gate electrode of the transistor TR 14. The N-type diffusion region 101 and the P-type diffusion region 111 are electrically connected by wiring, and a voltage VCCQ is applied thereto. P-type diffusion regions 112 and 1133 are electrically connected to node N3 by wiring. The conductor 131 is connected to the node N4 through a wiring. The signal S4 is applied to the conductor 132 through the wiring.

N-type diffusion regions 102 and 103 and P-type diffusion region 115 are sequentially disposed in the X direction inside semiconductor substrate 400. The upper ends of the N-type diffusion regions 102 and 103 and the P-type diffusion region 115 are connected to the upper surface of the semiconductor substrate 400. The N-type diffusion region 102 functions as a drain of the transistor TR 15. The N-type diffusion region 103 functions as a source of the transistor TR 15. The P-type diffusion region 115 is electrically connected to the semiconductor substrate 400. An insulator 123 is provided on the semiconductor substrate 400. The insulator 123 functions as a gate insulating film of the transistor TR 15. An electrical conductor 133 is provided on the insulator 123. The conductor 133 functions as a gate electrode of the transistor TR 15. The N-type diffusion region 102 is electrically connected to the P-type diffusion region 114 by wiring. The N-type diffusion region 103 and the P-type diffusion region 115 are electrically connected by wiring, and a voltage VSS is applied thereto. The conductor 133 is connected to the node N4 through a wiring.

The N-type well region 202 is formed separately from the N-type well region 201 inside the semiconductor substrate 400. The upper end of the N-type well region 202 is connected to the upper surface of the semiconductor substrate 400. The Z-direction depth of the N-type well region 202 is deeper than the Z-direction depth of the N-type well region 201. The N-well region 202 is also referred to as a deep N-well. The P-type well region 301 is disposed inside the N-type well region 202. The upper end of the P-type well region 301 is connected to the upper surface of the semiconductor substrate 400. The depth of the P-type well region 301 in the Z direction is shallower than the depth of the N-type well region 202 in the Z direction. The P-type well region 301 is surrounded by the N-type well region 202 and separated from the semiconductor substrate 400. N-type diffusion regions 104 and 105 and a P-type diffusion region 116 are sequentially disposed in the X direction inside the P-type well region. The upper ends of the N-type diffusion regions 104 and 105 and the P-type diffusion region 116 are connected to the upper surface of the semiconductor substrate 400. The N-type diffusion region 104 functions as a drain of the transistor TR 16. The N-type diffusion region 105 functions as a source of the transistor TR 16. The P-type diffusion region 116 is electrically connected to the P-type well region 301. An insulator 124 is disposed over the P-type well region 301. The insulator 124 functions as a gate insulating film of the transistor TR 16. An electrical conductor 134 is disposed on the insulator 124. The conductor 134 functions as a gate electrode of the transistor TR 16. The N-type diffusion region 104 is connected to the node N3 by wiring. The N-type diffusion region 105 and the P-type diffusion region 116 are electrically connected by wiring, and a voltage VSS1 is applied thereto. The signal S3 is applied to the conductor 134 through the wiring. An N-type diffusion region 106 is provided inside the N-type well region 202. The upper end of the N-type diffusion region 106 is in contact with the upper surface of the semiconductor substrate 400. The N-type diffusion region 106 is electrically connected to the N-type well region 202. The voltage VCCQ is applied to the N-type diffusion region 106 through wiring.

The N-type MOSFET is provided in, for example, a P-type semiconductor substrate or a P-type well region, and the N-type diffusion region functions as a source or a drain. For example, when the voltage of the P-type well region is VSS and the voltage of the N-type diffusion region functioning as a source is VSS1 which is lower than VSS, a forward bias current may flow from the P-type well region to the N-type diffusion region. In contrast, in the example shown in fig. 31, the transistor TR16 whose source is applied with the voltage VSS1 is provided in the P-type well region 301, and the P-type well region 301 is provided in the N-type well region 202. The P-type well region 301 is surrounded by the N-type well region 202 and separated from the semiconductor substrate 400. Further, the voltage of the N-type well region 202 is the voltage VCCQ applied via the N-type diffusion region 106. With this configuration, the voltage of the P-type well region 301 can be determined to be different from the voltage of the semiconductor substrate 400. The voltage of the P-type well region 301 is the voltage VSS1 applied through the P-type diffusion region 116. This suppresses forward bias current from flowing from the P-type well region 301 to the N-type diffusion regions 104 and 105 functioning as the source and drain of the transistor TR16.

This configuration in which a P-type well region is provided in an N-type well region (deep N-well) provided deeper is also called a triple-well structure. In the example shown in fig. 31, an example in which the transistor TR16 is provided on the triple-well structure is shown, but the transistor provided on the triple-well structure is not limited to the transistor TR16. An N-type transistor to which a voltage lower than the voltage VSS may be applied to the source or drain may also be provided on the triple well structure. In addition, an N-type transistor in which a voltage lower than the voltage VSS is not applied to the source or the drain may be provided on the triple well structure.

Fig. 32 shows an example of a cross-sectional structure of the pre-driver 71 according to embodiment 2. The example shown in fig. 32 also includes P-type well region 302 and P-type diffusion region 117, relative to the example shown in fig. 31, and N-type well region 202 is replaced with N-type well region 202a including P-type well region 302. Specifically, the P-type well region 302 is provided separately from the P-type well region 301. Each of the N-type diffusion regions 102 and 103 and the P-type diffusion region 115 is disposed within a P-type well region 302. Insulator 123 and conductor 133 are disposed on P-type well region 302. The P-type diffusion region 115 is electrically connected to the P-type well region 302. N-well region 202a includes P-well regions 301 and 302. The P-type well region 301 is surrounded by the N-type well region 202a, and is separated from the P-type well region 302 and the semiconductor substrate 400. The P-type well region 302 is surrounded by the N-type well region 202a, and is separated from the P-type well region 301 and the semiconductor substrate 400. The P-type diffusion region 117 is disposed within the semiconductor substrate 400. The upper end of the P-type diffusion region 117 is connected to the upper surface of the semiconductor substrate 400. The P-type diffusion region 117 is electrically connected to the semiconductor substrate 400. The voltage VSS is applied to the P-type diffusion region 117 through the wiring.

The voltage of the P-type well region 302 is the voltage VSS applied through the P-type diffusion region 115. That is, in the example shown in fig. 32, 2P-type well regions to which different voltages are applied are provided in the N-type well region 202a. In this way, a plurality of P-type well regions to which different voltages are applied can be provided in the N-type well region provided deeper.

[8] Embodiment 7

The semiconductor memory device 1 of embodiment 7 is different from the semiconductor memory device 1 of embodiment 2 in the configuration of the logic unit 60 and the main driver 80. Hereinafter, the semiconductor memory device 1 according to embodiment 7 will be described with respect to the differences from embodiment 2.

[8-1] constitution

Fig. 33 shows an example of the configuration of the output circuit 32 according to embodiment 7. As shown in fig. 33, in the output circuit 32 of embodiment 7, the logic unit 60 includes an OR gate 61a and an OR gate 62. The OR gate 61a performs an OR operation on the signal SP and the signal STBY, and outputs the operation result to the node N2. The OR gate 62 performs an OR operation on the signal SN and the signal STBY, and outputs the operation result to the node N4. The signals SP and SN are, for example, signals input from the data bus to the output circuit 32.

In addition, the main driver 80 includes a transistor TR7a and a transistor TR8. The transistors TR7a and TR8 are, for example, N-type MOSFETs. The voltage VCCQ is applied to the drain of the transistor TR7 a. The source of transistor TR7a is connected to pad 50. The gate of the transistor TR7a is connected to the node N1. The back gate of the transistor TR7a is grounded. The drain of transistor TR8 is connected to pad 50. Each of the source and back gate of the transistor TR8 is grounded. The gate of the transistor TR8 is connected to the node N3.

Other configurations of the semiconductor memory device 1 of embodiment 7 are the same as those of embodiment 2.

[8-2] operation of output Circuit 32

Next, an operation of the output circuit 32 in the semiconductor memory device 1 according to embodiment 7 will be described. In embodiment 7, it is assumed that the voltages VSS1 and VSS2 are negative voltages lower than the voltage VSS, the absolute value of the voltage VSS2 is larger than the absolute value of the voltage VSS1, and the absolute value of the voltage VSS2 is equal to or larger than the absolute value of the threshold voltage of the transistor TR 14.

Fig. 17 shows the relationship between the logic level and the voltage of various signals in the semiconductor memory device 1 according to embodiment 7. The "H" level of the signal S3 corresponds to the voltage VDD. The "L" level of the signal S3 corresponds to the voltage VSS 1. The "H" level of the signal S4 corresponds to the voltage VDD. The "L" level of the signal S4 corresponds to the voltage VSS 2.

First, the operation of the pre-driver 71 according to embodiment 7 in the 1 st state will be described. In the 1 st state, the output circuit 32 is in a standby state, the logic level of the node N2 is at the "H" level, and the logic level of the node N4 is at the "H" level.

The transistor TR11 is turned off because the "H" level is applied to the gate. The transistor TR12 is turned on by the application of the "H" level to the gate. As a result, the voltage of the node N1 is determined as the voltage VSS by the transistor TR12 in the on state.

The transistor TR16 is turned on by the signal S3 of the voltage VDD applied to the gate. The transistor TR13 is turned off because the "H" level is applied to the gate. The transistor TR14 is turned off by the signal S4 of the voltage VDD applied to the gate. The transistor TR15 is substantially turned off because the transistors TR13 and TR14 are turned off and no current flows. As a result, the voltage of the node N3 is determined as the voltage VSS1 by the transistor TR16 in the on state.

As a result of the operation of the pre-driver 71, in the 1 st state, each of the transistors TR7a and TR8 of the main driver 80 is turned off, and the output node of the output circuit 32 is turned into a high impedance state. At this time, the voltage VSS1 is applied to the gate of the transistor TR 8.

Next, the operation of the predriver 71 according to embodiment 7 in the 2 nd state will be described in order of the case where the output circuit 32 outputs the "L" level and the case where the output circuit 32 outputs the "H" level.

In state 2, the output circuit 32 is active, the logic level of the node N2 is equal to the logic level of the signal SP, and the logic level of the node N4 is equal to the logic level of the signal SN. First, a case will be described in which the logic level of the node N2 is the "L" level, and the logic level of the node N4 is the "L" level.

The transistor TR11 is turned on by the application of the "L" level to the gate. The transistor TR12 is turned off because the gate is applied with the "L" level. As a result, the voltage of the node N1 is determined as the voltage VCCQ by TR11 in the on state.

The transistor TR16 is turned off by the signal S3 of the voltage VSS1 applied to the gate. The transistor TR13 is turned on by the application of the "L" level to the gate. The transistor TR15 is turned off because the gate is applied with the "L" level. A signal S4 of a voltage VSS2, which is a voltage equal to or higher than the threshold voltage of the transistor TR14 lower than the voltage VSS, is applied to the gate of the transistor TR 14. However, since the transistor TR15 is in an off state, the transistor TR14 does not apply a voltage to the node N3. As a result, the voltage of the node N3 is determined as the voltage VCCQ by the transistor TR13 in the on state.

As a result of the operation of the pre-driver 71, in the 2 nd state, the transistor TR7a of the main driver 80 is turned off, the transistor TR8 of the main driver 80 is turned on, and the output circuit 32 can output the "L" level of the voltage VSS.

Next, in the state 2, a case will be described in which the logic level of the node N2 is the "H" level, and the logic level of the node N4 is the "H" level.

The transistor TR11 is turned off because the "H" level is applied to the gate. The transistor TR12 is turned on by the application of the "H" level to the gate. As a result, the voltage of the node N1 is determined as the voltage VSS by the transistor TR12 in the on state.

The transistor TR16 is turned off by the signal S3 of the voltage VSS1 applied to the gate. The transistor TR13 is turned off by the signal of "H" level applied to the gate. A signal S4 of a voltage VSS2, which is a voltage equal to or higher than the threshold voltage of the transistor TR14 lower than the voltage VSS, is applied to the gate of the transistor TR 14. An "H" level is applied to the gate of the transistor TR 15. Accordingly, the transistors TR14 and TR15 are turned on. As a result, the voltage of the node N3 is determined as the voltage VSS by the transistors TR14 and TR15 in the on state.

As a result of the operation of the pre-driver 71, in the 2 nd state, the transistor TR7a of the main driver 80 is turned on, and the transistor TR8 of the main driver 80 is turned off. The transistor TR7a is an N-type MOSFET. Therefore, unlike the output circuit 32 of embodiment 2, the output circuit 32 of embodiment 7 outputs a voltage obtained by subtracting the threshold voltage of the transistor TR7a from the voltage VCCQ as an "H" level.

As described above, the output circuit 32 in the semiconductor memory device 1 according to embodiment 7 can control the voltage of the node N3 to the voltage VSS or the voltage VCCQ in the active state, and output the "L" level or the "H" level to the output node. Fig. 34 shows the output waveform of the output circuit 32 according to embodiment 7 and the output waveform of the output circuit 32 according to embodiment 2. As shown in fig. 34, the voltage of the "H" level at the output node (pad 50) of the output circuit 32 of the semiconductor memory device 1 of embodiment 7 is lower than that of embodiment 2. In addition, the amplitude of the "L" level and the "H" level at the output node (pad 50) of the output circuit 32 of the semiconductor memory device 1 of embodiment 7 is smaller than that of embodiment 2. That is, in the semiconductor memory device 1 of embodiment 7, the voltage VAVR, which is the average value of the amplitude of the output signal at the output node (pad 50) of the output circuit 32, is smaller than the average value ((vccq+vss)/2) of the voltage VCCQ and the voltage VSS.

[8-3] Effect of embodiment 7

As described above, in the semiconductor memory device 1 according to embodiment 7, the negative voltage VSS1 is applied to the node N3 in the standby state. In this way, in the semiconductor memory device 1 according to embodiment 7, the transistor TR8 in the standby state is in the reverse bias state, and the leakage current of the transistor TR8 can be suppressed. As a result, the semiconductor memory device 1 of embodiment 7 can suppress power consumption of the semiconductor memory device 1 in the standby state, as in embodiment 2.

In the semiconductor memory device 1 according to embodiment 7, the voltage output from the output node (pad 50) by the output circuit 32 corresponds to the voltage VSS in the case of the "L" level, and corresponds to the voltage VCCQ minus the threshold voltage of the transistor TR7a in the case of the "H" level. Therefore, the voltage corresponding to the "H" level can be reduced, and the amplitudes of the "L" level and the "H" level can be reduced. Therefore, the operation time required for shifting the level of the output signal between the "L" level and the "H" level can be shortened, and the power consumption can be reduced.

In the semiconductor memory device 1 according to embodiment 7, the level of the voltages VSS1 and VSS2 can be changed appropriately according to the characteristics of the transistors. The signal may also be used as a signal according to the relationship between the voltages. For example, the voltage VSS1 may be set to a voltage higher than the voltage VSS and lower than the threshold voltage of the transistor TR8 so that the transistor TR8 is biased in a weak forward direction. In this case, a regulator may also be used instead of the negative charge pump 23 to generate the voltage VSS1. In addition, in this case, the signal STBY or the signal S4 may be used instead of the signal S3.

[8-4] variation of embodiment 7

In embodiment 7, the case where the voltage VSS1 is applied to the node N3 via the transistor TR16 is described as an example, but the method of applying the voltage VSS1 is not limited thereto. For example, similar to embodiment 4, a voltage may be applied to the node N3 by a circuit including a current source.

Fig. 35 shows the structure of the output circuit 32 according to a modification of embodiment 7. The output circuit 32 of the modification of embodiment 7 is different from the output circuit 32 of embodiment 7 in that: the pre-driver 71 does not include the transistor TR16, but includes the transistor TR17a, the resistor R2a, and the current source CS2a. The transistor TR17a is, for example, an N-type MOSFET.

The voltage VSS1 is applied to the source and back gates of the transistor TR17 a. A signal S3 is applied to the gate of the transistor TR17 a. The drain of the transistor TR17a is connected to one end of the resistor R2 a. The other end of resistor R2a is connected to node N3. The voltage VCCQ is applied to the current source CS2a, and a current is supplied from the voltage VCCQ to the node N3 based on the signal STBY. Other configurations of the semiconductor memory device 1 according to the modification of embodiment 7 are the same as those of embodiment 7. The semiconductor memory device 1 according to the modification of embodiment 7 can operate in the same manner as the semiconductor memory device 1 according to embodiment 7.

Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in other various modes, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. These embodiments and variations thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and their equivalents.

Claims (16)

1. An output circuit is provided with:

a 1 st power line;

a 2 nd power line;

a 3 rd power line;

a bonding pad;

the 1 st transistor, the 1 st end is connected with the 1 st power line, the 2 nd end is connected with the welding pad;

the 2 nd transistor, the 1 st end is connected with the 2 nd power line, the 2 nd end is connected with the welding pad;

a 1 st circuit connected to each of the 3 rd power line and the gate of the 1 st transistor;

a 3 rd transistor, the 1 st end is connected to the 1 st power line;

a 4 th transistor, a 1 st end is connected to the gate of the 1 st transistor, and a 2 nd end is connected to a 2 nd end of the 3 rd transistor; and

A 5 th transistor, the 1 st end is connected to the 2 nd power line, the 2 nd end is connected to the grid of the 1 st transistor, and the grid is connected to the grid of the 3 rd transistor; and is also provided with

Applying a 1 st voltage to the 1 st power line,

applying a 2 nd voltage lower than the 1 st voltage to the 2 nd power line,

applying a 3 rd voltage different from both the 1 st voltage and the 2 nd voltage to the 3 rd power line,

in case 1, the 1 st circuit applies a 4 th voltage to the gate of the 1 st transistor, applies the 2 nd voltage to the gate of the 4 th transistor,

in case 2, the 1 st circuit electrically connects the 3 rd power line to the gate of the 1 st transistor, applies a 5 th voltage higher than the 1 st voltage to the gate of the 4 th transistor, and each of the 3 rd voltage and the 4 th voltage is higher than the 1 st voltage.

2. The output circuit of claim 1, wherein

The 1 st circuit comprises

A 6 th transistor having a 1 st terminal connected to the 3 rd power line and a 2 nd terminal connected to the gate of the 1 st transistor.

3. The output circuit of claim 2, wherein

Each of the 4 th voltage and the 5 th voltage is equal to the 3 rd voltage, and

in the 1 st case, the 3 rd voltage is applied to the gate of the 6 th transistor.

4. The output circuit of claim 1, wherein

The 1 st circuit comprises

A 7 th transistor, a 1 st resistor and a 1 st current source connected in series between the 3 rd power line and the 2 nd power line, and

in the 1 st case, the 7 th transistor is turned on, the 1 st current source supplies the 1 st current,

in the 2 nd case, the 7 th transistor is turned off, and the 1 st current source does not supply the 1 st current.

5. The output circuit of claim 1, wherein

The 4 th voltage is lower than the 1 st voltage and higher than the 2 nd voltage,

the 1 st transistor makes the 1 st power line and the bonding pad be electrically connected under the 1 st condition.

6. The output circuit of claim 5, wherein

The 1 st circuit comprises

A 6 th transistor having a 1 st terminal connected to the 3 rd power line and a 2 nd terminal connected to the gate of the 1 st transistor.

7. The output circuit of claim 5, wherein

The 1 st circuit comprises

A 7 th transistor, a 1 st resistor and a 1 st current source connected in series between the 3 rd power line and the 2 nd power line, and

in the 1 st case, the 7 th transistor is turned on, the 1 st current source supplies the 1 st current,

In the case of the 2 nd, the 7 th transistor is turned off, and the 1 st current source supplies no current.

8. The output circuit according to claim 1, further comprising:

a 2 nd resistor connected between the 2 nd terminal of the 1 st transistor and the bonding pad; and

And the 3 rd resistor is connected between the 2 nd end of the 2 nd transistor and the welding pad.

9. An output circuit is provided with:

a 1 st power line;

a 2 nd power line;

a 3 rd power line;

a bonding pad;

the 1 st transistor, the 1 st end is connected with the 1 st power line, the 2 nd end is connected with the welding pad;

the 2 nd transistor, the 1 st end is connected with the 2 nd power line, the 2 nd end is connected with the welding pad;

a 1 st circuit connected to each of the 3 rd power line and the gate of the 2 nd transistor;

a 3 rd transistor, wherein a 1 st end is connected to the 1 st power line, and a 2 nd end is connected to the gate of the 2 nd transistor;

a 4 th transistor, the 1 st end is connected to the grid electrode of the 2 nd transistor; and

A 5 th transistor, the 1 st end is connected to the 2 nd power line, the 2 nd end is connected to the 2 nd end of the 4 th transistor, and the grid is connected to the grid of the 3 rd transistor; and is also provided with

Applying a 1 st voltage to the 1 st power line,

Applying a 2 nd voltage lower than the 1 st voltage to the 2 nd power line,

applying a 3 rd voltage different from both the 1 st voltage and the 2 nd voltage to the 3 rd power line,

in case 1, the 1 st circuit applies a 4 th voltage to the gate of the 2 nd transistor, applies a 5 th voltage higher than the 1 st voltage to the gate of the 4 th transistor,

in case 2, the 1 st circuit makes the 3 rd power line electrically disconnected from the gate of the 2 nd transistor, applies a 6 th voltage lower than the 2 nd voltage to the gate of the 4 th transistor,

each of the 3 rd voltage and the 4 th voltage is lower than the 2 nd voltage.

10. The output circuit of claim 9, wherein

The 1 st circuit comprises

And a 6 th transistor having a 1 st end connected to the 3 rd power line and a 2 nd end connected to the gate of the 2 nd transistor.

11. The output circuit of claim 9, wherein

The 1 st circuit comprises

A 7 th transistor, a 1 st resistor and a 1 st current source connected in series between the 1 st power line and the 3 rd power line,

in the 1 st case, the 7 th transistor is turned on, the 1 st current source supplies the 1 st current,

In the 2 nd case, the 7 th transistor is turned off, and the 1 st current source does not supply the 1 st current.

12. The output circuit of claim 9, wherein

The 3 rd voltage is lower than the 1 st voltage and higher than the 2 nd voltage,

the 2 nd transistor makes the 2 nd power line and the bonding pad be electrically connected under the 1 st condition.

13. The output circuit of claim 12, wherein

The 1 st circuit comprises

And a 6 th transistor having a 1 st end connected to the 3 rd power line and a 2 nd end connected to the gate of the 2 nd transistor.

14. The output circuit of claim 12, wherein

The 1 st circuit comprises

A 7 th transistor, a 1 st resistor and a 1 st current source connected in series between the 1 st power line and the 3 rd power line,

in the 1 st case, the 7 th transistor is turned on, the 1 st current source supplies the 1 st current,

in the 2 nd case, the 7 th transistor is turned off, and the 1 st current source does not supply the 1 st current.

15. The output circuit according to claim 9, further comprising:

a 2 nd resistor connected between the 2 nd terminal of the 1 st transistor and the bonding pad; and

And the 3 rd resistor is connected between the 2 nd end of the 2 nd transistor and the welding pad.

16. The output circuit of claim 9, wherein the 1 st transistor is an N-type MOSFET, and

the 2 nd transistor is an N-type MOSFET.