CN112910298A - Minimum space vector modulation method for zero sequence voltage of cascaded multilevel converter - Google Patents

Minimum space vector modulation method for zero sequence voltage of cascaded multilevel converter Download PDF

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CN112910298A
CN112910298A CN202110098098.9A CN202110098098A CN112910298A CN 112910298 A CN112910298 A CN 112910298A CN 202110098098 A CN202110098098 A CN 202110098098A CN 112910298 A CN112910298 A CN 112910298A
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switching
vector
switch
switch state
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CN112910298B (en
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曾文军
王翠
王沄禾
李常学
段万政
曾瑄
涂振宇
欧阳俊铭
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Nanchang Institute of Technology
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices

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Abstract

The invention discloses a minimum space vector modulation method for zero sequence voltage of a cascade multilevel converter, which comprises the steps of converting a non-homogeneous linear equation set mapped between a basic vector and a switching state in an SVPWM (space vector pulse width modulation) algorithm into a homogeneous linear equation set by adding a specific constraint condition, solving a new homogeneous linear equation set, and obtaining a switching state corresponding to the basic vector under the specific constraint condition, wherein the obtained switching state is the minimum zero sequence voltage in all switching states corresponding to the basic vector. The simplified SVPWM method is suitable for any-level multilevel converters. Compared with the prior space vector modulation technology, the scheme of the invention can directly obtain the switching state with the minimum zero sequence voltage in all the switching states corresponding to the basic vector, can realize the algorithm only by comparison and simple four arithmetic operations, avoids complex trigonometric function and irrational number calculation, and is easy to realize by a computer.

Description

Minimum space vector modulation method for zero sequence voltage of cascaded multilevel converter
Technical Field
The invention belongs to the field of inverter modulation, and relates to a minimum space vector modulation method for zero sequence voltage of a cascaded multilevel converter.
Background
The cascaded multilevel converter topology is the earliest multilevel converter circuit, and after twenty years of development, particularly the demand of industrial production for medium-high voltage high-power converters is increased, people pay great attention to the converter topology structure. The cascade type converter realizes high-voltage large-capacity output by using a low-voltage power device, overcomes the problem that the voltage grade and the capacity of the converter are limited by the withstand voltage and the capacity of a single power switch device, and can increase the number of cascade units according to the application requirement to increase the level number of output voltage, thereby improving the voltage grade and the capacity of the converter. The cascade type converter has the characteristics of high modularization degree, easiness in expansion and control, good reliability, low harmonic content and the like, so that the cascade type structure has a wide application range.
The Space Vector Pulse Width Modulation (SVPWM) technology is a PWM control method combining a Sinusoidal Pulse Width Modulation (Sinusoidal Pulse Width Modulation-SPWM) technology and a circular track of an alternating current motor flux linkage. The realization method is that when the AC motor is powered by three-phase symmetrical sine wave voltage, the generated ideal circular flux linkage track is used as a reference, and the flux linkage generated by the combination control of different switch states of the fully-controlled switch device approaches the ideal circular flux linkage track, thereby obtaining the expected output voltage. Compared with the traditional SPWM technology, the switching times of the power switching device of the SVPWM technology can be reduced by 1/3, the direct-current voltage utilization rate can be improved by 15%, and real-time digital control is easy to realize, so that the SVPWM technology is widely applied.
According to the traditional SVPWM technology, firstly, three-phase reference voltage is converted into a reference vector on a two-dimensional rectangular coordinate plane through Clark conversion, then the reference vector is positioned, three basic vectors which are closest to the reference vector are determined, the three closest basic vectors are used for synthesizing the reference vector according to a volt-second balance principle, action time of the corresponding basic vector is calculated, then a switch state corresponding to the basic vector is calculated, a switch state switching sequence is determined, finally, the switch state is converted into a control signal of a specific switch device, work of each cascade unit is controlled, and space vector modulation of a three-phase converter is achieved. Calculating the corresponding switch state by the basic vector requires solving a non-homogeneous linear equation set, the number of solutions of the non-homogeneous linear equation set is infinite, and a finite number of solutions can be obtained by considering the limitation of the number of the actual cascade units, namely, one basic vector corresponding to a plurality of switch states (called redundant switch states) exists. The redundant switch state causes the problems of large calculation workload, complex switching path selection and the like, when the number of cascade units is increased, the calculation workload is increased exponentially, and the SVPWM realization difficulty is greatly increased.
Based on the above-mentioned problem of difficulty in implementation of the conventional SVPWM technology, it is necessary to research a new space vector modulation method for the cascaded multilevel converter.
Disclosure of Invention
The invention aims to provide a minimum space vector modulation method for zero sequence voltage of a cascaded multilevel converter aiming at the problems of a space vector modulation algorithm of the traditional cascaded multilevel converter, which converts a non-homogeneous linear equation set mapped between a basic vector and a switch state in an SVPWM algorithm into a homogeneous linear equation set by adding a specific constraint condition, solves a new homogeneous linear equation set, and can obtain the switch state corresponding to the basic vector under the specific constraint condition, wherein the obtained switch state is the minimum zero sequence voltage in all the switch states corresponding to the basic vector. The simplified SVPWM method is suitable for any-level multilevel converters.
In order to achieve the purpose, the technical scheme of the invention is as follows:
FIG. 1 shows a structure of a three-phase n-level H-bridge cascaded multilevel converter, each phase consisting of n voltage typesThe submodules of the single-phase full-bridge inverter are connected in series (the submodules of the single-phase full-bridge inverter are H-bridges), each H-bridge consists of four IGBTs and anti-parallel diodes, a capacitor connected with the H-bridge in parallel indicates that the submodules are in voltage type inversion, the input voltages of all the submodules are equal, and U is useddcThe output voltage of the H-bridge inverter submodule has three conditions: -Udc、0、UdcFor three levels: -1, 0, 1. For a three-phase n-level H-bridge cascade multilevel converter, the level number of three-phase output voltage is represented by a, b and c, and then a, b and c are belonged to [ +/-, +/- (n-1), +/- (n-2),. +/-, +/-2, +/-1, 0](ii) a Three phase voltage reference signals of the cascade multilevel converter are ura，urb，urc：
Figure BDA0002915081450000021
In the formula, m represents a modulation coefficient, m is more than 0 and less than or equal to 1, the utilization rate of the input direct-current voltage of the H bridge is reflected, n represents the number of the cascaded H bridge units of each phase, omega represents the angular frequency of a reference signal, and t represents time.
The minimum space vector modulation method for the zero sequence voltage of the cascade multilevel converter comprises the following steps, and the specific implementation steps are shown in the following figure 2:
the method comprises the following steps: for three phase voltage reference signals ura，urb，urcSampling, namely a given signal, a reference signal is called a reference signal in a multilevel converter modulation algorithm, and a reference vector on an alpha '-beta' coordinate system is calculated
Figure BDA0002915081450000031
Figure BDA0002915081450000032
In the formula, alpharAnd betarRepresenting reference vectors
Figure BDA0002915081450000033
Coordinate component of, to αrAnd betarGetting the whole:
Figure BDA0002915081450000034
determining a distance reference vector by taking int (x) as an integer function
Figure BDA0002915081450000035
The four most recent base vectors are
Figure BDA0002915081450000036
Base vector
Figure BDA0002915081450000037
Figure BDA0002915081450000038
Form a unit square as shown in FIG. 3;
step two: basic vector on alpha '-beta' coordinate system
Figure BDA0002915081450000039
The mapping function with the switch state S (a, b, c) is:
Figure BDA00029150814500000310
alpha and beta represent basis vectors
Figure BDA00029150814500000311
The corresponding coordinate components are determined by the three-phase level numbers a, b, c ∈ [ +/- (n-1), +/- (n-2),. +/-, +/-2, +/-1, +/-0]Therefore, the basic vector on the alpha '-beta' plane is distributed in a unit integer coordinate point; s (a, b, c) is called the basis vector
Figure BDA00029150814500000312
Corresponding switch state, S represents the name of the switch state;
step three: according to the requirement of minimum zero sequence voltage N, constructing a constraint function:
N＝a+b+c＝0 (5)
step four: simultaneous equations (4) and (5) yield:
Figure BDA00029150814500000313
step five: judgment (α)r+βr)-(α0+β0) Whether the distance is greater than or equal to 1, and determining a distance reference vector
Figure BDA00029150814500000314
Three nearest basic vectors, and synthesizing reference vector by using the three nearest basic vectors
Figure BDA00029150814500000315
Calculating the action time of three basic vectors according to a volt-second balance principle, substituting the basic vectors into a formula (6), and calculating the switch states corresponding to the basic vectors;
step six: and determining the switching sequence of the three basic vectors corresponding to the switch states, and realizing space vector modulation by adopting a five-segment algorithm.
In step four, a, b, c obtained by calculating formula (6) may not be integers, and it is necessary to round a, b, c by a round function, round (x) represents rounding the logarithm value:
Figure BDA0002915081450000041
if the obtained a ', b ', c ' is in the range of [ + -n, +/- (n-1), +/- (n-2),. +/-, +/- (2), +/-1, 0]K is 0; if obtained, are
Figure BDA0002915081450000042
When min (a ', b', c ') < -n, k ═ min (a', b ', c') + n; when max (a ', b', c ') > n, k-max (a', b ', c') -n;
subtracting k from a ', b ', c ' simultaneously to obtain:
Figure BDA0002915081450000043
s (a ', b ', c ') is a base vector
Figure BDA0002915081450000044
The corresponding zero sequence voltage is the minimum switch state.
In step five, two situations can be obtained:
the first condition is as follows: when (alpha)r+βr)-(α0+β0) When the vector is more than or equal to 1, the basic vector is used
Figure BDA0002915081450000045
Synthetic reference vector
Figure BDA0002915081450000046
According to the volt-second equilibrium principle:
Figure BDA0002915081450000047
in the formula, t1，t2，t3Respectively representing basic vectors
Figure BDA0002915081450000048
Time of action of (T)sRepresents a sampling period;
calculating the basic vector according to the formulas (6), (7) and (8)
Figure BDA0002915081450000049
Corresponding switch state S1(a1″，b1″，c1″)、S2(a2″，b2″，c2") and S3(a3″，b3″，c3") that is
Figure BDA00029150814500000410
Figure BDA00029150814500000411
And S1Is a base vector
Figure BDA00029150814500000412
Minimum zero sequence voltage switching state, S2Is a base vector
Figure BDA00029150814500000413
Minimum zero sequence voltage switching state, S3Is a base vector
Figure BDA00029150814500000414
The switching state with the minimum zero sequence voltage;
case two: when (alpha)r+βr)-(α0+β0) When < 1, use the base vector
Figure BDA00029150814500000415
Synthetic reference vector
Figure BDA00029150814500000416
According to the volt-second equilibrium principle:
Figure BDA00029150814500000417
in the formula, t0，t1，t2Respectively representing basic vectors
Figure BDA00029150814500000418
The action time of (c);
calculating the basic vector according to the formulas (6), (7) and (8)
Figure BDA00029150814500000419
Corresponding switch state S0(a0″，b0″，c0″)、S1(a1″，b1″，c1") andS2(a2″，b2″，c2"), i.e.:
Figure BDA00029150814500000420
Figure BDA00029150814500000421
and S0Is a base vector
Figure BDA00029150814500000422
Minimum zero sequence voltage switching state, S1Is a base vector
Figure BDA00029150814500000423
Minimum zero sequence voltage switching state, S2Is a base vector
Figure BDA00029150814500000424
The switching state with the minimum zero sequence voltage.
In the sixth step, the number g of redundant switch states corresponding to the basic vector is calculated:
g＝2n-max{a，b，c}+min{a，b，c} (11)
three basis vectors can be calculated according to equation (11)
Figure BDA0002915081450000051
Or
Figure BDA0002915081450000052
The number of corresponding redundant switch states is g0，g1，g2Or g1，g2，g3：
g0＝2n-max{a0″，b0″，c0″}+min{a0″，b0″，c0″}；
g1＝2n-max{a1″，b1″，c1″}+min{a1″，b1″，c1″}；
g2＝2n-max{a2″，b2″，c2″}+min{a2″，b2″，c2″}；
g3＝2n-max{a3″，b3″，c3″}+min{a3″，b3″，c3″}；
Judging the switching sequence of the switch states according to the principle that the switching of the switch states is optimal (namely, the basic vectors with more redundant switch states have priority and the switch states switched back and forth are changed by +/-1 unit level), wherein the following two conditions exist;
case 1: when (alpha)r+βr)-(α0+β0) When > 1, the function mod ((g)1+g2+g3) And 3) two cases are obtained:
when mod ((g)1+g2+g3) And, when 3) is 1, the reaction solution,
Figure BDA0002915081450000053
the number of redundant switch states corresponding to one basic vector in the three basic vectors is one more than that of the other two basic vectors, and g is1，g2，g3The switch state corresponding to the largest one is taken as the first switching switch state, the switch state with the difference value of +/-1 with the switch state is taken as the second switching switch state, and the rest one is taken as the third switching switch state;
when mod ((g)1+g2+g3) And 3) when 2, the number of the redundant switch states corresponding to one basic vector in the three basic vectors is one less than that of the other two basic vectors, and g is equal to1，g2，g3The minimum corresponding switch state is taken as the third switching switch state, the switch state with the difference value of +/-1 with the switch state is taken as the second switching switch state, and the rest switch state is taken as the first switching switch state;
according to the result obtained by calculation, six switching sequences exist, the switching sequences are realized by adopting a five-segment algorithm, and the switching sequence of the switch states of the synthetic reference vector is as follows:
calculating the switching sequence to be S1，S2，S3The switching sequence of the switch states of the synthetic reference vector is S1→S2→S3→S2→S1Corresponding action times are respectively t1/2→t2/2→t3→t2/2→t1/2；
② the obtained switching sequence is calculated as S1，S3，S2The switching sequence of the switch states of the synthetic reference vector is S1→S3→S2→S3→S1Corresponding action times are respectively t1/2→t3/2→t2→t3/2→t1/2；
③ calculating the obtained switching sequence to be S2，S1，S3The switching sequence of the switch states of the synthetic reference vector is S2→S1→S3→S1→S2Corresponding action times are respectively t2/2→t1/2→t3→t1/2→t2/2；
Fourthly, the obtained switching sequence is calculated to be S2，S3，S1The switching sequence of the switch states of the synthetic reference vector is S2→S3→S1→S3→S2Corresponding action times are respectively t2/2→t3/2→t1→t3/2→t2/2；
Calculating the obtained switching sequence to be S3，S1，S2The switching sequence of the switch states of the synthetic reference vector is S3→S1→S2→S1→S3Corresponding action times are respectively t3/2→t1/2→t2→t1/2→t3/2；
Sixthly, the obtained switching sequence is calculated to be S3，S2，S1The switching sequence of the switch states of the synthetic reference vector is S3→S2→S1→S2→S3Corresponding time of actionAre each t3/2→t2/2→t1→t2/2→t3/2；
Case 2: when (alpha)r+βr)-(α0+β0) When < 1, the function mod ((g)0+g1+g2) And 3) two cases are obtained:
when mod ((g)0+g1+g2) And 3) when 1 is formed, the number of redundant switch states corresponding to one basic vector in the three basic vectors is one more than that of the other two basic vectors, and g is added0，g1，g2The switch state corresponding to the largest one is taken as the first switching switch state, the switch state with the difference value of +/-1 with the switch state is taken as the second switching switch state, and the rest one is taken as the third switching switch state;
when mod ((g)0+g1+g2) And 3) when 2, the number of the redundant switch states corresponding to one basic vector in the three basic vectors is one less than that of the other two basic vectors, and g is equal to0，g1，g2The minimum corresponding switch state is taken as the third switching switch state, the switch state with the difference value of +/-1 with the switch state is taken as the second switching switch state, and the rest switch state is taken as the first switching switch state;
according to the result obtained by calculation, six switching sequences exist, the switching sequences are realized by adopting a five-segment algorithm, and the switching sequence of the switch states of the synthetic reference vector is as follows:
calculating the switching sequence to be S0，S1，S2The switching sequence of the switch states of the synthetic reference vector is S0→S1→S2→S1→S0Corresponding action times are respectively t0/2→t1/2→t2→t1/2→t0/2；
② the obtained switching sequence is calculated as S0，S2，S1The switching sequence of the switch states of the synthetic reference vector is S0→S2→S1→S2→S0Corresponding action times are respectively t0/2→t2/2→t1→t2/2→t0/2；
③ calculating the obtained switching sequence to be S1，S0，S2The switching sequence of the switch states of the synthetic reference vector is S1→S0→S2→S0→S1Corresponding action times are respectively t1/2→t0/2→t2→t0/2→t1/2；
Fourthly, the obtained switching sequence is calculated to be S1，S2，S0The switching sequence of the switch states of the synthetic reference vector is S1→S2→S0→S2→S1Corresponding action times are respectively t1/2→t2/2→t0→t2/2→t1/2；
Calculating the obtained switching sequence to be S2，S0，S1The switching sequence of the switch states of the synthetic reference vector is S2→S0→S1→S0→S2Corresponding action times are respectively t2/2→t0/2→t1→t0/2→t2/2；
Sixthly, the obtained switching sequence is calculated to be S2，S1，S0The switching sequence of the switch states of the synthetic reference vector is S2→S1→S0→S1→S2Corresponding action times are respectively t2/2→t1/2→t0→t1/2→t2/2。
Compared with the prior space vector modulation technology, the scheme of the invention can directly obtain the switching state with the minimum zero sequence voltage in all the switching states corresponding to the basic vector, can realize the algorithm only by comparison and simple four arithmetic operations, avoids complex trigonometric function and irrational number calculation, and is easy to realize by a computer.
Drawings
Fig. 1 is a structural diagram of a three-phase n-level H-bridge cascade multilevel converter;
FIG. 2 is a block diagram of the implementation steps;
FIG. 3 is a schematic diagram of reference voltage vector positioning;
FIG. 4 is a diagram of switch state switching and time allocation for the embodiment;
FIG. 5 is a graph of simulated output phase voltage and line voltage waveforms; FIGS. 5(a) and 5(b) are waveform diagrams of phase and line voltages, respectively, where u ispRepresenting the phase voltage ulRepresenting the line voltage.
Detailed Description
In the following, a 4-stage 9-level converter is taken as an example (i.e., n is 4, the number of levels a, b, c e [ ± 4, ± 3, ± 2, ± 1, 0) of the three-phase output voltage]) Input DC voltage U of H bridge submoduledc100V, the modulation coefficient m of the phase voltage reference signal is 0.95, the angular frequency omega of the reference signal is 100 pi, and the sampling period TsThe invention is explained in further detail with reference to the figures and the specific embodiments, which are set forth in 0.2 ms:
a minimum space vector modulation method for zero sequence voltage of a cascaded multilevel converter comprises the following steps:
and when t is set to be 5.2ms, sampling, wherein the modulation method comprises the following steps:
the method comprises the following steps: for three phase voltage reference signals ura，urb，urcSampling to obtain: u. ofra＝-0.276、urb＝3.93、urc-3.655, calculated according to equation (2) to obtain αr＝3.379、βr4.206, i.e. reference vectors
Figure BDA0002915081450000071
For alpharAnd betarGet the whole to alpha0＝3、β0＝4。
Distance reference vector
Figure BDA0002915081450000072
The four most recent base vectors are
Figure BDA0002915081450000073
Figure BDA0002915081450000074
Base vector
Figure BDA0002915081450000075
Constituting a unit square.
Step two: (alphar+βr)-(α0+β0) 0.582 < 1 (3.376+4.206) - (3+4), using basic vector
Figure BDA0002915081450000076
Synthetic reference vector
Figure BDA0002915081450000077
Step three: calculating a base vector according to equation (10)
Figure BDA0002915081450000078
Time of action t0，t1，t2：
Figure BDA0002915081450000079
Calculating to obtain: t is t0＝0.0836ms，t1＝0.0752ms，t2＝0.0412ms。
Step four: calculating a base vector according to equation (6)
Figure BDA00029150814500000710
The switching state of (2):
Figure BDA00029150814500000711
step five: a is paired according to formula (7)0，b0，c0、a1，b1，c1、a2，b2，c2Respectively rounding to get the following parts:
Figure BDA0002915081450000081
due to a0′，b0′，c0′∈[±4，±3，±2，±1，0]、a1′，b1′，c1′∈[±4，±3，±2，±1，0]、a2′，b2′，c2′∈[±4，±3，±2，±1，0]K is 0, calculated according to equation (8):
Figure BDA0002915081450000082
S0(0，4，-3)、S1(0，4，-4)、S2(-1, 4, -4) is the basic vector of the alpha '-beta' coordinate system
Figure BDA0002915081450000083
Figure BDA0002915081450000084
The corresponding switch state with the minimum zero sequence voltage;
step six: calculating a base vector according to equation (11)
Figure BDA0002915081450000085
Number g of redundant switch states0，g1，g2：
g0＝2n-max{a0″，b0″，c0″}+min{a0″，b0″，c0″}＝2*4-4+(-3)＝1
g1＝2n-max{a1″，b1″，c1″}+min{a1″，b1″，c1″}＝2*4-4+(-4)＝0
g2＝2n-max{a2″，b2″，c2″}+min{a2″，b2″，c2″}＝2*4-4+(-4)＝0
Step seven: according to the principle that the switching state is optimal (namely, the basic vectors with more redundant switching states have priority and the switching states switched before and after are only changed by 1 unit level), judging the switching state switching sequence:
since the reference vector selected by the present embodiment satisfies (α)r+βr)-(α0+β0)＝(3.376+4.206)-(3+4)＝0.582＜1，mod((g0+g1+g2) 3) is 1, thus, g0，g1，g2The largest of which is g0Its corresponding switch state S0(0, 4, -3) as the first switched switching state, and switching state S0(0, 4, -3) comparison, on-off state S1(0, 4, -4) is only in the c-phase component with the switch state S0(0, 4, -3) differ by 1 level, so S1(0, 4, -4) as a second switched switching state, the remainder of S2(-1, 4, -4) is the third switched switch state, switch state S2(-1, 4, -4) is associated with the switching state S only in the c-phase component1(0, 4, -4) differ by 1 level, i.e. switching sequence S0，S1，S2The principle of optimal handover is followed.
The calculated switching sequence is S0，S1，S2The switching sequence of the switch states of the synthetic reference vector is S0(0，4，-3)→S1(0，4，-4)→S2(-1，4，-4)→S1(0，4，-4)→S0(0, 4-3) corresponding to action times t0/2→t1/2→t2→t1/2→t0The specific switch state switching and time distribution is shown in FIG. 4.
In order to track the change of the reference vector, the above operation is repeated.
Fig. 5 shows simulation waveforms of one phase voltage and one line voltage obtained in this embodiment.

Claims (4)

1. A minimum space vector modulation method for zero sequence voltage of a cascaded multilevel converter is characterized by comprising the following steps:
the method comprises the following steps: reference to three phase voltagesSignal ura,urb,urcSampling and calculating to obtain a reference vector on an a '-beta' coordinate system
Figure FDA0002915081440000011
Figure FDA0002915081440000012
In the formula, arAnd betarRepresenting reference vectors
Figure FDA0002915081440000013
Coordinate component of, to arAnd betarGetting the whole:
Figure FDA0002915081440000014
determining a distance reference vector by taking int (x) as an integer function
Figure FDA0002915081440000015
The four most recent base vectors are
Figure FDA0002915081440000016
Base vector
Figure FDA0002915081440000017
Figure FDA0002915081440000018
Forming a unit square;
step two: basic vector on alpha '-beta' coordinate system
Figure FDA0002915081440000019
The mapping function with the switch state S (a, b, c) is:
Figure FDA00029150814400000110
a and beta represent the basis vectors, respectively
Figure FDA00029150814400000111
The corresponding coordinate components, S (a, b, c), are referred to as base vectors
Figure FDA00029150814400000112
Corresponding switch state, S represents switch state name, a, b, c represent the level corresponding to three phase voltage, for the n-level H bridge cascade multilevel converter, a, b, c ∈ [ +/-, +/- (n-1), +/- (n-2),. +/-, +/-2, +/-1, +/-0]；
Step three: according to the requirement of minimum zero sequence voltage N, constructing a constraint function:
N＝a+b+c＝0 (4)
step four: simultaneous equations (3) and (4) yield:
Figure FDA00029150814400000113
step five: judgment (a)r+βr)-(a0+β0) Whether the distance is greater than or equal to 1, and determining a distance reference vector
Figure FDA00029150814400000114
Three nearest basic vectors, and synthesizing reference vector by using the three nearest basic vectors
Figure FDA00029150814400000115
Calculating the action time of three basic vectors according to a volt-second balance principle, substituting the basic vectors into a formula (5), and calculating the switch states corresponding to the basic vectors;
step six: and determining the switching sequence of the three basic vectors corresponding to the switch states, and realizing space vector modulation by adopting a five-segment algorithm.
2. The modulation method according to claim 1, wherein in the fourth step, a, b, and c obtained by calculating formula (5) may not be integers, and a, b, and c need to be rounded by a round function, where round (x) represents rounding:
Figure FDA0002915081440000021
if the obtained a ', b ', c ' is in the range of [ + -n, +/- (n-1), +/- (n-2),. +/-, +/- (2), +/-1, 0]K is 0; if obtained, are
Figure FDA0002915081440000022
When min (a ', b ', c ')<-n, k ═ min (a ', b ', c ') + n; when max (a ', b ', c ')>n, k ═ max (a ', b ', c ') -n;
subtracting k from a ', b ', c ' simultaneously to obtain:
Figure FDA0002915081440000023
s (a ', b ', c ') is a basic vector
Figure FDA0002915081440000024
The corresponding zero sequence voltage is the minimum switch state.
3. The method for modulating the minimum space vector of the zero sequence voltage of the cascaded multilevel converter according to claim 1, wherein in the fifth step, two conditions can be obtained:
the first condition is as follows: when (a)r+βr)-(a0+β0) When the vector is more than or equal to 1, the basic vector is used
Figure FDA0002915081440000025
Synthetic reference vector
Figure FDA0002915081440000026
According to the volt-second equilibrium principle:
Figure FDA0002915081440000027
in the formula, t1,t2,t3Respectively representing basic vectors
Figure FDA0002915081440000028
Time of action of (T)sRepresents a sampling period;
calculating the basic vector according to the formulas (5), (6) and (7)
Figure FDA0002915081440000029
Corresponding switch state S1(a1”,b1”,c1”)、S2(a2”,b2”,c2") and S3(a3”,b3”,c3") that is
Figure FDA00029150814400000210
Figure FDA00029150814400000211
And S1Is a base vector
Figure FDA00029150814400000212
Minimum zero sequence voltage switching state, S2Is a base vector
Figure FDA00029150814400000213
Minimum zero sequence voltage switching state, S3Is a base vector
Figure FDA00029150814400000214
Switch shape with minimum zero sequence voltageState;
case two: when (alpha)r+βr)-(α0+β0)<1 hour, using the base vector
Figure FDA00029150814400000215
Synthetic reference vector
Figure FDA00029150814400000216
According to the volt-second equilibrium principle:
Figure FDA00029150814400000217
in the formula, t0,t1,t2Respectively representing basic vectors
Figure FDA00029150814400000218
The action time of (c);
calculating the basic vector according to the formulas (5), (6) and (7)
Figure FDA00029150814400000219
Corresponding switch state S0(a0”,b0”,c0”)、S1(a1”,b1”,c1") and S2(a2”,b2”,c2"), namely:
Figure FDA0002915081440000031
Figure FDA0002915081440000032
and S0Is a base vector
Figure FDA0002915081440000033
Minimum zero sequence voltage switching state, S1Is a base vector
Figure FDA0002915081440000034
Minimum zero sequence voltage switching state, S2Is a base vector
Figure FDA0002915081440000035
The switching state with the minimum zero sequence voltage.
4. The minimum space vector modulation method for zero sequence voltage of cascaded multilevel converter according to claim 1, wherein in the sixth step, the number g of redundant switch states corresponding to the basic vector is first calculated:
g＝2n-max{a，b，c}+min{a，b,c} (10)
three basis vectors can be calculated according to equation (10)
Figure FDA0002915081440000036
Or
Figure FDA0002915081440000037
The number of corresponding redundant switch states is g0，g1，g2Or g1，g2，g3：
g0＝2n-max{a0”,b0”，c0”}+min{a0”,b0”,c0”}；
g1＝2n-max{a1”,b1”,c1”}+min{a1”,b1”,c1”}；
g2＝2n-max{a2”,b2”,c2”}+min{a2”,b2”,c2”}；
g3＝2n-max{a3”,b3”,c3”}+min{a3”,b3”,c3”}；
Judging the switching sequence of the switch states according to the principle of optimal switching of the switch states, wherein the following two conditions exist;
case 1: when (alpha)r+βr)-(α0+β0) When > 1, the function mod ((g)1+g2+g3) And 3) two cases are obtained:
when mod ((g)1+g2+g3) And, when 3) is 1, the reaction solution,
Figure FDA0002915081440000038
the number of redundant switch states corresponding to one basic vector in the three basic vectors is one more than that of the other two basic vectors, and g is1,g2,g3The switch state corresponding to the largest one is taken as the first switching switch state, the switch state with the difference value of +/-1 with the switch state is taken as the second switching switch state, and the rest one is taken as the third switching switch state;
when mod ((g)1+g2+g3) And 3) when 2, the number of the redundant switch states corresponding to one basic vector in the three basic vectors is one less than that of the other two basic vectors, and g is equal to1,g2,g3The minimum corresponding switch state is taken as the third switching switch state, the switch state with the difference value of +/-1 with the switch state is taken as the second switching switch state, and the rest switch state is taken as the first switching switch state;
according to the result obtained by calculation, six switching sequences exist, the switching sequences are realized by adopting a five-segment algorithm, and the switching sequence of the switch states of the synthetic reference vector is as follows:
calculating the switching sequence to be S1,S2,S3The switching sequence of the switch states of the synthetic reference vector is S1→S2→S3→S2→S1Corresponding action times are respectively t1/2→t2/2→t3→t2/2→t1/2；
② the obtained switching sequence is calculated as S1,S3,S2The switching sequence of the switch states of the synthetic reference vector is S1→S3→S2→S3→S1Corresponding action time respectivelyIs t1/2→t3/2→t2→t3/2→t1/2；
③ calculating the obtained switching sequence to be S2,S1,S3The switching sequence of the switch states of the synthetic reference vector is S2→S1→S3→S1→S2Corresponding action times are respectively t2/2→t1/2→t3→t1/2→t2/2；
Fourthly, the obtained switching sequence is calculated to be S2,S3,S1The switching sequence of the switch states of the synthetic reference vector is S2→S3→S1→S3→S2Corresponding action times are respectively t2/2→t3/2→t1→t3/2→t2/2；
Calculating the obtained switching sequence to be S3,S1,S2The switching sequence of the switch states of the synthetic reference vector is S3→S1→S2→S1→S3Corresponding action times are respectively t3/2→t1/2→t2→t1/2→t3/2；
Sixthly, the obtained switching sequence is calculated to be S3,S2,S1The switching sequence of the switch states of the synthetic reference vector is S3→S2→S1→S2→S3Corresponding action times are respectively t3/2→t2/2→t1→t2/2→t3/2；
Case 2: when (a)r+βr)-(a0+β0)<1, the function mod ((g)0+g1+g2) And 3) two cases are obtained:
when mod ((g)0+g1+g2) And 3) when 1 is formed, the number of redundant switch states corresponding to one basic vector in the three basic vectors is one more than that of the other two basic vectors, and g is added0,g1,g2The largest one of the corresponding switch states being the first one to switchThe switch state, the switch state with the difference of +/-1 with the switch state is taken as the second switching switch state, and the rest is the third switching switch state;
when mod ((g)0+g1+g2) And 3) when 2, the number of the redundant switch states corresponding to one basic vector in the three basic vectors is one less than that of the other two basic vectors, and g is equal to0,g1,g2The minimum corresponding switch state is taken as the third switching switch state, the switch state with the difference value of +/-1 with the switch state is taken as the second switching switch state, and the rest switch state is taken as the first switching switch state;
according to the result obtained by calculation, six switching sequences exist, the switching sequences are realized by adopting a five-segment algorithm, and the switching sequence of the switch states of the synthetic reference vector is as follows:
calculating the switching sequence to be S0,S1,S2The switching sequence of the switch states of the synthetic reference vector is S0→S1→S2→S1→S0Corresponding action times are respectively t0/2→t1/2→t2→t1/2→t0/2；
② the obtained switching sequence is calculated as S0,S2,S1The switching sequence of the switch states of the synthetic reference vector is S0→S2→S1→S2→S0Corresponding action times are respectively t0/2→t2/2→t1→t2/2→t0/2；
③ calculating the obtained switching sequence to be S1,S0,S2The switching sequence of the switch states of the synthetic reference vector is S1→S0→S2→S0→S1Corresponding action times are respectively t1/2→t0/2→t2→t0/2→t1/2；
Fourthly, the obtained switching sequence is calculated to be S1,S2,S0The switching sequence of the switch states of the synthetic reference vector is S1→S2→S0→S2→S1Corresponding action times are respectively t1/2→t2/2→t0→t2/2→t1/2；
Calculating the obtained switching sequence to be S2,S0,S1The switching sequence of the switch states of the synthetic reference vector is S2→S0→S1→S0→S2Corresponding action times are respectively t2/2→t0/2→t1→t0/2→t2/2；
Sixthly, the obtained switching sequence is calculated to be S2,S1,S0The switching sequence of the switch states of the synthetic reference vector is S2→S1→S0→S1→S2Corresponding action times are respectively t2/2→t1/2→t0→t1/2→t2/2。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103944438A (en) * 2014-04-25 2014-07-23 广东工业大学 Rapid n-level multi-level inverter space vector pulse width modulation algorithm
CN104467496A (en) * 2014-06-23 2015-03-25 南昌工程学院 Three-dimensional space vector modulation algorithm of multi-level inverter
CN105490575A (en) * 2016-01-21 2016-04-13 广东工业大学 Alpha-beta coordinate system multilevel current converter zero sequence voltage optimization control method through stretching
CN110518822A (en) * 2019-08-26 2019-11-29 浙江大学 The Cascade H bridge inverter space vector width pulse modulation method of any more level
EP3657664A1 (en) * 2018-11-23 2020-05-27 Valeo Siemens eAutomotive France SAS Method for controlling a three-phase electrical machine

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103944438A (en) * 2014-04-25 2014-07-23 广东工业大学 Rapid n-level multi-level inverter space vector pulse width modulation algorithm
CN104467496A (en) * 2014-06-23 2015-03-25 南昌工程学院 Three-dimensional space vector modulation algorithm of multi-level inverter
CN105490575A (en) * 2016-01-21 2016-04-13 广东工业大学 Alpha-beta coordinate system multilevel current converter zero sequence voltage optimization control method through stretching
EP3657664A1 (en) * 2018-11-23 2020-05-27 Valeo Siemens eAutomotive France SAS Method for controlling a three-phase electrical machine
CN110518822A (en) * 2019-08-26 2019-11-29 浙江大学 The Cascade H bridge inverter space vector width pulse modulation method of any more level

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
CUI WANG,ETAL: "Space Vector Modulation in the 45 Coordinates for Multilevel Converters", 《IEEE TRANSACTIONS ON POWER ELECTRONICS》 *
刘铮: "多电平逆变器空间矢量调制技术研究", 《中国优秀博硕士学位论文全文数据库（博士） 电子期刊 工程科技Ⅱ辑》 *
王翠: "n级逆变器SVPWM调制零序电压优化算法", 《电工技术学报》 *

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