CN112909093A - Semiconductor device with a plurality of transistors - Google Patents

Semiconductor device with a plurality of transistors Download PDF

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Publication number
CN112909093A
CN112909093A CN202110079908.6A CN202110079908A CN112909093A CN 112909093 A CN112909093 A CN 112909093A CN 202110079908 A CN202110079908 A CN 202110079908A CN 112909093 A CN112909093 A CN 112909093A
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doped region
semiconductor device
field plate
plate structure
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CN112909093B (en
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葛薇薇
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Xiamen Jiebote Semiconductor Co.,Ltd.
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Joulwatt Technology Hangzhou Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/068—Nanowires or nanotubes comprising a junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors

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Abstract

The semiconductor device comprises a well region and a drift region which are transversely distributed on the surface of the semiconductor device, wherein a source end doping region and a drain end doping region are respectively arranged in the well region and the drift region to respectively form a source end and a drain end, a grid structure covers between the well region and the drift region, a field plate structure covers on the upper surface of the drift region and is used for forming an accumulation layer on the upper surface of the drift region, wherein a surface doping region with a doping type opposite to that of the drift region is arranged in a region, located between the field plate structure and the drain end doping region, on the upper surface of the drift region, and the surface doping region is electrically led out and electrically connected with the field plate structure. The semiconductor of the invention can ensure that the potential of the upper surface of the field plate structure is slightly higher than the potential of the lower surface of the field plate structure, and the electron accumulation layer is effectively formed below the field plate structure in the conduction state of the semiconductor device, thereby reducing the conduction resistance of the semiconductor device and improving the performance of the semiconductor device.

Description

Semiconductor device with a plurality of transistors
Technical Field
The present invention relates to the field of semiconductor technology, and in particular, to semiconductor devices.
Background
In order to improve the electrical characteristics of a laterally-diffused metal-oxide semiconductor (LDMOS), it is generally required to increase the Breakdown Voltage (BV) and reduce the specific on-resistance (on-resistance).
Common application technologies include field plate technology, resurf (resurf) technology, and super junction devices. The field plate technology is widely applied to a large number of devices, can effectively adjust the electric field of the drift region, improves the BV of the device, can assist in depleting the drift region in a voltage-resistant state, and can have higher doping concentration and lower on-resistance under the same voltage-resistant condition.
Disclosure of Invention
In view of the above problems, an object of the present invention is to provide a semiconductor device, whereby the on-resistance of the semiconductor device is further reduced and the withstand voltage capability of the semiconductor device is improved.
According to an aspect of the present invention, there is provided a semiconductor device including:
the drift region is arranged on the surface of the semiconductor device, and a source end doped region and a drain end doped region are respectively arranged at one end of the drift region far away from the drift region and one end of the well region far away from the well region;
the gate structure covers between the well region and the drift region;
a field plate structure overlying the drift region upper surface between the gate structure and the second doped region, wherein,
the upper surface of the drift region further comprises a surface doped region with the doping type opposite to that of the drift region, the surface doped region is located between the drain end doped region and the field plate structure, and the surface doped region is electrically led out and electrically connected with the field plate structure.
Optionally, the field plate structure comprises a plurality of segments spaced laterally apart.
Optionally, the well region is formed by self-alignment of the gate structure.
Optionally, the field plate structure and the gate structure are formed by simultaneously etching using the same mask as a mask.
Optionally, the semiconductor device further includes an epitaxial layer, the epitaxial layer is located on the substrate, and the well region and the drift region are located on the upper surface of the epitaxial layer and are distributed at intervals.
Optionally, the drift region is an N-type doped region;
the well region is a P-type doped region;
the first doped region comprises a P-type doped region and an N-type doped region which are transversely connected, and the P-type doped region of the first doped region is far away from the drift region than the N-type doped region;
the second doped region is an N-type doped region.
Optionally, the surface doped region is a P-type doped region, the upper surface of the surface doped region further includes a P-type doped electrical extraction region, and the electrical extraction region is electrically connected to the field plate structure.
Optionally, the drift region is a P-type doped region;
the well region is an N-type doped region;
the first doped region comprises an N-type doped region and a P-type doped region which are transversely connected, and the N-type doped region of the first doped region is far away from the drift region than the P-type doped region;
the second doped region is a P-type doped region.
Optionally, the surface doped region is an N-type doped region, the upper surface of the surface doped region further includes an N-type doped electrical extraction region, and the electrical extraction region is electrically connected to the field plate structure.
Optionally, at least one of a shallow trench isolation structure and a local silicon oxide isolation structure is further disposed in the drift region, and the at least one of the shallow trench isolation structure and the local silicon oxide isolation structure is disposed between two adjacent ones of the surface doped region, the field plate structure, and the drain doped region.
The semiconductor device provided by the invention comprises a well region and a drift region which are transversely distributed on the surface of the semiconductor device, a source end doping region and a drain end doping region are respectively arranged in the well region and the drift region to respectively form a source end and a drain end, a grid structure covers between the well region and the drift region, a field plate structure covers on the upper surface of the drift region to form an accumulation layer on the upper surface of the drift region, wherein a surface doping region with a doping type opposite to that of the drift region is arranged in a region between the field plate structure and the drain end doping region on the upper surface of the drift region, the surface doping region is electrically led out to be electrically connected with the field plate structure, the potential on the upper surface of the field plate structure is slightly higher than the potential on the lower surface of the field plate structure, and an electron accumulation layer is effectively formed below the field plate in a conducting state of the semiconductor device, so that the conducting resistance of, the performance of the semiconductor device is improved. And the breakdown risk of the dielectric layer of the field plate structure can be reduced under the condition that the thickness of the dielectric layer of the field plate structure is not increased, and the electric field adjusting capability of the field plate structure is ensured.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1 shows an overall structural schematic diagram of a semiconductor device according to an embodiment of the present invention;
fig. 2 through 6 are schematic diagrams illustrating a partial process flow of a semiconductor device according to an embodiment of the present invention.
Detailed Description
Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale.
The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples.
Fig. 1 shows an overall structural diagram of a semiconductor device according to an embodiment of the present invention.
As shown in fig. 1, a semiconductor device 100 according to an embodiment of the present invention includes an epitaxial layer 120 disposed on a substrate 110, an upper surface of the epitaxial layer 120 (corresponding to an upper surface of the semiconductor device 100) includes a well region 140 and a drift region 130 which are laterally spaced apart, an upper surface of an end of the well region 140 away from the drift region 130 includes a first conductive type doped region 141 and a second conductive type doped region 142 which are laterally connected and distributed to form a first doped region, the first doped region corresponds to a source end doped region to form a source S, an upper surface of an end of the drift region 130 away from the well region 140 includes a second doped region 131, the second doped region 131 is doped with a second conductive type, the second doped region 131 corresponds to a drain end doped region to form a drain D, a gate structure 151 covers the upper surface of the semiconductor device 100 and is connected to a contact of the second conductive type doped region 142 of the well region 140 and the drift region 130, a channel region is formed in a lower surface of the gate structure 151.
In the present embodiment, the well region 140 and the drift region 130 are spaced apart, and in an alternative embodiment, the well region 140 and the drift region 130 are disposed in contact.
The upper surface of the drift region 130 between the gate structure 151 and the second doped region 131 is further covered with a field plate structure 152, the upper surface of the drift region 130 further includes a surface doped region 101, the doping type of the surface doped region 101 is opposite to the doping type of the drift region 130, the surface doped region is located between the field plate structure 152 and the second doped region 131, the upper surface of the surface doped region 101 further includes an electrical extraction region 102, the electrical extraction region 102 and the field plate structure 152 are electrically connected to the adjusting terminal N1, the field plate is connected to an adjusting voltage input, so that the potential of the upper surface of the field plate structure 152 is slightly higher than the potential of the lower surface of the field plate structure 152, and in an on state of the semiconductor device 100, an electron accumulation layer can be effectively formed below the field plate structure 152, and the on resistance of the semiconductor device 100 is reduced.
In an alternative embodiment, the semiconductor device 100 is an N-type LDMOS, the drift region 130 is an N-type doped region, the well region 140 is a P-type doped region, the first conductive-type doped region 141 is a P-type doped region, the second conductive-type doped region 142 is an N-type doped region, the second doped region 131 is an N-type doped region, the surface doped region 101 is a P-type doped region, and the electrical lead-out region 102 is a P-type doped region.
In another alternative embodiment, the semiconductor device 100 is a P-type LDMOS, the drift region 130 is a P-type doped region, the well region 140 is an N-type doped region, the first conductive-type doped region 141 is an N-type doped region, the second conductive-type doped region 142 is a P-type doped region, the second doped region 131 is a P-type doped region, the surface doped region 101 is an N-type doped region, and the electrical lead-out region 102 is an N-type doped region.
Fig. 2 through 6 are schematic diagrams illustrating a partial process flow of a semiconductor device according to an embodiment of the present invention.
Referring to fig. 2 to 6, the semiconductor device 100 according to the embodiment of the present invention first grows an epitaxial layer 120 on a substrate 110 to form the structure shown in fig. 2. The substrate 110 is made of germanium, silicon germanium, silicon carbide, silicon on insulator, germanium on insulator, or the like. The epitaxial layer 120 is an N-type epitaxial layer corresponding to the N-type LDMOS, wherein N-type doped impurity ions are doped, which include one or more of phosphorus ions, arsenic ions, or antimony ions, which is not particularly limited in the present invention.
An implant of drift region 130 is then performed on the upper surface of epitaxial layer 120 to form the structure shown in fig. 3. By providing the epitaxial layer 120, the withstand voltage of the semiconductor device 100 can be improved, and the performance can be improved. The drift region 130 is formed by implanting N-type impurity ions through the well, corresponding to the N-type LDMOS.
After the drift region 130 is implanted, a surface doped region 101 is implanted at a corresponding position on the upper surface of the drift region 130, so as to form the structure shown in fig. 4. The doping type of the surface doping region 101 is opposite to the doping type of the drift region 130, and the surface doping region 101 is P-type doped corresponding to the N-type doped drift region 130 of the N-type LDMOS.
A gate oxide layer (a dielectric layer corresponding to the field plate structure 152) is then formed on the upper surface of the epitaxial layer 120 and the drift region 130 by thermal oxidation, polysilicon is deposited on the gate oxide layer, and then etching is performed to obtain a gate structure 151 and a field plate structure 152, so as to form the structure shown in fig. 5. And meanwhile, the gate structure 151 and the field plate structure 152 are manufactured, so that the consumption of an etched mask can be reduced, and the cost is reduced.
After the gate structure 151 is formed, a self-aligned implantation is performed to form the well region 140 by using the gate structure 151 as a mask, thereby forming the structure shown in fig. 6. The implanted impurity ions of the well region 140 are P-type impurity ions corresponding to the N-type LDMOS.
In the present embodiment, the well region 140 is formed by self-alignment using the gate structure 151 as a mask, the alignment is accurate, and the connection effect between the well region 140 and the channel region formed on the lower surface of the gate structure 151 is good. In an alternative embodiment, the well region 140 is formed by implantation before the gate structure 151 is fabricated, for example, after the drift region 130 is formed, implantation is performed by using a corresponding mask plate as a mask, then a gate oxide layer and a polysilicon layer are sequentially fabricated on the upper surfaces of the epitaxial layer 120, the well region 140 and the drift region 130, and then the gate structure 151 and the field plate structure 152 are formed by etching.
Then, the first conductive type doped region 141, the second conductive type doped region 142, the electrical lead-out region 102 and the second doped region 131 are formed by implantation at corresponding positions on the upper surfaces of the well region 140, the surface doped region 101 and the drift region 130, and electrodes are led out, so that the semiconductor device 100 of the embodiment of the invention shown in fig. 1 can be formed. Corresponding to the N-type LDMOS, the first conductive type doped region 141 is doped with P-type impurity ions, the second conductive type doped region 142 is doped with N-type impurity ions, the electrical lead-out region 102 is doped with P-type impurity ions, the second doped region 131 is doped with N-type impurity ions, the first conductive type doped region 141 and the second conductive type doped region 142 are led out and interconnected to form a source electrode S, the electrical lead-out region 102 is electrically connected with the field plate structure 152 and led out to be connected with a field plate voltage input, the second doped region 131 is electrically led out to form a drain electrode D, and the gate structure 151 is electrically led out to be a gate electrode G.
The field plate structure 152 may also be a segmented field plate, and is laterally spaced between the surface doped region 101 and the gate structure 151.
In the semiconductor device 100 according to the embodiment of the present invention, at least one of a shallow trench isolation structure and a local silicon oxide isolation structure may be disposed in the drift region 130, and disposed between the field plate structure 152 and the surface doped region 101 and between the surface doped region 101 and the second doped region 131, so that the isolation performance between the field plate structure 152 and the second doped region 131 can be ensured, and the breakdown voltage of the semiconductor device 100 can be further improved.
The semiconductor device of the invention forms the surface doping area between the drain terminal and the field plate structure in the drift area, the surface doping area is electrically led out to be electrically connected with the field plate structure, the electric potential on the upper surface of the field plate structure is slightly higher than the electric potential on the lower surface of the field plate structure, and under the conduction state of the semiconductor device, an electron accumulation layer can be effectively formed under the field plate structure, the conduction resistance of the semiconductor device is reduced, and the performance of the semiconductor device is improved. And the breakdown risk of the dielectric layer of the field plate structure is reduced under the condition that the thickness of the dielectric layer of the field plate structure is not increased, the voltage resistance of the field plate structure is improved, and the adjusting capability of the field plate structure on an electric field is ensured.
The well region is formed by self-aligned injection of the grid structure, the alignment accuracy of the well region and the channel region on the lower surface of the grid structure is improved, the channel performance is improved, the specific on-resistance is reduced, and the electrical performance of the semiconductor device is improved.
The well region and the drift region are arranged in the epitaxial layer, so that the withstand voltage can be improved.
The method is suitable for both N-type LDMOS and P-type LDMOS, and has high practicability.
The upper surface of the surface doping region is also provided with an electric lead-out region which is electrically connected with the field plate structure, so that the electric lead-out effect of the surface doping region is improved, the auxiliary effect on the field plate structure can be improved, the auxiliary depletion effect on the drift region is improved, the breakdown voltage of the semiconductor device is improved, and the electrical characteristics of the semiconductor device are improved.
While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.

Claims (10)

1. A semiconductor device, comprising:
the drift region is arranged on the surface of the semiconductor device, and a source end doped region and a drain end doped region are respectively arranged at one end of the drift region far away from the drift region and one end of the well region far away from the well region;
the gate structure covers between the well region and the drift region;
a field plate structure overlying the drift region upper surface between the gate structure and the second doped region, wherein,
the upper surface of the drift region further comprises a surface doped region with the doping type opposite to that of the drift region, the surface doped region is located between the drain end doped region and the field plate structure, and the surface doped region is electrically led out and electrically connected with the field plate structure.
2. The semiconductor device of claim 1,
the field plate structure includes a plurality of segments spaced apart laterally.
3. The semiconductor device of claim 1,
the well region is formed by self-aligning the gate structure.
4. The semiconductor device of claim 1,
the field plate structure and the grid structure are formed by simultaneously etching by using the same mask as a mask.
5. The semiconductor device of claim 1,
the epitaxial layer is positioned on the substrate, and the well region and the drift region are positioned on the upper surface of the epitaxial layer and are distributed at intervals.
6. The semiconductor device of claim 1,
the drift region is an N-type doped region;
the well region is a P-type doped region;
the first doped region comprises a P-type doped region and an N-type doped region which are transversely connected, and the P-type doped region of the first doped region is far away from the drift region than the N-type doped region;
the second doped region is an N-type doped region.
7. The semiconductor device of claim 6,
the surface doping region is a P-type doping region, the upper surface of the surface doping region further comprises a P-type doped electric leading-out region, and the electric leading-out region is electrically connected with the field plate structure.
8. The semiconductor device of claim 1,
the drift region is a P-type doped region;
the well region is an N-type doped region;
the first doped region comprises an N-type doped region and a P-type doped region which are transversely connected, and the N-type doped region of the first doped region is far away from the drift region than the P-type doped region;
the second doped region is a P-type doped region.
9. The semiconductor device of claim 8,
the surface doping region is an N-type doping region, the upper surface of the surface doping region further comprises an N-type doped electric leading-out region, and the electric leading-out region is electrically connected with the field plate structure.
10. The semiconductor device of claim 1,
the drift region is further provided with at least one of a shallow trench isolation structure and a local silicon oxide isolation structure, and the at least one of the shallow trench isolation structure and the local silicon oxide isolation structure is arranged between two adjacent surface doped regions, the field plate structure and the drain terminal doped region.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117153888A (en) * 2023-10-30 2023-12-01 粤芯半导体技术股份有限公司 Semiconductor device and method for manufacturing the same

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