CN112906074B - Data self-destruction circuit - Google Patents
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- CN112906074B CN112906074B CN202110126680.1A CN202110126680A CN112906074B CN 112906074 B CN112906074 B CN 112906074B CN 202110126680 A CN202110126680 A CN 202110126680A CN 112906074 B CN112906074 B CN 112906074B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
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Abstract
The application provides a data self-destruction circuit, wherein the circuit comprises: the power supply, the power supply chip, the first diode, the singlechip, the self-destruction circuit, a plurality of memories connected in parallel, and each memory is respectively connected with a corresponding fuse; the power supply supplies power for the power chip and the self-destruction circuit; the power chip is used for supplying power to the memory and the singlechip after reducing the voltage of the power supply; the first diode is used for preventing the current of the power supply from reversely flowing to the power supply chip through the self-destruction circuit; the self-destruction circuit is conducted after receiving the trigger level sent by the singlechip, so that the current of the power supply flows to the memory through the self-destruction circuit and the fuse; the fuse is used to open when the memory is shorted. The embodiment of the application adopts the same power supply to supply power to the memory and the self-destruction circuit, and when the voltage of the power supply flows to the memory through the self-destruction circuit, the data self-destruction is caused, so that the aim of simultaneously carrying out physical self-destruction on a plurality of memories under one power supply condition is fulfilled.
Description
Technical Field
The application relates to the technical field of circuits, in particular to a data self-destruction circuit.
Background
The data self-destruction is a method for destroying the data of the memory in a physical self-destruction mode, so that the stored data cannot be recovered, the data is prevented from being leaked in an illegal way, and the data protection is realized.
Most of the existing data self-destruction modes are to connect a memory with a self-destruction power supply independently, and to make the power supply end of the memory short-circuited for self-destruction by connecting high voltage to the power supply end of the memory. If the power supply ports of the memories are directly connected with the self-destruction power supply, the power supply port of one of the memories is short-circuited to the ground when the data is self-destroyed, and then the voltage is pulled down, so that the data cannot be self-destroyed by the low voltage in the other memories.
Therefore, the existing data self-destruction mode is difficult to realize that a plurality of memories are subjected to physical self-destruction simultaneously under the condition of power supply of a power supply.
Disclosure of Invention
In view of the above, the present application is directed to a data self-destruction circuit for implementing physical self-destruction of a plurality of memories under a power supply condition.
In a first aspect, an embodiment of the present application provides a data self-destruction circuit, including: the power supply, the power supply chip, the first diode, the singlechip, the self-destruction circuit, a plurality of memories connected in parallel, and each memory is respectively connected with a corresponding fuse; the power supply is respectively connected with the power supply chip and the self-destruction circuit; each memory is connected with the first diode and the self-destruction circuit through the fuse; the power chip is respectively connected with the first diode and the singlechip; the singlechip is respectively connected with the memory and the self-destruction circuit;
the power chip is used for reducing the voltage of the power supply and supplying power to the memory and the singlechip by using the reduced voltage;
the singlechip is used for sending a trigger level to the self-destruction circuit;
the first diode is used for preventing the current of the power supply from reversely flowing to the power supply chip after the self-destruction circuit receives the trigger level;
the self-destruction circuit is used for being conducted after receiving the trigger level, and the current of the power supply flows to the memory through the self-destruction circuit and the fuse;
the fuse is configured to open when the memory is shorted.
With reference to the first aspect, an embodiment of the present application provides a first possible implementation manner of the first aspect, where the self-destruction circuit includes: a MOS tube;
the MOS tube is used for being conducted after receiving the trigger level.
With reference to the first possible implementation manner of the first aspect, an embodiment of the present application provides a second possible implementation manner of the first aspect, where the self-destruction circuit further includes: a second diode;
the second diode is used for preventing the current of the power supply from reversely flowing to the MOS tube through the power supply chip and the first diode.
With reference to the first aspect, an embodiment of the present application provides a third possible implementation manner of the first aspect, where the single chip microcomputer is further configured to send a shutdown signal to the self-destruction circuit within a preset time after sending a trigger level to the self-destruction circuit;
the self-destruction circuit is used for being disconnected when receiving the closing signal.
With reference to the first aspect, an embodiment of the present application provides a fourth possible implementation manner of the first aspect, where the method further includes: a pressure sensor; the pressure sensor is connected with the singlechip;
the pressure sensor is used for converting the detected air pressure signal into a voltage signal and sending the voltage signal to the singlechip;
the singlechip is used for receiving the voltage signal and judging whether the voltage value of the voltage signal is larger than a preset voltage value or not;
and when the voltage value of the voltage signal is larger than the preset voltage value, sending a trigger level to the self-destruction circuit.
With reference to the first aspect, an embodiment of the present application provides a fifth possible implementation manner of the first aspect, wherein the memory includes any one or more of: secure digital cards, micro SD cards, solid state memories, hard drives, and flash drives.
With reference to the first aspect, an embodiment of the present application provides a sixth possible implementation manner of the first aspect, where the power supply includes any one or more of the following: primary batteries, alkaline batteries, lithium batteries, and secondary batteries.
With reference to the first aspect, an embodiment of the present application provides a seventh possible implementation manner of the first aspect, where a voltage value provided by the power supply is greater than 15V and less than 50V.
With reference to the first aspect, an embodiment of the present application provides an eighth possible implementation manner of the first aspect, wherein the single chip microcomputer is further configured to convert an external analog signal into a digital signal; and sending the digital signal to the memory for data storage.
With reference to the first aspect, an embodiment of the present application provides a ninth possible implementation manner of the first aspect, wherein the reduced voltage is greater than 3.3V and less than 3.9V.
The embodiment of the application provides a data self-destruction circuit, which comprises: the power supply, the power supply chip, the first diode, the singlechip, the self-destruction circuit, a plurality of memories connected in parallel, and each memory is respectively connected with a corresponding fuse; the power supply is respectively connected with the power chip and the self-destruction circuit; each memory is connected with the first diode and the self-destruction circuit through fuses respectively; the power chip is connected with the first diode and the singlechip respectively; the singlechip is respectively connected with the memory and the self-destruction circuit; the power chip is used for reducing the voltage of the power supply and supplying power to the memory and the singlechip by using the reduced voltage; the singlechip is used for sending a trigger level to the self-destruction circuit; the first diode is used for preventing the current of the power supply from reversely flowing to the power supply chip after the self-destruction circuit receives the trigger level; the self-destruction circuit is used for being conducted after receiving the trigger level, and the current of the power supply flows to the memory through the self-destruction circuit and the fuse; the fuse is used to open when the memory is shorted. The embodiment of the application adopts the same power supply to supply power to the singlechip, the memories and the self-destruction circuit, when the voltage of the power supply flows to the memories through the self-destruction circuit and the fuses at the same time, the data is self-destroyed and the fuses are disconnected, and meanwhile, the power supply chip is protected by the first diode in the reverse direction, so that the power supply chip and the singlechip work normally, thereby realizing the purpose that the memories are self-destroyed physically at the same time under one power supply condition, and simultaneously keeping the singlechip to work normally all the time.
In order to make the above objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a data self-destruction circuit according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of a second data self-destruction circuit according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of a third data self-destruction circuit according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of a fourth data self-destruction circuit according to an embodiment of the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. The components of the embodiments of the present application generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the application, as presented in the figures, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by a person skilled in the art without making any inventive effort, are intended to be within the scope of the present application.
In recent years, some storage devices have begun to employ a matrix controller to connect to a plurality of memories for capacity expansion, limited by the capacity of a single memory, thereby constructing a mass storage device. Some mass storage devices are required to destroy data in a physical self-destruction mode under special conditions due to data protection requirements, so that the stored data cannot be recovered, and the data is prevented from being leaked through illegal paths.
Most of the existing data self-destruction modes are to connect a memory with a self-destruction power supply independently, and to make the power supply end of the memory short-circuited for self-destruction by connecting high voltage to the power supply end of the memory. If the power supply ports of the memories are directly connected with the self-destruction power supply, the power supply port of one of the memories is short-circuited to the ground when the data is self-destroyed, and then the voltage is pulled down, so that the data cannot be self-destroyed by the low voltage in the other memories.
Therefore, the existing data self-destruction mode is difficult to realize that a plurality of memories are subjected to physical self-destruction simultaneously under the condition of power supply of a power supply.
Considering that the prior art cannot realize that a plurality of memories are self-destructed physically at the same time under one power supply condition, the embodiment of the application provides a data self-destruction circuit, and the data self-destruction circuit is described below through the embodiment.
For the sake of understanding the present embodiment, a data self-destruction circuit disclosed in the present embodiment is first described in detail. Fig. 1 is a schematic diagram of a data self-destruction circuit. Comprising the following steps: the power supply, the power supply chip, the first diode, the singlechip, the self-destruction circuit, a plurality of memories connected in parallel, and each memory is respectively connected with a corresponding fuse; the power supply is respectively connected with the power chip and the self-destruction circuit; each memory is connected with the first diode and the self-destruction circuit through fuses respectively; the power chip is connected with the first diode and the singlechip respectively; the singlechip is respectively connected with the memory and the self-destruction circuit;
the power chip is used for reducing the voltage of the power supply and supplying power to the memory and the singlechip by using the reduced voltage;
the singlechip is used for sending a trigger level to the self-destruction circuit;
the first diode is used for preventing the current of the power supply from reversely flowing to the power supply chip after the self-destruction circuit receives the trigger level;
the self-destruction circuit is used for being conducted after receiving the trigger level, and the current of the power supply flows to the memory through the self-destruction circuit and the fuse;
the fuse is used to open when the memory is shorted.
In the embodiment of the application, the data self-destruction circuit is suitable for a device containing a plurality of memories, when the self-destruction circuit receives a touch-up power level, all the memories in the device are subjected to physical self-destruction, namely, high voltage is provided for all the memories in the device, so that the power supply ports of the memories are short-circuited to the ground due to high voltage breakdown, and the memories after the physical self-destruction cannot be used continuously, so that the data in the memories cannot be recovered.
The memory is low-voltage equipment, and the power supply is used for providing high voltage. Specifically, under the normal working state of the storage device, the self-destruction circuit is in an off state, the power supply is used for providing high voltage for the power supply chip, the power supply chip is used for converting the received high voltage into low voltage required by the memory and the singlechip, and the reduced voltage is used for supplying power to the singlechip and each memory, so that the memory and the singlechip work normally.
When the data in all memories in the storage device are subjected to self-destruction, the singlechip sends a trigger level to the self-destruction circuit, and after the self-destruction circuit receives the trigger level sent by the singlechip, the self-destruction circuit is conducted to start working, so that high voltage provided by a power supply flows to power supply ports of all memories through the self-destruction circuit and fuses. The power chip can prevent high voltage from reversely flowing to the power chip through the self-destruction circuit due to the reverse protection of the first diode, so that the power chip and the singlechip can still work normally after the self-destruction circuit is started, and particularly, the first diode can be a high-power diode. The power supply port of the memory is short-circuited to ground due to high voltage breakdown, and thus a large current is passed through the circuit of the memory, resulting in the disconnection of the corresponding fuse of the memory. And meanwhile, high voltage is applied to the power supply ports of other memories, so that the power supply ports of the other memories are subjected to high-voltage breakdown and short circuit to the ground, and other fuses are disconnected due to high current until all fuses are disconnected.
The fuse can be a disposable low-power fuse, the disconnection time of the disposable low-power fuse is extremely short and is about 20 milliseconds, and because a large amount of capacitance with high capacitance value is used as voltage stabilizing discharge in a power chip circuit, the power supply voltage in the power chip and the singlechip cannot be pulled down in the process of disconnecting the fuse, and the normal operation of the power chip and the singlechip is ensured. If the fuse is not arranged, the power supply ports of the memories are all in direct short circuit, the power supply port of one of the memories is in short circuit to the ground when the data is self-destroyed, and then the voltage is lowered, so that the other memories are protected and cannot be self-destroyed.
In the embodiment of the application, the power supply voltage is not required to be independently provided for the self-destruction circuit; the power supply of the memories also adopts the same power supply voltage, and a power supply switch or a self-destruction protection circuit is not required to be arranged for each memory independently; the data self-destruction process time of the memories is extremely short, and the singlechip can always keep normal work in the working process of the self-destruction circuit; after the self-destruction circuit receives the trigger level, the self-destruction circuit directly performs data self-destruction without complex logic judgment, the self-destruction logic is simple to control, and the self-destruction speed of the data is extremely high.
In a possible embodiment, the singlechip is further configured to send a shutdown signal to the self-destruction circuit within a preset time after sending the trigger level to the self-destruction circuit; the self-destruction circuit is used for being disconnected when receiving the closing signal.
Specifically, after the self-destruction circuit starts to work, the power supply port of each memory is short-circuited to the ground, and after the fuse corresponding to the memory is disconnected, and under the condition that the singlechip can work normally, the singlechip sends a closing signal to the self-destruction circuit within a preset time after the trigger level is sent to the self-destruction circuit by the singlechip, and the self-destruction circuit is disconnected when receiving the closing signal, so that the process of data self-destruction is completed. In the application, all off-line operations can be completed only by controlling the self-destruction circuit through the singlechip.
In one possible embodiment, as shown in fig. 2, a schematic structure of a second data self-destruction circuit is shown, where the self-destruction circuit includes: and the MOS transistor (Metal-Oxide-Semiconductor Field-Effect Transistor) is used for being conducted after receiving the trigger level.
Specifically, when the storage device works normally, that is, when the self-destruction circuit is in an off state, it may be that the MOS transistor in the self-destruction circuit is in an off state; the MOS tube is used for receiving the trigger level sent by the singlechip and then conducting, so that high voltage provided by the power supply can flow to the memory through the self-destruction circuit, wherein the MOS tube is a high-power MOS tube because the voltage passing through the MOS tube is high.
In one possible embodiment, as shown in fig. 3, a schematic structure of a third data self-destruction circuit is shown, where the self-destruction circuit further includes: and the second diode is used for preventing the current provided by the power supply from reversely flowing to the MOS tube through the power supply chip and the first diode.
The second diode is used for preventing current provided by the power supply from reversely flowing to the MOS tube through the power supply chip and the first diode. And since the voltage passing through the self-destruction circuit is high voltage, the second diode is a high-power diode.
In one possible embodiment, as shown in fig. 4, a schematic structural diagram of a fourth data self-destruction circuit further includes: a pressure sensor; the pressure sensor is connected with the singlechip;
the pressure sensor is used for converting the detected air pressure signal into a voltage signal and sending the voltage signal to the singlechip;
the singlechip is used for receiving the voltage signal and judging whether the voltage value of the voltage signal is larger than a preset voltage value or not;
and when the voltage value of the voltage signal is larger than a preset voltage value, sending a trigger level to the self-destruction circuit.
In a specific working scenario, for example, a circuit completely wrapped by a casing, the inside of which is in a vacuum environment by a vacuum pumping mechanism, a pressure sensor is located inside a casing, and the pressure sensor detects an air pressure signal inside the casing and converts the detected air pressure signal into a voltage signal to be sent to a singlechip. If an external illegal person breaks the shell, the internal part is not in a vacuum environment, and the air pressure signal detected by the pressure sensor is transformed. The pressure sensor converts the air pressure signal detected in real time into a voltage signal and sends the voltage signal to the singlechip, wherein the voltage value corresponding to the voltage signal is larger as the air pressure value corresponding to the air pressure signal is larger, the singlechip judges whether the voltage value corresponding to the voltage signal is larger than a preset voltage value according to the received voltage signal, if the voltage value of the voltage signal is larger than the preset voltage value, the inside of the shell is not in a vacuum environment, namely the shell is forcibly broken by illegal personnel, the singlechip immediately sends a trigger level to the self-destruction circuit, and the data stored in the memory are subjected to physical self-destruction; if the voltage value of the voltage signal is not greater than the preset voltage value, the shell is still in a vacuum environment, namely the shell is not broken forcedly, and the stored data is not needed to be destroyed.
In one possible embodiment, the memory includes any one or more of the following: secure digital cards, micro SD cards, solid state memories, hard drives, and flash drives.
Specifically, the types of the memories may not be uniform, and in a specific embodiment, for example, when a certain storage device contains 10 memories in total, the types and the numbers of the memories may be respectively in a combination manner of 4 hard disks, 3 solid state memories, 3 secure digital cards and the like. The flash memory drive may be a USB flash memory drive (i.e., a USB disk).
In one possible embodiment, the voltage value provided by the power supply is greater than 15V and less than 50V.
Specifically, since the memory in the present application is a low voltage device, the power supply range of the memory is typically 3.3v±0.3V, and thus a voltage in the range of more than 15V and less than 50V belongs to a high voltage for the memory in the present application.
In one possible embodiment, the power supply includes any one or more of the following: primary batteries, alkaline batteries, lithium batteries, and secondary batteries.
Specifically, the power supply includes, but is not limited to, a primary battery, an alkaline battery, a lithium battery, a secondary battery, and the like. In a specific embodiment, for example, the power supply is a 24V dc power supply formed by connecting multiple strings of 16 disposable 1.5V primary batteries (alkaline batteries) in parallel.
In one possible embodiment, the reduced voltage is greater than 3.3V and less than 3.9V.
Since the diode itself has a voltage drop of 0.3V after the current passes through the diode, and the power supply range of the memory is typically 3.3v±0.3V, the power chip can reduce the voltage value provided by the power supply to 3.6v±0.3V, i.e. 3.3V to 3.9V.
In a possible embodiment, the single-chip microcomputer is further configured to convert an external analog signal into a digital signal; the digital signal is sent to a memory for data storage.
Specifically, the high voltage provided by the power supply is reduced by the power supply chip to provide stable low voltage for the singlechip, and the singlechip is used for controlling the conversion of external analog signals into digital signals and storing the digital signals into the memory.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
In the description of the present application, it should be noted that, directions or positional relationships indicated by terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., are directions or positional relationships based on those shown in the drawings, or those that are conventionally put in use of the product of the application, are merely for convenience of describing the present application and simplifying the description, and do not indicate or imply that the apparatus or elements referred to must have a specific direction, be configured and operated in a specific direction, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," "third," and the like are used merely to distinguish between descriptions and should not be construed as indicating or implying relative importance.
In the description of the present application, it should also be noted that, unless explicitly specified and limited otherwise, the terms "disposed," "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art.
Finally, it should be noted that: the above examples are only specific embodiments of the present application, and are not intended to limit the scope of the present application, but it should be understood by those skilled in the art that the present application is not limited thereto, and that the present application is described in detail with reference to the foregoing examples: any person skilled in the art may modify or easily conceive of the technical solution described in the foregoing embodiments, or perform equivalent substitution of some of the technical features, while remaining within the technical scope of the present disclosure; such modifications, changes or substitutions do not depart from the spirit and scope of the corresponding technical solutions. Are intended to be encompassed within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. A data self-destruction circuit, comprising: the power supply, the power supply chip, the first diode, the singlechip, the self-destruction circuit, a plurality of memories connected in parallel, and each memory is respectively connected with a corresponding fuse; the power supply is respectively connected with the power supply chip and the self-destruction circuit; each memory is connected with the first diode and the self-destruction circuit through the fuse; the power chip is respectively connected with the first diode and the singlechip; the singlechip is respectively connected with the memory and the self-destruction circuit;
the power chip is used for reducing the voltage of the power supply and supplying power to the memory and the singlechip by using the reduced voltage;
the singlechip is used for sending a trigger level to the self-destruction circuit;
the first diode is used for preventing the current of the power supply from reversely flowing to the power supply chip after the self-destruction circuit receives the trigger level;
the self-destruction circuit is used for being conducted after receiving the trigger level, and the current of the power supply flows to the memory through the self-destruction circuit and the fuse;
the fuse is configured to open when the memory is shorted.
2. The data self-destruction circuit of claim 1, wherein the self-destruction circuit comprises: a MOS tube;
the MOS tube is used for being conducted after receiving the trigger level.
3. The data self-destruction circuit of claim 2, further comprising: a second diode;
the second diode is used for preventing the current of the power supply from reversely flowing to the MOS tube through the power supply chip and the first diode.
4. The data self-destruction circuit of claim 1, wherein the single-chip microcomputer is further configured to send a shutdown signal to the self-destruction circuit within a preset time after sending a trigger level to the self-destruction circuit;
the self-destruction circuit is used for being disconnected when receiving the closing signal.
5. The data self-destruction circuit of claim 1, further comprising: a pressure sensor; the pressure sensor is connected with the singlechip;
the pressure sensor is used for converting the detected air pressure signal into a voltage signal and sending the voltage signal to the singlechip;
the singlechip is used for receiving the voltage signal and judging whether the voltage value of the voltage signal is larger than a preset voltage value or not;
and when the voltage value of the voltage signal is larger than the preset voltage value, sending a trigger level to the self-destruction circuit.
6. The data self-destruction circuit of claim 1, wherein the memory includes any one or more of: secure digital cards, micro SD cards, solid state memories, hard drives, and flash drives.
7. The data self-destruction circuit according to claim 1, wherein the power supply comprises any one or more of: primary batteries, alkaline batteries, lithium batteries, and secondary batteries.
8. The data self-destruction circuit according to claim 1, wherein the voltage value provided by the power supply is greater than 15V and less than 50V.
9. The data self-destruction circuit of claim 1, wherein,
the singlechip is also used for converting an external analog signal into a digital signal; and sending the digital signal to the memory for data storage.
10. The data self-destruction circuit of claim 1, wherein the reduced voltage is greater than 3.3V and less than 3.9V.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107818257A (en) * | 2017-11-23 | 2018-03-20 | 迈普通信技术股份有限公司 | One kind illegally tears machine data self-desttruction equipment and electronic equipment open |
Non-Patent Citations (1)
| Title |
|---|
| 自毁技术与装置研究;郝英好;赵楠;线珊珊;;中国高新技术企业(14);全文 * |
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