CN112905509A

CN112905509A - Gray scale number transmission controller, transmission control system and transmission method

Info

Publication number: CN112905509A
Application number: CN202110385361.2A
Authority: CN
Inventors: 不公告发明人
Original assignee: Chengdu Lipson Microelectronics Co ltd
Current assignee: Chengdu Lipson Microelectronics Co ltd
Priority date: 2020-04-15
Filing date: 2021-04-09
Publication date: 2021-06-04
Anticipated expiration: 2041-04-09
Also published as: CN214409973U; CN112905509B; CN112835830A

Abstract

The utility model relates to a grey scale number transmission controller, transmission control system and transmission method divide into public integer data and remainder coefficient data with grey scale data, then send public integer data and remainder coefficient data mixture to make just there is remainder coefficient data at the beginning in the PWM that shows, reduced the space of data storage, make chip cost reduce, still make remainder coefficient data distribute more evenly in every frame, thereby promote the display effect.

Description

Gray scale number transmission controller, transmission control system and transmission method

Technical Field

The present disclosure relates to the field of gray scale display, and more particularly, to a gray scale number transmission controller, a transmission control system, and a transmission method.

Background

The gray data is the data of the gray display intensity of the display, in the middle and high-order display screen, a constant current source driving chip which can output high refreshing PWM is usually adopted, all the chips usually receive and store the gray data, and then a PWM generating device is used for generating PWM driving signals. The full storage of the gray data requires a larger memory, and particularly, a chip adopting the Piig-Poig storage structure requires two memories, which increases the cost of the chip. On the premise, a method of separately transmitting gray scale data is proposed, for example, chinese patent publication No. Ci105096821B discloses a gray scale display driving method and a gray scale display driving apparatus, in which the gray scale display driving apparatus calculates gray scale data including a more significant bit and a remaining number of bits from display data in a video signal, then disperses weights of the more significant bit and the remaining number of bits into m sub-frames to obtain a plurality of sub-frame bit weight sequences and a plurality of sub-frame bit number value sequences, and outputs a gray scale driving signal on a sub-frame-by-sub-frame basis to drive LEDs of an LED display panel.

The patent provides that the gray data are divided into the gray data with high effective bits and the gray data with the rest bits, and then the gray data are respectively displayed, so that the problem that a larger memory is needed for transmitting the gray data once is solved, and meanwhile, the refresh rate of the gray data is also improved. The problems of non-uniform display and low refresh rate in the gray scale display process are solved in a certain achievement. However, this patent does not solve the display problem during the transmission of the gradation data. Generally, the gray data is transmitted by using a data bus, and currently, a driving chip generally uses one data bus, and when the gray data is divided into the gray data of the more significant bit and the gray data of the more significant bit for display, the gray data of the more significant bit and the gray data of the more significant bit are transmitted separately.

At present, in the data transmission process, a control card (or called as a controller) generally controls the data bus transmission process, and the traditional data transmission mode is to transmit all gray data for storage at one time, which occupies a large storage space and has a high chip cost. If the above patent is adopted to divide the gray data into the more significant bits and the less significant bits and perform the uniform display, the data transmission is performed in several times.

For a device for separately receiving common integer data and remainder coefficient data, when the controller controls data transmission, a certain bus time (bus bandwidth) is required for the driving chip to receive the common integer, and further, for the situation that the common integer is received first and then the remainder coefficient is received, the gray scale is incomplete before the remainder coefficient is received, the display effect is poor, and especially for low-gray data, the picture display effect is worse.

Disclosure of Invention

The application aims to overcome the defects of the prior art, and provides the gray data transmission controller and the gray data display transmission method, which can send and receive integer data and remainder coefficient data in a mixed manner, thereby not only reducing the chip cost, but also enabling the remainder coefficient data to be more uniformly distributed in each frame, and further improving the display effect.

The purpose of the application is realized by the following technical scheme:

a gray data transmission controller displays a frame front section, and the controller mixedly transmits common integer data and remainder coefficient data;

displaying the rear section of the frame, and only sending the remaining remainder coefficient data by the controller;

and the requirements are met,

where D' represents the gray value actually displayed for a certain frame, Q represents common integer data, and R_iThe number of times of displaying the residue coefficient data in the display frame is N, and N is the number of times of displaying the residue coefficient data in the display frame, and N is smaller than N in general.

In order to improve the uniformity of gray data display and reduce the capacity of a memory so as to reduce the cost of a chip, when gray data are transmitted by a controller, the gray data are divided into common integer data and remainder coefficient data, and only the common integer data and part of the remainder coefficient data are stored when the data are transmitted, so that the data storage capacity is greatly reduced, the requirement on the memory is reduced, the capacity and the size of the memory are reduced, and the cost is reduced. In the transmission process, the public integer data and the remainder coefficient data are mixed and sent, so that in the PWM display, the remainder coefficient data and the public integer data are in the beginning, and the public integers are not required to be additionally displayed, so that the problem that a plurality of groups of public integers are required to be additionally displayed or remainder coefficient data are required to be waited for in the traditional transmission process of the public integer data and the remainder coefficient data is solved, and the PWM display is more uniform.

The gray data is divided into common integer data and remainder data by the controller for transmission, and the following conditions are met:

common integer data

Solving an integral function;

remainder data

A remainder function, wherein D represents the gray value and the remainder number of a certain frameDividing the data into a plurality of residue coefficient data R_i。

Wherein N is the weight of the integer part, and the residue coefficient data is 1bit or more bits in the residue data.

Furthermore, public integer data and remainder coefficient data sent in a mixed mode in the front section of the display frame are stored in the driving chip, and remainder coefficient data sent in the rear section of the display frame are not stored.

Furthermore, the front display frame segment and the rear display frame segment are completely sent by common integers to serve as distinguishing nodes. The term that all the transmission is finished means that all the public integer data corresponding to all the channels of the driving chip are completely transmitted, taking 16 channels as an example, if the public integer is 7 bits and the data bus bit width is 16 bits, only 2 public integer data of 7 bits can be transmitted each time, and 16 channels need 8 times to completely transmit the public integer.

Further, the hybrid transmitting the common integer data and the remainder coefficient data includes:

public integer data and partial remainder coefficient data are mixed to form a data packet A for cyclic transmission;

or;

public integer data is used as a data packet A, remainder coefficient data is used as a data packet B, and the data packet A and the data packet B are sent in a mixed mode;

or;

and mixing the public integer data and the partial remainder coefficient data to form a data packet A, taking the rest remainder coefficient data as a data packet B, and mixing and transmitting the data packet A and the data packet B.

Further, the partial remainder coefficient data is remainder high data, which is remainder coefficient data that can be displayed in multiple sets of PWM.

Further, the remainder high data is the iit of the remainder data, or [ (i-b): i ] bit; the remainder data of other bits is used as remainder coefficient data, wherein b is more than or equal to 1;

or, the remainder high data is obtained by calculating the numerical value of the remainder data.

Furthermore, in all the PWMs in a complete display frame, the residue coefficient data in a plurality of groups of PWMs are generated by the residue coefficient data stored in the driving chip, and the residue coefficient data in other groups of PWMs are transmitted by the bus.

Further, in one display frame period, the display timing of the PWM is:

sequence 1: the remainder coefficient data in the odd number groups of PWM are generated by the remainder coefficient data stored in the driving chip, and the remainder coefficient data in the even number groups of PWM are directly transmitted by a data bus; or the remainder coefficient data in the even number group of PWM is generated by the remainder coefficient data stored by the driving chip, and the remainder coefficient data in the odd number group of PWM is directly transmitted by the data bus;

or the like, or, alternatively,

and (2) time sequence: the remainder coefficient data in the first M groups of PWM are generated by remainder coefficient data stored in the driving chip, the remainder coefficient data in the rest groups of PWM are directly transmitted by a data bus, and the public integers are completely transmitted in M groups of PWM display periods.

Further, between the display frames, the time sequence 1 and the time sequence 2 are dynamically switched under the control of the controller.

Further, the time sequence 1 and the time sequence 2 are dynamically switched according to the gray level of the picture, the time sequence 2 is adopted when the gray level of the picture is greater than or equal to a gray level threshold value K, and the time sequence 1 is adopted when the gray level of the picture is less than the gray level threshold value K.

Further, the gray threshold K represents:

the gray value of one complete display frame;

or, the average gray value corresponding to each PWM in a complete display frame;

or judging whether the common integer is smaller than a certain threshold value, and further counting the number of pixel points meeting the conditions in the display area to judge whether the number of the pixel points is smaller than a certain preset value.

Further, the controller or the driving chip stores common integer weight W_QSum remainder weight W_R；

Correspondingly, the transmitted common integer data is changed from Q to Q', and the transmitted remainder coefficient data is changed from R_iIs changed into R_i'；

The gray scale of the final displayThe value is changed from D 'to D' and there are:

wherein, W_Q×Q'＝Q。

Further, said W_R＝2^j，W_RWhen the value is more than 1, the controller supplements and transmits remainder low-order data R [0: j-1%]I.e., bits 0 to (j-1) of the transmission remainder data R.

A gray data transmission system comprises a controller, a data bus and at least one driving chip, wherein the controller is connected with the driving chips through the data bus, the driving chips are cascaded through the data bus, and the controller is the gray data transmission controller.

A method of gray scale data transmission, the method comprising:

s100: the controller divides each frame of gray data into common integer data and a plurality of groups of residue coefficient data;

s200: the controller makes the public integer data and the partial remainder coefficient data into a data packet A, and the rest remainder coefficient data is used as a data packet B;

under control of the controller:

the data packet A is sent in a circulating mode at the front section of the display frame, and the data packet B is sent at the rear section of the display frame; or the data packet A and the data packet B are sent in a mixed mode at the front section of the display frame, and the data packet B is sent at the rear section of the display frame;

or;

and forming a data packet A by using the common integer data, taking the remainder coefficient data as a data packet B, mixedly sending the data packet A and the data packet B at the front section of the display frame, and sending the data packet B at the rear section of the display frame.

Further, remainder coefficient data included in the data packet a or the data packet B sent in the previous segment of the display frame is remainder high-order data, which is remainder coefficient data that can be displayed in multiple groups of PWM.

Further, when the data packet a is composed of common integer data and partial remainder coefficient data, the remainder coefficient data in the data packet a is 1bit, 2bit, or 3 bit.

Furthermore, the front display frame segment and the rear display frame segment are completely sent by common integers to serve as distinguishing nodes.

Further, the data packet A or the data packet B at the front section of the display frame is sent to a driving chip for storage;

and in the rear section of the display frame, the data packet B is not stored and is directly sent through a data bus or sent to a drive chip for storage.

Further, in a complete display frame, the display timing sequence of the PWM is:

sequence 1: the remainder coefficient data in the odd number groups of PWM are determined by the stored remainder coefficient data, and the remainder coefficient data in the even number groups of PWM are transmitted by a data bus; or the remainder coefficient data in the even number group of PWM is generated by the stored remainder coefficient data, and the remainder coefficient data in the odd number group of PWM is directly transmitted by the data bus;

or;

and (2) time sequence: the remainder coefficient data in the first M groups of PWM of the display frame is determined by the stored remainder coefficient data, the remainder coefficient data in the rest PWM are transmitted by a data bus, and the public integers are completely sent in M groups of PWM time sequences.

Further, the display frames are switched between a time sequence 1 and a time sequence 2 according to a gray level threshold K, when the gray level of the picture is greater than or equal to the threshold K, the time sequence 2 is adopted, and when the gray level of the picture is smaller than the threshold K, the time sequence 1 is adopted.

The finally displayed gray value is changed from D' to D ", and there are:

wherein, W_Q×Q'＝Q。

The design can be used for a plurality of situations without dispersionThe minimum display effect is optimized, and the minimum width of the display of the residue coefficient data is changed from 1 pulse to W_RWhen the pulse is larger than 1, the display effect is improved, and meanwhile, compared with Q, the bit width of Q 'is reduced, for example, in 4 non-scattering periods, the bit shift of the public integer to the high bit is 2 bits, and if Q is 8 bits, Q' is 6 bits, so that the occupation of a data bus can be reduced, even the times of sending the public integer data are reduced, and the public integer data can be sent out more quickly.

Further, said W_R＝2^j，W_RWhen the value is more than 1, the controller supplements and transmits remainder low-order data R [0: j-1%]I.e., bits 0 to (j-1) of the transmission remainder data R. As described above, in the 4 scatters, the common integer is shifted to the high order by 2 bits, and the remainder coefficient data is also shifted by 2 bits, which means that the 2-bit remainder coefficient data of the lowest order is lost, so that the remainder coefficient data of 2 bits of the sender needs to be additionally supplemented to ensure the integrity of the gray scale data.

The beneficial effect of this application is:

(1) compared with the traditional controller, the controller divides the gray data into the common integer data and the remainder coefficient data in the gray transmission process, and only stores the common integer data during storage, so that compared with the traditional mode, the requirement on the memory is lower, the capacity and the size of the memory can be reduced, and the chip cost is saved;

(2) in the data transmission process, the controller mixes and sends the public integer data and the remainder coefficient data, so that the driver chip already has the remainder coefficient data when displaying the public integer, the picture display is more uniform, and the ash jumping can be avoided;

(3) the controller mixes and sends the public integer data and the remainder coefficient data, and the remainder coefficient data exist at the beginning of display, so that the public integer does not need to be additionally displayed, and image distortion can be avoided;

(4) the occupied time of the data bus can be saved, and the saved data bus time is used for transmitting the public integer data and remainder coefficient data which need to be stored in the next display frame.

Drawings

FIG. 1 is a hardware schematic of a driver chip;

FIG. 2 is a functional block diagram of one embodiment of a driver chip;

FIG. 3 is a functional block diagram of another embodiment of a driver chip;

FIG. 4 is a schematic diagram of a cyclic transmission of a data packet A;

fig. 5 is a schematic diagram of hybrid transmission of data packet a and data packet B;

FIG. 6 is a schematic diagram of an alternative hybrid transmission of packet A and packet B;

FIG. 7 is a schematic diagram of the present application of separate storage of residue coefficient data;

FIG. 8 is a schematic diagram of the storage of the remainder coefficients in their entirety;

FIG. 9 is a prior art data reception and display schematic;

FIG. 10 is a prior art packet transmission and display relationship diagram;

FIG. 11 is a schematic diagram of the data reception and display of the present application;

FIG. 12 is a diagram of the present packet transmission and display relationship;

FIG. 13 is a schematic diagram of time sequence 1;

FIG. 14 is a schematic diagram of sequence 2;

FIG. 15 is a schematic diagram of the structure of the dynamic switching of sequence 1 and sequence 2;

FIG. 16 is a schematic diagram of a data transmission system;

FIG. 17 is a schematic diagram of the composition of packet A and packet B;

FIG. 18 is a schematic illustration of early remainder coefficient data and display relationships;

FIG. 19 is a functional block diagram of a first memory unit employing a ping-pong architecture;

fig. 20 is a diagram showing an example in which gradation data is transmitted in 32 groups;

fig. 21 is a diagram showing an example in which gradation data is transmitted in 64 groups.

Detailed Description

The technical solution of the present application is further described in detail with reference to the following specific examples, but the scope of the present application is not limited to the following.

It should be noted that, unless otherwise specified, the remainder data and the common integer data described above and in the embodiment refer to the gray scale data of the same display frame in the LED display panel.

In a complete display frame, the gray data is divided into common integer data and remainder data, and a binary gray data of 13 bits is taken as an example for description, and the data of 13 bits is defined as D [12:0], that is, data with 13 bits of bit width. As far as the present is concerned, the gradation data is generally 16 bits at the maximum, and the principle of dividing the common integer data and the remainder data is as follows regardless of the size of the gradation data:

common integer data

Solving an integral function;

remainder data

A remainder function;

d here refers to the gray value that needs to be displayed actually, i.e. the gray value of a certain frame, i.e. the gray value transmitted to the control card (controller), and ideally D and D' (the gray value that is actually displayed) should be equal, i.e. the gray value that is actually displayed is equal to the gray value that needs to be displayed actually. Where N is the weight of the integer part, it can be understood as the number of groups of the common integer data, for example, in this embodiment, let N be 64, that is, include 64 groups of common integer data, that is, Q be D [12:6], R be D [5:0], in other words, the common integer data is the upper data of 7-bit gray scale data, and the remainder data is the lower data of 6-bit gray scale data, and the total number is 64 PWMs. And each 1bit or 2 bits or more of the 6-bit lower data is the remainder coefficient data.

In addition to the above, the present embodiment provides another division method in the art, such as a 13-bit gray scale data, the data form is expressed as a 13-bit binary digit string, the 13-bit binary digit string is divided into common integer data and remainder data, that is, divided by data bits, the upper data is used as the common integer data and the lower data is used as the remainder data, wherein the upper data and the lower data are relative, when the number of division bits is determined, the upper data and the lower data are automatically generated, for example, in a 13-bit gray scale data, when the lower 6 bits are defined as the remainder data, the upper 7 bits are automatically used as common integer data, i.e., the 1 st to 6 th bits are lower data, and the 7 th to 13 th bits are upper data, and vice versa, and when the upper data is determined, the lower data is also naturally determined.

That is, the nature of dividing the gray scale data into common integer data and remainder data, i.e., dividing the gray scale data into upper data and lower data, is also a relatively common way of decomposition in the art, and for example, in patent publication No. CN105096821B, the gray scale display driving method and the gray scale display driving apparatus, the gray scale data is divided into more significant bits and less significant bits.

Based on the decomposition, it can be seen that, for any one gray scale data, the common integer data is fixed, for example, in the gray scale value of 1110111111011, the common integer data is fixed to 1110111, the weight of the common integer data is 64, that is, the common integer data needs to be displayed 64 times, which is equivalent to that the common integer data needs to be circularly displayed 64 times, so that the common integer data is stored in the application for repeated use, and compared with the conventional mode in which the entire gray scale data is stored by 13 bits, the application only stores 7 bits of the common integer, which is equivalent to saving nearly half of the memory capacity, so the application has the technical progress of lower chip cost and smaller memory size.

The remainder data can be further split as follows:

r < 5 >: shown within 32 of them.

R < 4 >: shown within 16 of these groups.

R < 3 >: shown in 8 of these groups.

R < 2 >: shown in 4 of these groups.

R < 1 >: shown in group 2.

R < 0 >: shown in group 1 thereof.

Wherein, R < 0 >]-R[5]It is the bit order of the remainder coefficient data, i.e. the remainder data is decomposed into 1bit remainder coefficient data (or into multiple bits), wherein the remainder coefficient data of each bit may be different. Wherein, R < 5 >]The residue coefficients in 32 PWM sets, i.e., values representing 32 residue coefficient data, R4, can be determined]The residue coefficient, R3, of 16 PWM sets can be determined]The residue coefficients in 8 sets of PWMs can be determined, and so on. Accumulating into 63 groups, i.e. 63 residue coefficient data R_iThe serial numbers are R according to the display sequence₁-R₆₃. That is, there is a group of PWMs that contains no residue coefficient, only common integer, or the residue coefficient of the group is considered to be fixed to 0, which is equivalent to 64 PWMs that each contain a common integer data and residue coefficient data, and the PWM containing both common integer data and residue coefficient data is referred to as complete PWM in this application.

The value of N is 2ⁿIn this case, the common integer data and the remainder data are just divided by binary digits, that is, the upper bits of the gray scale data are used as the common integer data and the lower bits of the gray scale data are used as the remainder data, which is most preferable and most common in the example application. At this time, the common integer data, the remainder data, and the remainder high-order data can be directly extracted from the gradation data. Such as R < 5 > above]Is the most significant bit of the remainder data, R4]Remainder sub-high bits, etc., and the remainder sub-high bits referred to herein may be divided by R [0]]Any other than the above, but in general R1]And R2]And also does not meet the actual requirements.

When N does not take the value of 2ⁿIt cannot be defined by the high or low bits of the gray scale data, and the common integer data and the remainder coefficient data are calculated or determined by a look-up table (which is essentially a background calculation). When the decimal number is 7675 and N is 40, the common integer data is obtained by converting 1110111111011 as a column

After calculation, it is publicThe integer becomes 191, converted to binary 10111111, the remainder data is 35, and converted to binary 100011, and it is obvious that neither 10111111 nor 100011 is taken directly from 1110111111011 in digits, but is confirmed by calculation. In this case, the common integer data can still be represented by 10111111, while 10111111 is stored, while the remainder data cannot be taken from 100011, where 35 represents 35 means that the remainder coefficient of 35 PWM groups is 1 and the remaining 5 groups is 0 among 40 PWM groups, and 100011 if according to R [0]]-R[5]If the method (2) is shown, 63 groups are also shown. That is, in this case, the remainder high data cannot be directly taken from 100011 in bit order. But can only be taken into value by calculation. Assuming that the weight of the remainder coefficient is 1, the remainder data is less than 40, assuming that the high order of the remainder stores 1bit, at this time, we can set that when the remainder data is greater than or equal to 20, the high order of the remainder is 1 (indicating that the remainder coefficient data in 20 groups is 1), otherwise, the high order of the remainder is 0, and the rest of the remainder coefficients are transmitted in real time through a data bus. The remainder high 1 is stored in memory as 20 sets of remainder coefficients, and the 20 sets of remainder high need not be transmitted multiple times over the bus. In this example, the high bits of the remainder are not taken from a bit of the remainder data, but are calculated by determining a plurality of sets of remainder coefficients for the high bits of the remainder, and multiplying the high bits of the remainder by the number of sets plus the remainder coefficients of the remaining sets, the sum being equal to the remainder data. The existence of the high bits of the remainder enables a plurality of groups of remainder coefficients not to be sent repeatedly through the bus, thereby saving bus time for sending other data, such as integer data. It is not necessary to limit the remainder data to be greater than 20, as long as the remainder high order data can represent multiple sets of remainder coefficient data, for example, even if the remainder data is 10, the remainder high order data can be 1, which means that the remainder coefficient is 1 in 10 sets, and it is only necessary to satisfy that the common integer can be sent in the time sequence displaying 10 sets of PWM. Calculation of remainder coefficient data and common integer data by way of a look-up table is equally applicable to values of N to 2ⁿThe situation (2).

Except for the binary gray scale data, the principle is the same for decimal and hexadecimal data processing. In the present embodiment, a decimal number is used as an example, the decimal data 8191, assuming that N is equal to 64, the common integer data is 127, and 63 is used as remainder data, 8191 includes 64 groups 127, and the remainder data 63 may show 1 in each group, and a group that does not include remainder data remains, or the remainder data of the group is considered to be constant 0, and the principle is completely consistent with the binary system. The final result thus represented is still 8191.

A gray data transmission controller displays the front section of a frame, the controller mixedly sends public integer data and remainder coefficient data, and displays the rear section of the frame, the controller only sends the remainder coefficient data; and the requirements are met,

where D' represents the gray value actually displayed for a certain frame, Q represents common integer data, and R_iAnd representing the residue coefficient data, wherein N is the number of times of circular display of the common integer data in the display frame, and N is the number of times of display of the residue coefficient data in the display frame. Wherein D' is the gray value actually displayed by the display frame, and the gray value may be greater than or less than the actual gray value D, and is equal to the actual gray value D under the optimal display effect. For example, the number of groups N actually displayed here is smaller than the weight of the integer part, and is smaller than the actual gray scale value, and is equal to the actual gray scale value only when the two are actually equal.

The controller acts on the driving chip and transmits common integer data and remainder coefficient data of the gray data through the data bus. A complete gray scale datum is divided into common integer data and remainder coefficient data under the action of the controller, and the decomposition is as described above. And the decomposed common integer data and remainder coefficient data are transmitted to a driving chip for display through a data bus under the control of the controller.

Optionally, in the gray scale data transmission controller, the public integer data and the remainder coefficient data sent in a mixed manner at the front segment of the display frame are stored in the driver chip, and the remainder coefficient data sent at the rear segment of the display frame are not stored.

Optionally, a gray data transmission controller, the controller or the driving chip stores a common integer weight W_QSum remainder weight W_R(ii) a Correspondingly, the transmitted common integer data is changed from Q to Q', and the transmitted remainder coefficient data is changed from R_iIs changed into R_i'; the finally displayed gray value is changed from D' to D ", and there are:

wherein, W_QQ ═ Q. I.e. by configuring the remainder weight W_RThe minimum width of the display to optimize the display effect.

Optionally, a gray data transmission controller, W_R＝2^j，W_RWhen the value is more than 1, the controller supplements and transmits remainder low-order data R [0: j-1%]Namely, the 0 th to (j-1) th bits of the remainder data R are transmitted in complement, and the remainder low-order data R [0: j-1 ] is transmitted in complement]The j times of sending are finished, for example, in 4 non-scattering times, j is 2, that is, supplement 2 additional sending times, which are respectively used for sending the 0 th bit and the 1 st bit, in other words, which lower data are lost in several non-scattering processes and then supplement the lower data for sending, wherein all the lower data can be sent out 1 time, that is, 1 time, the lost lower data are all sent out, or 1bit can be sent out each time, that is, j times of sending are required to be finished, and simultaneously, an indefinite number of bits can be sent out once until all lost remainder data are sent out. As can be seen from the above analysis, if the remainder data of lower bits is not transmitted in a complementary manner, i.e., a few remainder coefficients are less, this results in D "being less than D'.

Optionally, a gray data transmission controller, remainder weight W_RStored in a drive chip or a controller, and only transmits the remainder coefficient data R when transmitting_i. When the remainder coefficient data is provided with the weight, the public integer data is also necessary to be synchronously provided with the weight, for example, a gray value of 13 bits, if 4 pieces of data are not scattered, the minimum number is 2 bits for extra transmission, and if N is ensured to be unchanged, the remainder coefficient data is shifted by two bits in a sequential manner and is changed into R [7: 2]]The common integer data is sequenced and then changed into D [12:8 ]]In other words, the common integer is the same as the original oneThe 7bit is changed into 5bit, in this case, the data bus can transmit 3 pieces of common integer data at a time, that is, the 16-channel common integer data can be transmitted only 6 times, and compared with the original 8 times, 2 times of data bus transmission is saved.

Optionally, a gray data transmission controller, the remainder weight W of each set of remainder coefficient data_RThe same; or, the residue weight W of each group of residue coefficient data_RConfigured by a controller or register. Theoretically using the remainder weight W of each set of remainder coefficient data_RThe operation amount of the chip can be reduced as the optimal implementation scheme, but the modification of the remainder weight W by a controller or a register is not excluded_RThe situation (2).

Optionally, in one embodiment, W_R＝2^j，W_RWhen the value is more than 1, the controller supplements and transmits remainder low-order data R [0: j-1%]I.e., bits 0 to (j-1) of the transmission remainder data R. Several groups of PWM data for displaying remainder coefficient loss without compensation are correspondingly supplemented, as in the above embodiment, when 4 pieces of non-scattered data are adopted, 3 pieces of remainder coefficient data are lost, and according to the above record, 3 pieces of remainder coefficient data, namely R1, can be known]And R < 0 >]I.e., the lower 2 bits of the residue coefficient data are lost, supplemental display should be required to ensure that the gray scale data is not distorted. And adding P groups or P-1 groups of PWM for supplementary display, analyzing that 1 group of PWM has no remainder coefficient data as above, and displaying a remainder coefficient data in a reorganization mode, namely only needing to supplement and display the P-1 group. Each set of displayed gray scale data is

Wherein, P ═ j, T_jThe value of each bit with the lost bit width is the value of the j-1 bit; v_jIs T_jCorresponding weight of 2^j. For example, j is 1, i.e., 2 are not scattered, and the 0 th bit, i.e., R [0], is displayed in addition]When j is 2, 4 are not scattered, and the 1 st bit and 0 th bit are displayed in addition, that is, R1]And R < 0 >]. If j is 2 in 4 non-scattering data, the data displayed is T₁×1、T₂X 2. Referring to FIGS. 20 and 21, the supplementary numbersAccording to the schematic diagram shown, i.e. T₁、T₂、T₂Three remainder coefficients are displayed schematically, and T is sent by occupying a data bus when residue coefficient data is not transmitted₁、T₂、T₂And displaying. Corresponding 8 non-scattering supplementary displays are T₁×1、T₂×2、T₃X 4, i.e., the accumulated complement of 7 remainder coefficient data. When the overall value of the gray data is large, the lost remainder low-order data can not be supplemented, and when the overall gray data value is small, the lost remainder low-order data must be supplemented, the low-order data in the graph is lost remainder low-order data, the medium-order data is remainder coefficient data sent through a data bus, and the no-data means that the remainders coefficient data in the reorganization is generated by the stored remainder high-order data.

In order to further make the working principle of the controller clearer, the present embodiment further provides a driving chip structure used in cooperation with the controller, and as shown in fig. 1, a gray data display driving module (i.e., a driving chip) includes a first memory 100, and a PWM generating unit 200 and a remainder coefficient parsing unit 400 connected to the first memory 100, where the remainder coefficient parsing unit 400 is connected to the PWM generating unit 200, and the PWM generating unit 200 generates a PWM for displaying according to the remainder coefficient data parsed by the remainder coefficient parsing unit 400 and the common integer data stored in the first memory 100.

Within a complete display frame, the display frame is divided into N groups of PWMs, where N is the above-mentioned integer part weight, where each PWM includes a common integer data and remainder coefficient data (from the above analysis, it can be seen that 1 group of PWMs does not include remainder coefficient data), where the remainder coefficient data is obtained from either direct transmission via the data bus or from the remainder high-order data stored in the first storage unit 100. The total integer data and the remainder coefficient data may be displayed as 1 PWM or 2 PWMs, and 1 or 2 of the data are referred to as 1 set of PWMs. In general, the display is performed as 1 PWM. The core of the application is that an original display frame is divided into N groups of PWM for display. That is, the generated PWM includes two types, one PWM is composed of common integer data + remainder high data, and the other PWM is composed of common integer data + remainder coefficient data.

The first memory 100 is connected to the data bus, receives and stores data packets transmitted from the data bus, the data stored in the first memory 100 includes not only common integer data but also residue coefficient data, and the first memory 100 provides the stored data to the residue coefficient parsing unit 400 and the PWM generating unit 200.

The remainder coefficient parsing unit 400 includes two input interfaces, one of which is connected to the data bus to receive the data packet transmitted by the data bus for parsing and outputting remainder coefficient data, and the other of which is connected to the first memory 100 to read and parse the stored data packet to obtain corresponding remainder coefficient data.

If the remainder coefficient data is not stored, the remainder coefficient data needs to be sent through a data bus, namely 63 times, in addition, common integer data also needs to be sent, the common integer data generally needs to be sent for completion for many times, generally, the transmission quantity of the data bus is generally 16 bits, for a 16-channel chip, the required common integer data quantity is 16 x 7 bits, the data bus can only send 2 common integer data of 7 bits at a time, and therefore 8 times is needed for transmission completion, when the common integer data is transmitted, the remainder coefficient data is lacked in the displayed PWM, the picture is uneven, and the performance is poor. Therefore, the common integer data is generally not displayed when being transmitted at present, the principle of the common integer data is shown in fig. 9 and fig. 10, inter-frame black fields occur in the case, when the chip refresh rate is large enough, the common integer data is generally difficult to find by naked eyes, and in order to solve the problem, the common integer data is additionally displayed when the remainder coefficient data is lacked, so that the gray skipping phenomenon is caused, and the picture uniformity is not enough.

In order to solve the technical problem, in the present application, the common integer and remainder coefficient data are mixed and transmitted, so that the remainder coefficient data is available at the beginning of the display, thereby ensuring the integrity of the PWM and improving the display effect, the principle is as shown in fig. 11 and fig. 12, referring to fig. 11, a certain delay exists between the receiving and the displaying of the data, and the duration is limited by the transmission rate of the data bus, and generally, the delay cannot be observed by naked eyes, so the receiving and the displaying are generally considered to be synchronous in the subsequent schematic diagrams, but a skilled person should know that the delay still exists actually, for example, in fig. 12, the common integer data packet and the display are aligned, wherein the first common integer data packet on the left side of fig. 12 refers to the common integer data of the previous display frame instead of the current frame.

In one embodiment, a specific implementation scheme for hybrid transmission of common integer and remainder coefficient data is as follows:

the front segment of the display frame, the common integer data and the remainder coefficient data are mixed and sent to the first memory 100 for storage. That is, when the common integer data is transmitted, the remainder coefficient data is also stored in the first memory 100, so that the PWM generating unit 200 can read not only the common integer data but also the remainder coefficient data, thereby generating a complete PWM for display.

As described above by taking the 13-bit gray scale data as an example, the common integer data is 7 bits, and each time 2 pieces of common integer data are transmitted, the data bit width occupies 14 bits, so that 2 bits of remainder coefficient data can be additionally transmitted.

Since the common integer data needs 8 transmissions, that is, 2 bits by 8-16 bits of remainder coefficient data can be additionally transmitted, and the chip has 16 channels, that is, each channel corresponds to 1bit of remainder coefficient data. In other words, 2 bits of remainder coefficient data are required to be sent each time, and the number of the common integer data is 2, that is, 2 channels of data are included in 1 data packet, that is, each channel corresponds to 7 bits of common integer data and 1bit of remainder coefficient data, and a schematic diagram thereof can be referred to as shown in fig. 17.

In addition to the above-described embodiments, when the common integer data is less than 7 bits, the remainder coefficient data can be transmitted more than 1bit as long as the common integer data + the remainder coefficient data is less than or equal to 16 bits. Those skilled in the art will recognize that any combination of data that conforms to this formula is intended to be within the scope of the present application.

Obviously, in order to reduce the capacity of the memory as much as possible, that is, to reduce the capacity of the first memory 100, the remainder coefficient data is naturally as small as possible, and therefore, it is an optimal choice to store only 1bit of remainder coefficient data per channel. For example, in the above-mentioned 13-bit gray scale data, the remainder coefficient data is 6 bits, and are respectively R0 to R5, and it is preferable to store which remainder coefficient data is stored, since the common integer data needs 8 times to be transmitted, and the time and display of the transmitted data are substantially equal, that is, when the common integer data is transmitted, 8 PWMs are displayed, and in order to ensure that each PWM has the remainder coefficient data, it is required that the stored remainder coefficient data can be displayed in at least 8 groups, obviously, R0 to R2 are not satisfied, and R3 to R5 are all satisfied, that is, the stored remainder coefficient data should be remainder high-order data, and the principle thereof can be referred to fig. 3.

Furthermore, which bit of remainder coefficient data is stored in R3-R5 has the best effect, because the remainder coefficient data only stores one bit, and the rest needs to be transmitted through the data bus, based on the analysis, it can be seen that R5 needs to be displayed in 32 groups, that is, needs to be transmitted 32 times, and obviously, when the most significant bit of the remainder coefficient data is stored, the time occupied by the data bus for transmitting the data can be reduced to the greatest extent, that is, the most significant bit R5 of the remainder coefficient data is sent to the first memory 100 for storage. That is, the common integer data and the partial remainder coefficient data are mixed to form a data packet a for cyclic transmission, where the partial remainder coefficient data is preferably remainder high-order data, and it is not necessary to transmit the highest order, but it can be said that the time occupied by the data bus can be saved to the greatest extent by transmitting the highest order of the remainder data. Data reception and display schematic the data reception and display schematic can be seen with reference to fig. 4, where the nth group n +1 in fig. 4 represents different display lines of the LED panel. Since the data packet a contains the residue coefficient data, the PWM which starts to be displayed also contains the residue coefficient data, so as to ensure the integrity of the PWM.

As described above, in another aspect, the most significant bit of the remainder coefficient data is stored, which reduces the data transmission amount of the data bus, the original data bus needs to send the remainder coefficient data 63 times, and after the most significant bit of the remainder coefficient data is stored, only 31 times of sending is needed, which is equivalent to reducing half of the transmission amount of the data bus, that is, compared with the prior art, the present application has a technical progress of lower data bus transmission load.

Besides the above mixing method, the embodiment also provides other mixing methods for the common integer data and the remainder coefficient data, which are specifically as follows:

or;

The schematic diagram of data reception in the above two manners can be shown in fig. 5 and fig. 6, where data packet a and data packet B can be sent alternately, or several data packets a can be sent more than once and 1 data packet B can be sent, and based on the above analysis, it can be seen that, for a chip with 16 channels, at least 1bit of gray scale data needs to be sent in each channel, for a chip with 16 channels, at least 16 bits of remainder coefficient data needs to be sent, and the maximum data bus transmission amount is 16 bits, that is, only 1 time of data packet B is sent, the requirement for remainder coefficient data can be met, but the situation of sending many times is not excluded, for example, when 2-3 bits of remainder coefficient data are sent in each channel, the remainder coefficient data can be completely sent many times, sending remainder coefficient data greater than 1bit has the advantage that the transmission amount of the data bus can be further reduced, and the disadvantage that the storage capacity of the first memory 100 is increased, so that the chip cost increases.

Referring to fig. 6, the transmission sequence of the data packets B may be set arbitrarily, and in order to ensure that the PWM has the common integer data as soon as possible, the data packets B should be transmitted as far ahead as possible, that is, the first data packet and the second data packet should include the data packet a and the data packet B, especially when the data packet a does not include the remainder coefficient data.

In addition to the above-defined situation of the remainder high order data, the remainder coefficient data that is mixedly transmitted may be determined by means of a lookup table, for example, 20 pieces of remainder coefficient data are stored if the remainder coefficient data needs to be displayed in 20 groups, and specifically, which 20 pieces of remainder coefficient data are determined by means of the lookup table, for example, if each displayed remainder coefficient data in 20 groups is 1, the remainder high order data determined by the lookup table is 20. The nature of the remainder high data representation herein does not refer to the number of bits of data, but is determined by a look-up table. In other words, the essential representation of the remainder high data in the present application is the remainder data that can determine the remainder coefficient data in the plurality of sets of PWM.

Compared with the method that the common integer data and the partial remainder coefficient data are mixed to form the data packet A for cyclic transmission, when the data packet A only comprises the common integer data, the displayed first PWM does not comprise the remainder coefficient data or the common integer data. For example, the first is that the data packet B does not contain a common integer, the first is that the data packet a does not contain remainder coefficient data, the influence on the display is that the first PWM gray scale data is incomplete, and when the plurality of PWM data equivalent to the conventional mode are incomplete, the scheme still has great progress and advantages, taking the gray scale data of 13 bits as an example, the common integer data is 64 groups, that is, 64 groups of PWM need to be displayed, while the remainder coefficient data is only 63 groups, and exactly one group has no remainder coefficient data, so that the data packet a is sent first just in line with the actual situation, that is, the data packet a is sent first (when the data packet a does not contain remainder coefficient data) is the best choice.

When the data of the front section of the display frame is sent out, the data transmission of the rear section of the display frame is started, and because the common integer data is stored in the first memory 100, the data of the remainder coefficient is only sent out at the rear section of the display frame.

The sending mode comprises the following steps:

(1) the residue coefficient data is sent to the residue coefficient parsing unit 400, which can be configured as shown in fig. 1 or fig. 3, that is, the residue coefficient data is sent to the PWM generating unit 200 through the residue coefficient parsing unit 400.

(2) The remainder coefficient data is sent to the first memory 100 for storage; the structure of the data bus can be seen in fig. 8, in which case the data bus can save a lot of time for transmitting data, and the difference is that the previously stored residue coefficient data needs to be overwritten, which may cause a delay (as mentioned above, the delay is negligible) for data transmission and reception.

(3) The remainder coefficient data is directly transmitted to the PWM generating unit 200, and the structure thereof can be as shown in fig. 2, that is, the remainder coefficient data is directly transmitted to the PWM generating unit 200 for display without passing through the remainder coefficient parsing unit 400, in which case the timing of the transmitted data can be controlled by a clock or a controller (control card).

To sum up, the remaining remainder coefficient data transmitted at the later stage of the display frame may be entirely divided into two types, i.e., the remaining remainder coefficient data is transmitted through a data bus without being stored, or the remaining remainder coefficient data is stored continuously, provided that the previously stored remainder coefficient data is completely displayed, for example, the remainder coefficient data R [5] must be stored before the remaining remainder coefficient data is transmitted after 32 sets of PWM are displayed.

It is worth emphasizing that the display frame front segment and the display frame rear segment in the present application are all sent out in a common integer as a differentiation node. That is, the common integer data is transmitted as the front segment of the display frame, and the common integer data is transmitted as the rear segment of the display frame.

Optionally, in an embodiment, the partial remainder coefficient data is 1bit or ibit, where i is greater than or equal to 2 and less than or equal to n, where n is a bit width of the remainder coefficient data. For example, in the 13-bit gradation data, the remainder coefficient data is 6 bits, that is, n is 6. The partial remainder coefficient data is remainder coefficient data mixed with common integer data to be used as a data packet a, and when the data packet a is sent in a circulating mode, the common integer data and the remainder coefficient data can be understood to be sent at the same time, wherein the remainder coefficient data can be 1bit (here, 1-bit remainder coefficient data per channel of a chip is referred to, and not only 1-bit remainder coefficient data in the whole data packet a). The method can also be multi-bit remainder coefficient data, when i is equal to n, the essence of the method is that the gray data is sent as a whole, and the scheme generally does not adopt the mode in actual operation, that is, the value of i is generally not more than 3.

Optionally, in an embodiment, the maximum data amount of the data packet B is mbit, where m is the number of channels of the driver chip, that is, each channel corresponds to 1bit or ibit remainder coefficient data, currently, a main chip channel is generally 16 channels, and since a bit width of a data bus is 16 bits, the maximum data packet is generally 16 bits, where it can be understood that, for a 16-channel chip, if each channel transmits 1bit remainder coefficient data, it can be completed by transmitting 1 data packet B, when each channel needs 2bit remainder coefficient data, it needs 2 data packets B to be transmitted, in an actual situation, the remainder coefficient data in the data packet B is 1bit, that is, only 1 data packet B is needed each time to transmit the remainder coefficient data required by a complete channel, so as to reduce the number of transmission times of the remainder coefficient data, the occupied time of the data bus is saved, and meanwhile, because the first storage unit 100 also stores the remainder coefficient data, when the first storage unit 100 adopts two memories to work according to a ping-pong structure, the saved time can be used for sending the common integer data of the next display frame (namely, the common integer data and the remainder coefficient data of the next display frame are sent in a mixed manner).

As is known from the above description, when the common integer data and the remainder coefficient data are mixed and transmitted for storage, the stored remainder coefficient data is preferably remainder high-order data, that is, the lowest order and the next lowest order of the non-remainder coefficient data of the partial remainder coefficient data, that is, the lowest order and the next lowest order of the remainder coefficient data are generally stored, and the storage significance is not great.

Optionally, in an embodiment, the partial remainder coefficient data is the most significant bit or the second most significant bit, or the most significant bit + the second most significant bit of the remainder coefficient data, that is, when the remainder coefficient data is 2 bits, the 2-bit data, i.e., the most significant bit and the second most significant bit, of the remainder coefficient data may be stored, so that the time occupied by the data bus for transmitting the remainder coefficient data may be reduced to the greatest extent, and the saved time may be used for transmitting integer data or registers, instructions, and the like.

In order to further improve the uniformity of gray scale data display, the present embodiment further designs which sets of PWM are controlled by the stored residue coefficient data.

From the above analysis, it can be known that when the remainder high-order data is stored in the first memory 100, it can determine the gray-scale data in the multiple groups of PWM, for convenience of explanation, or exemplified by gray-scale data of 13 bits, where the common integer is 7 bits and the remainder coefficient is 6 bits. From the above, it can be seen that R5 is displayed in 32 groups, and there are 64 groups of PWM in total, that is, R5 can be controlled specifically in which groups to display, and several embodiments are provided in this application.

Optionally, in an embodiment, in all the PWMs in a complete display frame, several sets of residue coefficient data are generated from the residue coefficient data stored in the first memory 100, and residue coefficient data in other sets of PWMs are transmitted by a bus, that is, it is not limited in which sets of PWMs the residue coefficient data stored in the first memory 100 are specifically displayed, that is, it is enough to display randomly, that is, R5 is not emphasized to specifically control which sets, which may be the first 32 sets, the middle 32 sets, the last 32 sets, or the random display 32 sets, but those skilled in the art should know that since the common integer data has the largest influence on the PWM display, the common integer data should be transmitted as soon as possible, if the stored residue coefficient data controls the last 32 sets, this means that the first 32 sets need to transmit additional residue coefficient data, and the data bus cannot transmit data packet a and data packet B at the same time, this greatly delays the common integer data transfer time.

Alternatively, in an embodiment, within one display frame period, the PWM is displayed according to the time sequence 1, that is, the residue coefficient data in the odd number groups of PWM are generated from the residue coefficient data stored in the first memory 100, and the residue coefficient data in the even number groups of PWM are directly transmitted through the data bus, as shown in fig. 13.

As can be seen from fig. 13, in the displayed PWM, the integers (common integer data) + the remainder high bits, which are the remainder coefficient data stored in the first memory 100, are displayed in the odd-numbered group, whereas only the integers (common integer data) in the even-numbered group PWM do not include the remainder high bits, but the remainder coefficient data must be displayed in the actual display, and thus in the even-numbered group PWM display, the remainder coefficient data must be transmitted through the data bus for padding. In this case, the mixed sending of the common integer data and the remainder coefficient data is that a data packet a is formed by mixing the common integer data and the partial remainder coefficient data, the remaining remainder coefficient data is used as a data packet B, and the data packet a and the data packet B are sent in a mixed way, wherein the data packet a and the data packet B adopt an alternate sending mode. The drawback is that the common integer takes longer to transmit to completion. Suppose that the gray scale value D has 13 bits; the weight is 64, and 64 groups are displayed, so that the common integer data is D [12:6], the remainder coefficient data is D [5:0] (assuming that a plurality of non-scattered data is not considered here), one packet a transmitting integers can transmit 2 common integer data and 2 remainder high bits, i.e., { D0[12:5], D1[12:5] }, the principle of which can be seen in fig. 17, i.e., the packet a includes the common integer data of the point P1 and the point P2, and the remainder coefficient data of the point P1 and the point P2, where the points P1 and P2 correspond to D0 and D1, and the packet B is also the same and includes the remainder coefficient data of a plurality of points, and generally, when only 1-bit remainder coefficient data is transmitted, one packet B can include the remainder coefficient data of 16 points at most. Assuming a total of 32 rows and 16 channels per IC, a total of 32 x 16 to 512 integer data needs to be stored; assuming that the time for transmitting a joint data packet on the bus is close to the display time of one row, it is required to 512/2 ═ 256 row display times, i.e. 256/32 ═ 8 group display times, for transmitting all integer data (including remainder high order). For the display of uniformity, it is assumed that the high-order D [5] of the remainder controls the residue coefficients of the 1/3/5/7 … 63 th odd-numbered groups of 32. Based on the above analysis, it can be seen that the common integer originally needs to be transmitted only 8 times, but in this embodiment, since the remainder coefficient data (data packet B) needs to be inserted at intervals, the common integer data can be completely transmitted at the 15 th time, which is equivalent to delaying the duration of the front segment of the display frame by phase change, and the defect is that the picture is torn, but when the gray data is low, the effect is not substantially affected.

Sequence 1 in addition to the above display manner, the odd and even groups may be interchanged, that is, the residue coefficient data in the even group PWM is generated from the residue coefficient data stored in the first memory 100, and the residue coefficient data in the odd group PWM is directly transmitted through the data bus, except that the first data packet transmitted in the display sequence must be a residue coefficient data packet, which makes the first PWM displayed have no common integer, but hardly has any effect on the whole display frame, and the principle can be shown in fig. 18.

When packet a has only common integer data and packet B is residue coefficient data, it is obvious that when packet a is sent first, the first set of PWMs has no residue coefficients to use. Based on the above, the number of groups displayed by the remainder coefficient data is 1 less than that of the common integer data, for example, in the gray scale data of 13bit, if the weight of the common integer data is 64 (64 groups are displayed), the remainder coefficient data is only 63 groups, that is, there is one group of PWM that necessarily has no remainder coefficient data, so when the data packet a only has the common integer data and the data packet B is the remainder coefficient data, the remainder coefficient data is just not displayed by the first group of PWM.

In other words, the timing sequence 1 defines that the stored residue coefficient data and the residue coefficient data transmitted by the data bus are alternately and cyclically used in the displayed PWM sequence, and does not define which particular set of residue coefficient data is derived from, that is, when the odd set uses the stored residue coefficient data, the even set inevitably uses the residue coefficient data transmitted by the data bus, and vice versa.

Optionally, in an embodiment, in one display frame period, the PWMs are displayed according to the time sequence 2, the remainder coefficient data in the first M groups of the PWMs are generated from the remainder coefficient data stored in the first memory 100, the remainder coefficient data in the remaining PWMs are directly transmitted by the data bus, and the common integers are all sent out in the M groups of the PWM display periods, the principle of which can be shown in fig. 14. The first M groups of PWMs display integers (common integer data) + remainder high bits, where the remainder high bits are remainder coefficient data stored in the first memory, that is, in the first M groups, it is not necessary to additionally occupy a data bus to transmit the remainder coefficient data, and the common integer data can be quickly sent out, taking the gray scale data of 13 bits as an example, 7 bits of common integer data, and a 16-channel chip can completely transmit the remainder coefficient data only 8 times, that is, M is 8. The present embodiment has an advantage that the common integer data can be transmitted as quickly as possible, and has an advantage that the tearing degree of the picture can be reduced, and has a disadvantage that the PWM display is not as uniform as the time sequence 1, but when the gray scale data is large, the influence of the remainder coefficient data on the picture is small, and the uniformity is not substantially affected.

Optionally, in an embodiment, the remainder coefficient data required by the time sequence 1 and the time sequence 2 are provided by the remainder coefficient parsing unit, that is, the remainder coefficient parsing unit 400 parses out corresponding remainder coefficient data according to the time sequence 1 or the time sequence 2 and sends the remainder coefficient data to the PWM generating unit 200, that is, in the display process, the remainder coefficient parsing unit 400 parses the remainder high-order data stored in the first memory 100 to obtain the remainder coefficient data, or directly sends the remainder coefficient data transmitted by the data bus to the PWM generating unit 200.

In addition to the above, since timing 1 and timing 2 are good and bad respectively, and the combination of them is definitely the best selection scheme, this embodiment also provides a scheme for dynamically switching timing 1 and timing 2, that is, in one embodiment, timing 1 and timing 2 can be dynamically switched. Based on the above analysis, it can be seen that when the gray data values are different, it is better to display with different time sequences, where the gray value is the whole gray of only one display frame. That is, in a continuous multi-frame picture, switching between timing 1 and timing 2 can be performed in a dynamic switching manner. And when the gray level of the picture is greater than or equal to the gray level threshold value K, adopting a time sequence 2, and when the gray level of the picture is less than the gray level threshold value K, adopting a time sequence 1.

In addition to the above switching manner, the time sequence 1 and the time sequence 2 can also be switched by a manual configuration manner.

Referring to fig. 15, a gray data display driving module (i.e., a driving chip), includes a first memory 100, and a PWM generating unit 200 and a remainder coefficient parsing unit 400 connected to the first memory 100, the remainder coefficient parsing unit 400 is connected to the PWM generating unit 200, the PWM generating unit 200 generates a PWM according to the remainder coefficient data parsed by the remainder coefficient parsing unit 400 and the common integer data stored in the first memory 100 for displaying, the switching of the time sequence 1 and the time sequence 2 is completed by a controller/logic processing module 500, the controller/logic processing module 500 is connected to the remainder coefficient parsing unit 400, the controller/logic processing module 500 is provided with a built-in threshold K, and controls whether the remainder coefficient parsing unit 400 parses the remainder coefficient data stored in the first memory 100 or the remainder coefficient data transmitted through the data bus according to the threshold K.

Alternatively, in an embodiment, the controller/logic processing module 500 may be implemented by a controller in a gray scale transmission system, and the principle of the controller may be as shown in fig. 16, where the controller is connected to each stage of driving chips and is used to control whether the remainder coefficient parsing unit 400 receives data transmitted by a data bus or parses remainder high-order data stored in the first memory 100.

Besides, a logic processing module may be separately designed to implement the above control, wherein the logic processing module may be integrated with the driving chip.

Whether it is a controller or a logic processing module, the essence is realized by controlling a clock signal of a display timing, for example, the high-level residue coefficient parsing unit 400 parses residue high-level data stored in the first memory 100, and the low-level data bus directly transmits residue coefficient data to the residue coefficient parsing unit 400 and outputs the residue coefficient data to the PWM generating unit 200.

Optionally, in an embodiment, the gray threshold K represents a gray value of a complete display frame, or represents an average gray value corresponding to each PWM in a complete display frame; or judging whether the common integer is smaller than a certain threshold value, and further counting the number of pixel points meeting the conditions in the display area to judge whether the number is smaller than a certain preset value. Whether the average gray value is used as the reference of the gray threshold value K or the whole gray value is used as the reference of the gray threshold value K, the gray value of the picture, namely the brightness of the picture, can be finally measured.

Optionally, in an embodiment, the remainder coefficient parsing unit 400 and the PWM generating unit 200 are packaged together as a PWM generating device. That is, the remainder coefficient parsing unit 400 and the PWM generating unit 200 are different functional units in the same module in terms of hardware representation, that is, the design is equivalent to a PWM generating apparatus in the prior art, and this design can make the driving chip simpler in structure and smaller in occupied area.

Optionally, in another embodiment, the PWM generating unit 200 is packaged as a PWM generating device, and the remainder coefficient analyzing unit 400 is electrically connected to the PWM generating device. In the present embodiment, the PWM generating unit 200 and the remainder coefficient parsing unit 400 are two independent modules in representation form, and the PWM generating unit 200 and the remainder coefficient parsing unit 400 are electrically connected to implement data transmission.

In other words, the residue coefficient parsing unit 400 and the PWM generating unit 200 referred to in the present application are limited by the functions of the modules, and are not specific to the hardware structure, and all modules having the functions of the two are known in the art and can be used in the present application as an alternative.

The remainder coefficient parsing unit 400 is essentially a logic module, and functions to select corresponding remainder coefficient data to be input into the PWM generating unit 200, as in the above embodiment, the remainder coefficient parsing unit 400 may be controlled by a controller, or may be controlled by a logic processing module, or is a logic module itself, and the remainder coefficient data can be selectively output according to a time sequence 1 or a time sequence 2 in combination with a clock module, and all modules known in the art that can achieve this function may be used as the remainder coefficient parsing unit 400, or should be regarded as the remainder coefficient parsing unit 400, and if only the name of a function module is changed, the function that is finally achieved should be the same as the remainder coefficient parsing unit 400 in this embodiment.

In addition to the solutions described in the above embodiments, the present embodiment further provides another solution for storing remainder coefficient data, in a gray scale data display driving module, a small storage is added for storing remainder coefficient data, as shown in fig. 7, which includes a first storage 100 and a second storage 300, a PWM generating unit 200 connected to the first storage 100, a remainder coefficient parsing unit 400 connected to the second storage 300, and the remainder coefficient parsing unit 400 is connected to the PWM generating unit 200; within a complete display frame, dividing the gray data into common integer data and remainder coefficient data; at the front section of the display frame, public integer data and remainder coefficient data are sent in a mixed mode, wherein the public integer data are sent to the first memory 100 to be stored, and the remainder coefficient data are sent to the second memory 300 to be stored; displaying the rear section of the frame, and only sending the remainder coefficient data to the second memory 300 for storage; or may be directly transmitted to the PWM generating unit 200 or the remainder coefficient parsing unit 400 through the data bus, and the PWM generating unit 200 generates the PWM for display according to the remainder coefficient data parsed by the remainder coefficient parsing unit 400 and the common integer data stored in the first memory 100. In the embodiment, the second memory 300 is additionally provided for storing remainder coefficient data, and the first memory 100 is used for storing common integer data, that is, the common integer data and the remainder coefficient data are separately stored, so that compared with the case of only the first memory 100, the embodiment can further reduce the storage space and size of the first memory 100, but needs to additionally provide the second memory 300, which slightly increases the cost, but still has a greater technical progress compared with the conventional technology. Since the common integer data and the remainder coefficient data are stored separately, when the data packets a and B are sent in a mixed manner, only the data packet a and the data packet B can be sent separately in a mixed manner, that is, the data packet a only has the common integer, the data packet B only has the remainder coefficient data, and the sending manner of the data packet a and the data packet B is the same as that of the previous embodiment. That is, the data packet a (common integer data) is mainly transmitted in the front of the display frame, and 1 or 2 data packets B may be transmitted, and the transmission order may be the data packet a or the data packet B. And the front display frame segment and the rear display frame segment are completely sent by common integers to serve as distinguishing nodes. Optionally, the remainder coefficient data sent in the front segment of the display frame is the highest bit or the next highest bit of the remainder coefficient data, or the highest bit + the next highest bit. Optionally, the remainder coefficient parsing unit 400 and the PWM generating unit 200 are packaged together as a PWM generating device; or the PWM generating unit 200 is packaged as a PWM generating device, and the remainder coefficient analyzing unit 400 is electrically connected to the PWM generating device.

Optionally, in a gray scale data display driving module, the second memory 300 is used for storing the remainder coefficient number, and it can be known from the above embodiment that the remainder coefficient data can only send 1bit at least, and for a 16-channel chip, only 16 bits of storage space is needed, so that the storage capacity of the second memory 300 is smaller than that of the first memory 100, and even far smaller than that of the first memory 100.

Alternatively, referring to fig. 19, in a gray data display driving module, the first memory 100 is composed of a memory 1-a and a memory 1-B, and the memory 1-a and the memory 1-B alternately transmit and receive data using a ping-pong structure. The problem of picture tearing can be completely solved by adopting the ping-pong structure to alternately receive and transmit data, and the defect is that the cost is higher compared with the structure of a single memory, but the capacities of the memories 1-A and 1-B are smaller in the scheme compared with the traditional mode, namely the technical progress with lower cost is still achieved compared with the prior art. Under this structure, in addition to displaying the display frames in time sequence 1 and time sequence 2, another display mode is provided in the present embodiment to completely solve the problem of screen tearing. In all the PWMs in a complete display frame, the last M groups of the PWMs are generated by the remainder coefficient data stored in the first memory 100, and the transceiving states of the memories 1-a and 1-B are switched in the time for displaying the M groups, so that the mixed transmission of the common integer data and the remainder coefficient data which need to be stored in the next display frame is completed, that is, the saved data bus transmission time is used for transmitting the gray data of the next display frame in advance, so as to avoid occupying the display time of the next display frame. For example, in the above embodiment of 13 bits, if the common integer data and the remainder coefficient data are sent in a mixture of the time sequence 1, 15 PWMs are required to be completely sent, that is, M is 15, that is, 15 PWMs are reserved in the previous frame to perform a mixture sending of the common integer data and the remainder coefficient data of the next display frame; if the public integer data and the remainder coefficient data are mixed and transmitted according to the time sequence 2, M is 8;

or, when the current display frame uses the stored remainder coefficient data for display, the transmission of the common integer data and the remainder coefficient data which need to be stored in the next display frame is completed. Or common integer data or remainder coefficient data required to be stored in the next display frame can be transmitted when the stored remainder coefficients are used for displaying in sequence 1 and sequence 2. In particular, memory 1-a stores the common integer data and remainder coefficient data of the previous display frame, which, when displayed, using the data stored in memory 1-a for display, when using the stored remainder coefficient data, the data bus is idle, it may be used to transmit the common integer and remainder coefficient data that needs to be stored for the next display frame, into memory 1-B, the time for the data bus to transmit the remainder coefficient data can be reduced by more than half, so that the public integer data and the remainder coefficient data which need to be stored in the next display frame are completely transmitted in enough time, namely the public integer data and the remainder coefficient data which are transmitted in a mixed mode in the front section of the display frame, the controller is used for transmitting the data which need to be stored in the next display frame by controlling the data bus with saved time, and the problem of picture tearing can be completely solved.

In another aspect, the present embodiment also provides a gray data transmission method, including:

under control of the controller:

or;

Referring to fig. 16, a schematic diagram of a gray data transmission system is shown, where a plurality of chips are sequentially connected in series (the chip is a gray data display driving module in this embodiment), data transmission is controlled by a controller, and data transmission is completed by connecting the controller and the chips through a data bus, where the overall system framework is completely consistent with that of a conventional chip data transmission system. The difference lies in the processing flow of the controller to the data, that is, the gray data transmission method provided in this embodiment.

The gray scale data is divided into common integer data and remainder coefficient data by the controller in the same manner as in the above embodiment, that is, the gray scale data is divided into high-order data and low-order data, for example, 13-bit gray scale data is divided into 7-bit common integer data and 6-bit remainder coefficient data, and in addition, the gray scale data can be divided into 8-bit common integer data and 5-bit remainder coefficient data, and generally, the remainder coefficient data is preferably not more than 7 bits. For another example, in 16-bit gray scale data, 10-bit common integer data and 6-bit remainder coefficient data can be decomposed, which is also a decomposition method commonly used in the art and will not be described herein, but those skilled in the art should know that all the common integer data and remainder coefficient data decomposition methods known in the art can be used in the present scheme.

After the gray data decomposition is completed, the controller controls the sending sequence of the data packet a and the data packet B, and inevitably, the data packet a and the data packet B also comprise a compression and decompression process at the sending end and the receiving end.

Optionally, in the gray scale data transmission method, the controller combines the common integer data and the partial remainder coefficient data into a data packet a, and the remaining remainder coefficient data is used as a data packet B. The rest of remainder coefficient data in the application as the data packet B does not mean that the rest of remainder coefficient data is compressed in one data packet B, but one data packet B contains 1bit or several bits of remainder coefficient data of each channel of the chip, that is, a plurality of data packets B. The partial remainder coefficient data in the data packet a generally refers to the most significant bit or the second most significant bit, or the most significant bit + the second most significant bit of the remainder data. For example, if 1111111001110111 is defined for a 16-bit gray scale data, the common integer data is 9 bits, and the remainder coefficient data is 7 bits, then the common integer data is R [15,7] ═ 111111100, and the remainder coefficient data is R [6,0] ═ 1110111, i.e., R [6] ═ 1, R [5] ═ 1, R [4] ═ 1, R [3] ═ 0, R [2] ═ 1, R [1] ═ 1, and R [0] ═ 1, where R [6] is displayed in group 64, R [5] is displayed in group 32, R [4] is displayed in group 16, R [3] is displayed in group 8, R [2] is displayed in group 4, R [1] is displayed in group 2, and R [0] is displayed in group 1. What number of groups to display means that the data needs to be transmitted through the data bus, and the partial remainder coefficient data is stored in the application to reduce the time of occupying the data bus. That is, 63 packets B are required in the aggregate, of which 32 packets B have data R5, 16 packets B have data R4, and so on.

Obviously, the higher the number of bits of the remainder coefficient data to be stored, the more the reduced data bus occupation time is, and in this embodiment, if R6 is stored, the half time of the data bus can be reduced, so that half stores the most significant bit or the second most significant bit of the remainder coefficient data when storing. Or, storing the most significant bit + the next highest bit at the same time, and obviously requiring a larger storage space for storing the most significant bit + the next highest bit compared with storing only one bit (1bit) remainder coefficient data, therefore, in practical application, the 1bit remainder coefficient data is stored as the best scheme, the required accumulated storage space is equal to m × 1bit1, where m is the number of channels of the chip, the principle is as shown in fig. 17, where one data packet B includes remainder high bit data of a plurality of points (i.e., channels), and similarly, one data packet a also includes common integer data of 1 to 3 points. But does not exclude the case of storing 2-bit or 3-bit remainder coefficient data. That is, when only R6 is stored, the R5-R0 must be transmitted 63 times in total, which means that there are 63 packets B and 63 packets B must be transmitted. Further, when the data packet a and the data packet B are transmitted, the data packet a is transmitted in a cycle by displaying the front section of the frame, and the principle can be referred to as fig. 4. The data packet B is sent at the rear section of the display frame; since it is necessary to include the remainder coefficient data in all the displayed PWMs, the remainder coefficient data in the M PWMs at the front stage of the display frame is the stored remainder coefficient data, and this case is defined as timing 2, the principle of which can be seen in fig. 14.

In another embodiment, a data packet a and a data packet B are sent in a mixed manner in the front section of the display frame, and a data packet B is sent in the rear section of the display frame, and the data packet B is not stored and therefore is to be displayed after being sent, which also includes two cases, where the data packet a and the data packet B are sent alternately, that is, one data packet a and one data packet B are sent, and the stored remainder coefficient data is used at intervals in the displayed PWM, and this case is defined as a time sequence 1, and the principle thereof can be shown in fig. 13. In addition to the alternate transmission of packets a and B, packets B may be transmitted randomly or out of order, which may be defined as timing sequence 3, in which case which sets of PWMs use the stored residue coefficient data randomly, and in practice this case is used less, the principle of which may be seen with reference to fig. 6. Optionally, the data packet a or the data packet B at the front section of the display frame is sent to the first memory 100 for storage; in the latter stage of the display frame, the data packet B is not stored and is directly transmitted through the data bus, or the data packet B is transmitted to the first memory 100 for storage.

Optionally, in the method for transmitting gray scale data, the first memory 100 is connected to the PWM generating unit 200, and further includes a residue coefficient analyzing unit 400 connected to the first memory 100, wherein an output end of the residue coefficient analyzing unit 400 is connected to the PWM generating unit 200; the PWM generating unit 200 generates 1 set of PWM according to the common integer data stored in the first memory 100 and the remainder coefficient data parsed by the remainder coefficient parsing unit 400; in a complete display frame, N groups of PWM are generated together, and N is the weight of common integer data.

Optionally, in a complete display frame, the display timing of the PWM is:

sequence 1: the remainder coefficient data in the odd number groups of PWM are determined by the stored remainder coefficient data, and the remainder coefficient data in the even number groups of PWM are transmitted by a data bus; alternatively, the remainder coefficient data in the even group of PWMs is determined by the stored remainder coefficient data, and the remainder coefficient data in the odd group of PWMs is transmitted by the data bus, and the principle can be described with reference to fig. 13.

And (2) time sequence: the remainder coefficient data in the first M groups of PWMs of the display frame is determined by the stored remainder coefficient data, the remainder coefficient data in the remaining PWMs is transmitted by the data bus, and the common integers are all sent out within the M groups of PWM timing sequences, the principle of which can be seen in fig. 14.

Optionally, a gray data transmission method is used, where display frames are switched between time sequence 1 and time sequence 2 according to a gray threshold K, time sequence 2 is used when a picture gray is greater than or equal to threshold K, and time sequence 1 is used when the picture gray is smaller than threshold K. The switching between the time sequence 1 and the time sequence 2 is determined by the controller/logic processing module 500, and the controller/logic processing module 500 is connected to the remainder coefficient parsing unit 400, and is configured to control whether the remainder coefficient parsing unit 400 parses the stored remainder coefficient data or receives the remainder coefficient data transmitted by the data bus.

Optionally, a gray data transmission method is different from the foregoing embodiment, in this embodiment, common integer data is used to form a data packet a, remainder coefficient data is used as a data packet B, the data packet a and the data packet B are sent in a mixed manner in a front segment of a display frame, the data packet B is sent in a rear segment of the display frame, the data packet B may be sent only 1 time or multiple times in the front segment of the display frame, and a principle of the method may be as shown in fig. 6. Optionally, the data packet a at the front section of the display frame is sent to the first memory 100 for storage, and the data packet B is sent to the second memory 300 for storage; in the latter stage of the display frame, the data packet B is not stored and is directly transmitted through the data bus, or the data packet B is transmitted to the second memory 300 for storage. The first memory 100 is connected with the PWM generating unit 200, the second memory 300 is connected with the remainder coefficient analyzing unit 400, and the remainder coefficient analyzing unit 400 is connected with the PWM generating unit 200; the remainder coefficient parsing unit 400 is configured to parse remainder coefficient data received by the second memory 300, and the PWM generating unit 200 generates 1 set of PWM according to the common integer data stored in the first memory 100 and the remainder coefficient data parsed by the remainder coefficient parsing unit 400; in a complete display frame period, N groups of PWM are generated in total, wherein N is the weight of common integer data.

Optionally, in the gray scale data transmission method, the front segment of the display frame and the rear segment of the display frame are all sent as the differentiation nodes in common integers.

Optionally, a gray scale data transmission method is adopted, when several pieces of remainder coefficient data are not scattered, the remainder coefficient data of the transmission loss need to be supplemented, and the remainder weight W_R＝2^j，W_RWhen the value is more than 1, the controller supplements and transmits remainder low-order data R [0: j-1%]Namely, the 0 th to (j-1) th bits of the remainder data R are transmitted in complement, and the remainder low-order data R [0: j-1 ] is transmitted in complement]The j times of sending are finished, for example, in 4 non-scattering times, j is 2, that is, supplement 2 additional sending times, which are respectively used for sending the 0 th bit and the 1 st bit, in other words, which lower data are lost in several non-scattering processes and then supplement the lower data for sending, wherein all the lower data can be sent out 1 time, that is, 1 time, the lost lower data are all sent out, or 1bit can be sent out each time, that is, j times of sending are required to be finished, and simultaneously, an indefinite number of bits can be sent out once until all lost remainder data are sent out. As can be seen from the above analysis, if the remainder data of lower bits is not transmitted in a complementary manner, i.e., a few remainder coefficients are less, this results in D "being less than D'. And adding P groups or P-1 groups of PWM for supplementary display, analyzing that 1 group of PWM has no remainder coefficient data as above, and displaying a remainder coefficient data in a reorganization mode, namely only needing to supplement and display the P-1 group. Each set of displayed gray scale data is

Wherein, P ═ j, T_jFor each bit of the lost bit width, the value is the number of the j-1bitA value; v_jIs T_jCorresponding weight of 2^j. For example, j is 1, i.e., 2 are not scattered, and the 0 th bit, i.e., R [0], is displayed in addition]When j is 2, 4 are not scattered, and the 1 st bit and 0 th bit are displayed in addition, that is, R1]And R < 0 >]. If j is 2 in 4 non-scattering data, the data displayed is T₁×1、T₂X 2. Referring to fig. 20 and 21, the supplementary data is shown, i.e., T₁、T₂、T₂Three remainder coefficients are displayed schematically, and T is sent by occupying a data bus when residue coefficient data is not transmitted₁、T₂、T₂And displaying. Corresponding 8 non-scattering supplementary displays are T₁×1、T₂×2、T₃X 4, i.e., the accumulated complement of 7 remainder coefficient data. When the whole gray data value is large, the lost remainder low-order data is not compensated, and when the whole gray data value is small, the lost remainder low-order data is compensated.

The foregoing is illustrative of the preferred embodiments of this application, and it is to be understood that this application is not limited to the forms disclosed herein, but is not intended to be exhaustive of other embodiments and that various other combinations, modifications, and environments may be used, and changes may be made within the scope of the inventive concept as described herein, by the above teachings or the skill or knowledge of the relevant art. And that modifications and variations may be effected by those skilled in the art without departing from the spirit and scope of the application, which is to be protected by the claims appended hereto.

Claims

1. A gradation data transmission controller characterized by:

displaying a front section of a frame, and mixedly sending public integer data and remainder coefficient data by a controller;

and the requirements are met,

wherein D' represents the gray value actually displayed for a certain frame, and Q represents a common integerData, R_iAnd representing remainder coefficient data, wherein N is the number of times of circular display of the common integer data in the display frame, N is the number of times of display of the remainder coefficient data in the display frame, and N is less than or equal to N.

2. A gradation data transmission controller as claimed in claim 2, wherein the common integer data and remainder coefficient data are calculated by:

common integer data

Solving an integral function;

remainder data

A remainder function, wherein D represents the gray value of a certain frame, and the remainder data R is divided into a plurality of remainder coefficient data R_i。

3. A gradation data transmission controller according to claim 1 or 2, wherein common integer data and remainder coefficient data mixedly transmitted at a front stage of the display frame are stored in the driver chip, and remainder coefficient data transmitted at a rear stage of the display frame are not stored;

and the front display frame segment and the rear display frame segment are completely sent by common integers to be used as distinguishing nodes.

4. A gradation data transmission controller according to any one of claims 1 to 3, wherein said mixedly transmitting common integer data and remainder coefficient data comprises:

or;

5. The gray data transmission controller according to claim 4, wherein the partial remainder coefficient data is remainder high data, which is remainder coefficient data that can be displayed in a plurality of sets of PWM;

the remainder high data is the ibit of the remainder data, or the [ (i-b): i ] bit; the remainder data of other bits is used as remainder coefficient data, wherein b is more than or equal to 1;

6. A gray data transmission controller according to any one of claims 1 to 5, wherein, in all the PWMs in a complete display frame, the residue coefficient data in the PWMs of several groups are generated by the residue coefficient data stored in the driving chip, and the residue coefficient data in the PWMs of the other groups are transmitted by the bus;

in one display frame period, the display timing of the PWM is:

or the like, or, alternatively,

7. A gray scale data transmission controller as claimed in claim 6, wherein between each display frame, under the control of the controller, time sequence 1 and time sequence 2 are dynamically switched;

and the time sequence 1 and the time sequence 2 are dynamically switched according to the gray level of the picture, the time sequence 2 is adopted when the gray level of the picture is greater than or equal to a gray threshold value K, and the time sequence 1 is adopted when the gray level of the picture is less than the gray threshold value K.

8. A gray scale data transmission controller as claimed in claim 7, wherein said gray scale threshold K represents:

the gray value of one complete display frame;

9. A gray scale data transmission controller as claimed in any one of claims 1 to 8, wherein the controller or the driver chip stores a common integer weight W_QSum remainder weight W_R；

The finally displayed gray value is changed from D' to D ", and there are:

wherein, W_Q×Q'＝Q。

10. A gray scale data transmission controller as claimed in claim 9, wherein said remainder weight W_R＝2^j，W_RWhen the value is more than 1, the controller supplements and transmits remainder low-order data R [0: j-1%]I.e., bits 0 to (j-1) of the transmission remainder data R.

11. A gray data transmission system, comprising a controller, a data bus and at least one driving chip, wherein the controller is connected with the driving chip through the data bus, the driving chips are cascaded through the data bus, and the controller is the gray data transmission controller as claimed in any one of claims 1 to 11.

12. A method for transmitting gray scale data, the method comprising:

under control of the controller:

or;

13. The method according to claim 12, wherein the remainder coefficient data included in the data packet a or the data packet B transmitted at the previous segment of the display frame is remainder high-order data, which is remainder coefficient data that can be displayed in multiple groups of PWM;

when the data packet A consists of public integer data and partial remainder coefficient data, the remainder coefficient data in the data packet A is 1bit or 2 bits or 3 bits;

14. A gray scale data transmission method as claimed in claim 12 or 13, wherein the data packet a or B is sent to the driver chip for storage at the front segment of the display frame;

15. A method for transmitting gray scale data according to any one of claims 12-14, wherein the display timing of PWM is:

or;

16. A method for transmitting gradation data according to claim 15, wherein the display frames are switched between the time sequence 1 and the time sequence 2 according to the gradation threshold K, and the time sequence 2 is adopted when the gradation of the picture is equal to or greater than the threshold K, and the time sequence 1 is adopted when the gradation is less than the threshold K.

17. A method for transmitting gradation data according to any one of claims 12 to 16, wherein the controller or the driver chip stores a common integer weight W_QSum remainder weight W_R；

The finally displayed gray value is changed from D' to D ", and there are:

wherein, W_Q×Q'＝Q；

The remainder weight W_R＝2^j，W_RWhen the value is more than 1, the controller supplements and transmits remainder low-order data R [0: j-1%]I.e., bits 0 to (j-1) of the transmission remainder data R.