CN112887236B

CN112887236B - Synchronization and equalization device and method for high-speed burst signal

Info

Publication number: CN112887236B
Application number: CN202110036106.7A
Authority: CN
Inventors: 胡荣; 王志军
Original assignee: Fiberhome Telecommunication Technologies Co Ltd
Current assignee: Fiberhome Telecommunication Technologies Co Ltd
Priority date: 2021-01-12
Filing date: 2021-01-12
Publication date: 2021-09-21
Anticipated expiration: 2041-01-12
Also published as: CN112887236A

Abstract

The invention discloses a device and a method for synchronizing and equalizing high-speed burst signals, and relates to the technical field of optical access. The apparatus includes an equalizer, a time synchronizer, and an equalization controller. The equalizer receives the uplink burst signal and transmits the calculated equalization output to the time synchronizer in a blind equalization mode or a training equalization mode under the control of the equalization controller. The PSBu data pattern of the uplink burst signal comprises two parts, namely A + and A-which are in negative correlation characteristics. And the time synchronizer finds the uplink burst signal based on the PSBu data mode, carries out boundary identification and feeds back the uplink burst signal to the equalizer controller. And the equalization controller controls the equalizer to switch between a blind equalization mode and a training equalization mode according to the feedback and a preset equalization control state machine. The invention effectively combines the advantages of two equilibrium modes, not only can efficiently equalize and effectively ensure the effective load bandwidth of the system, but also can improve the quality of synchronization and training and meet the requirement of practical application.

Description

Synchronization and equalization device and method for high-speed burst signal

Technical Field

The invention relates to the technical field of optical access, in particular to a device and a method for synchronizing and equalizing high-speed burst signals.

Background

A TDM-PON (Time Division Multiplexing-Passive Optical Network) is a Passive Optical Network that uses Time Division Multiplexing as an access technology. In a TDM-PON system, an upstream burst data frame structure generally includes two parts, namely, a PSBu (upstream Physical Synchronization Block) and a Payload (data Payload), as shown in fig. 1. The PSBu is used for discovering the uplink burst signal and synchronizing. After synchronization is achieved, the system can accurately position Payload and extract frame data.

But as the transmission rate increases, for example: the code rate is increased to 50GBaud and above, and the synchronization of the data frames of the uplink burst signals in the TDM-PON system becomes more and more difficult, mainly reflected in that: 1) affected by the bandwidth of the optical/electrical device, 2) affected by the dispersion of the fiber. Inter Symbol Interference (ISI) of PSBu of the uplink high-speed burst signal is a serious problem, and it is difficult to accurately locate the Payload start position, resulting in data frame loss. In addition, the Payload portion signal is also affected by inter-symbol crosstalk, which results in a large number of symbol misjudgments.

To reduce the effect of inter-symbol crosstalk, an adaptive equalizer is a feasible implementation. There are two main approaches for adaptive updating of the equalizer, which are: constant Modulus Algorithm (CMA), and Training Sequence (Training Sequence) based adaptive update methods. The main differences between the above two methods are: 1) the constant modulus algorithm is an adaptive blind equalization method, and has the advantage that a training sequence is not needed, so that the net throughput of the system is higher. However, the constant modulus algorithm has the disadvantage of low equalization efficiency, mainly due to slow adaptive convergence. 2) The adaptive updating method based on the training sequence has the advantages that the adaptive equalization convergence speed is high, and the method is suitable for uplink burst signals with short duration. The disadvantage of this type of method is that the training sequence needs to be sent, so the training sequence occupies the payload bandwidth of the system, resulting in a lower net throughput of the system. In addition, the adaptive update method based on the training sequence needs to accurately locate the position of the training sequence, and therefore, the adaptive update method must be performed after the uplink data frame synchronization is completed.

The PSBu of the uplink burst signal is known to the receiver and thus is essentially a special form of training sequence. If the adaptive updating method based on the training sequence is adopted, the key problem lies in positioning the relative position of the PSBu in the burst signal. Therefore, how to overcome the contradiction between the equalizer training and the time synchronization, so that the equalizer can not only balance efficiently, but also ensure the payload bandwidth of the system effectively, and the quality of synchronization and training is improved is a problem to be solved by those skilled in the art.

Disclosure of Invention

The invention aims to overcome the defects of the background technology, and provides a device and a method for synchronizing and equalizing high-speed burst signals, so that an equalizer can be switched between blind equalization and training equalization, the advantages of two equalization modes are effectively combined, and not only can the effective equalization be realized, but also the effective load bandwidth of a system can be effectively ensured; meanwhile, the quality of synchronization and training can be improved, and the actual application requirements are met.

In order to achieve the above object, the present invention provides a synchronization and equalization apparatus for high-speed burst signals, comprising an equalizer, a time synchronizer and an equalization controller;

the equalizer is configured to: receiving an uplink burst signal, and transmitting the calculated balance output to a time synchronizer in a blind balance mode or a training balance mode under the control of a balance controller; the PSBu data pattern of the uplink burst signal comprises two parts, namely A + and A-, wherein the A + and the A-are in negative correlation characteristics;

the time synchronizer is configured to: outputting the output of the equalizer as a self output signal; meanwhile, an uplink burst signal is found based on the PSBu data mode, PSBu data mode boundary identification is carried out, and a found result and an identification result are fed back to an equalizer controller;

the equalization controller is configured to: and controlling the equalizer to switch between a blind equalization mode and a training equalization mode according to the feedback of the time synchronizer and a preset equalization control state machine.

On the basis of the technical scheme, the equalizer is an N-tap forward equalizer; the equalizer calculates an equalized output OUT at the current time according to N tap coefficients W [1,2, …, N ] and input signal samples IN [1,2, …, N ] corresponding to N taps at the current time, and the operation formula is as follows:

OUT＝P(W,IN)；

in the formula, an operator P (·) represents a dot product operation of two vector signals;

the equalizer updates the tap coefficient W by calculating the error E, and the update formula is:

W’＝W+u*E*IN；

in the formula, u is a constant and represents an adaptive update coefficient; w' denotes the updated N tap coefficients.

On the basis of the above technical solution, when the equalizer is in the blind equalization mode, the calculation formula of the error E is as follows:

E＝1–ABS(OUT)；

in the equation, the operator ABS (.) represents an absolute value operation.

On the basis of the above technical solution, when the equalizer is in a training equalization mode, the calculation formula of the error E is as follows:

E＝Ts–OUT；

in the equation, Ts represents a training sequence sample corresponding to the equalized output OUT signal at the current time.

On the basis of the technical scheme, the time synchronizer performs PSBu data mode boundary identification based on the PSBu data mode and feeds an identification result back to the equalizer controller, and the method specifically comprises the following operations:

detecting the correlation between the locally stored PSBu data pattern and the received PSBu data pattern by performing correlation operation on the locally stored PSBu data pattern and the received PSBu data pattern;

if the peak value or the valley value is output by correlation detection, the time interval between the current peak value/valley value and the previous valley value/peak value is T/2, and the T represents a data mode period, the identification result is that the PSBu data mode boundary identification is successful, and the identification result is fed back to the equalizer controller;

otherwise, the identification result is that the PSBu data mode boundary identification fails, and the identification result is fed back to the equalizer controller.

On the basis of the above technical solution, the equalization control state machine of the equalization controller includes: s1-ready state, S2-blind equalization state, S3-transition state, S4-training equalization state, S5-sync state.

On the basis of the technical scheme, the equalization controller controls the equalizer to switch between a blind equalization mode and a training equalization mode according to a preset equalization control state machine, and the method specifically comprises the following operations:

initially, the equalization control state machine is in an S1 state, and the equalization controller controls the equalizer to be in an initial state; when the time synchronizer feeds back a discovery result of discovering the uplink burst signal, the state of S2 is entered;

after entering the state of S2, controlling the equalizer to be in a blind equalization mode; when the time synchronizer feeds back the identification result of the PSBu data pattern boundary identification success, the state of S3 is entered, otherwise, the state of S2 is continuously kept;

after entering the state of S3, continuously controlling the equalizer to be in a blind equalization mode; meanwhile, initializing a Count value Count, when the time synchronizer feeds back an authentication result that the PSBu data mode boundary authentication is successful, adding 1 to the Count value, if the Count value is smaller than a blind equalization threshold, keeping an S3 state, and entering an S4 state once the Count value is equal to the blind equalization threshold; when the time synchronizer feeds back the authentication result of the PSBu data mode boundary authentication failure, the state of S2 is returned;

after entering the state of S4, controlling the equalizer to switch to a training equalization mode; meanwhile, initializing the Count, when the time synchronizer feeds back an authentication result that the PSBu data mode boundary authentication is successful, adding 1 to the Count value, if the Count value is smaller than the training equalization threshold value, keeping the state of S4, and entering the state of S5 once the Count value is equal to the training equalization threshold value; when the time synchronizer feeds back the authentication result of the PSBu data mode boundary authentication failure, the state of S3 is returned;

after entering the state of S5, the equalizer is controlled to be in the training equalization mode until PSBu ends, wherein the end of PSBu is bounded by a terminator.

On the basis of the technical scheme, the A + part and the A-part of the PSBu data mode meet the following rules: 1) the peak value/valley value of the correlation detection output is easy to identify, and the correlation values at other moments except the peak value/valley value are obviously distinguished from the peak value/valley value; 2) the A + and A-portions avoid longer consecutive "1" or "-1".

On the basis of the technical scheme, the PSBu data mode is a 32-bit data mode; the A + part of the PSBu data pattern is represented by [1,1, -1,1, -1, -1,1, -1,1,1,1, -1] in a binary mode; the A-portion of the PSBu data pattern is represented in binary as [ -1, -1,1, -1,1,1, -1,1, -1, -1, -1, 1.

On the basis of the technical scheme, the PSBu data mode is a 64-bit data mode; the a + part of the PSBu data pattern is represented in binary as [1, -1,1, -1, -1, -1,1,1, -1,1,1,1, -1, -1,1, -1,1, -1, -1, -1; the a-portion of the PSBu data pattern is represented in binary as [ -1,1, -1,1,1,1, -1, -1,1, -1, -1, -1,1,1, 1).

The invention also provides a high-speed burst signal synchronization and equalization method based on the device, which comprises the following steps:

the equalizer receives an uplink burst signal, a PSBu data mode of the uplink burst signal comprises an A + part and an A-part, and the A + and the A-parts are in negative correlation characteristics; under the control of the equalization controller, the calculated equalization output is transmitted to a time synchronizer in a blind equalization mode or a training equalization mode;

the time synchronizer outputs the output of the equalizer as a self output signal; meanwhile, an uplink burst signal is found based on the PSBu data mode, PSBu data mode boundary identification is carried out, and a found result and an identification result are fed back to an equalizer controller;

and the equalization controller controls the equalizer to switch between a blind equalization mode and a training equalization mode according to the feedback of the time synchronizer and a preset equalization control state machine.

The invention has the beneficial effects that:

(1) in the invention, the equalization controller can control the equalizer to switch between a blind equalization mode and a training equalization mode based on a preset state machine model, so that the equalizer can combine the advantages of the two equalization modes, realize high-efficiency equalization and effectively ensure the effective load bandwidth of the system, thereby improving the net throughput of the system. In addition, the scheme also provides an optimized PSBu data mode and a corresponding time synchronizer. The PSBu data mode consists of two symmetrical data blocks A + and A-, wherein A + and A-are in negative correlation characteristics and have good autocorrelation characteristics, so that a correspondingly designed time synchronizer can effectively confirm the mode boundary based on the PSBu data mode, thereby integrally improving the synchronization and training quality and meeting the actual application requirements.

(2) In the invention, the balance control state machine is optimally designed, so that the equalizer can be controlled to switch between a blind balance mode and a training balance mode, and balance and synchronization are simultaneously carried out in the blind balance mode, thereby improving the utilization rate of PSBu; once the synchronization is successful, the convergence speed and accuracy of the equalizer can be greatly improved by entering a training equalization mode; in the synchronization loss-of-lock state, the system can switch back to the blind equalization state to continuously perform channel equalization and gradually restore synchronization. The above characteristics ensure that the system can rapidly complete the functions of synchronization and signal equalizer parameter initialization under the condition of shorter PSBu.

(3) In the invention, the A + and A-parts of the PSBu data mode are specifically optimized and designed, so that higher balance and peak/valley detection efficiency can be realized.

Drawings

Fig. 1 is a schematic structural diagram of an uplink burst signal data frame;

FIG. 2 is a block diagram of a high-speed burst signal synchronization and equalization apparatus according to an embodiment of the present invention;

FIG. 3 is a diagram illustrating PSBu data pattern boundary identification in an embodiment of the present invention;

FIG. 4 is a diagram of an equalization control state machine in an embodiment of the present invention;

FIG. 5 is a schematic diagram illustrating the periodic correlation of a 32-bit PSBu data pattern according to an embodiment of the present invention;

FIG. 6 is a schematic diagram illustrating the periodic correlation of a 64-bit PSBu data pattern according to an embodiment of the present invention;

FIG. 7 is a flowchart illustrating a method for synchronizing and equalizing a high-speed burst signal according to an embodiment of the present invention.

Detailed Description

Aiming at the problems that in the prior art, a traditional equalizer adopts an adaptive blind equalization method, although the net throughput of a system is higher, the equalization efficiency is lower and the adaptive convergence is slower; and by adopting the adaptive updating method based on the training sequence, although the adaptive equalization convergence speed is high, the effective load bandwidth of the system is occupied, so that the problem of low net throughput of the system is caused. The invention aims to provide a device and a method for synchronizing and equalizing high-speed burst signals, which can ensure that an equalizer can be switched between blind equalization and training equalization, effectively combine the advantages of two equalization modes, and not only can efficiently equalize but also can effectively ensure the effective load bandwidth of a system; meanwhile, the quality of synchronization and training can be improved, and the actual application requirements are met.

The main design concept is as follows: the device for synchronizing and equalizing the high-speed burst signals comprises an equalizer, a time synchronizer and an equalization controller. The equalizer is used for receiving the uplink burst signal and can be switched in a blind equalization mode or a training equalization mode under the control of the equalization controller; the PSBu data pattern of the uplink burst signal is designed to be composed of two parts, namely A + and A-, and the A + and the A-are in negative correlation characteristics. The time synchronizer can find the uplink burst signal based on the designed PSBu data mode, carry out PSBu data mode boundary identification and feed back the found result and the identification result to the equalizer controller. And the equalization controller controls the equalizer to switch between a blind equalization mode and a training equalization mode according to the feedback of the time synchronizer and a preset equalization control state machine.

In the scheme, a mixed-mode equalizer and an equalization controller are provided. The equalization controller can control the equalizer to switch between a blind equalization mode and a training equalization mode based on a preset state machine model, so that the equalizer can combine the advantages of the two equalization modes, realize high-efficiency equalization and effectively ensure the effective load bandwidth of the system, thereby improving the net throughput of the system. In addition, the scheme also provides an optimized PSBu data mode and a corresponding time synchronizer. The PSBu data mode consists of two symmetrical data blocks A + and A-, wherein A + and A-are in negative correlation characteristics and have good autocorrelation characteristics, so that a correspondingly designed time synchronizer can effectively confirm the mode boundary based on the PSBu data mode, thereby integrally improving the synchronization and training quality and meeting the actual application requirements.

In order to make the technical problems, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be described in detail with reference to the accompanying drawings and specific embodiments.

However, it should be noted that: the examples to be described next are only some specific examples, and are not intended to limit the embodiments of the present invention necessarily to the following specific steps, values, conditions, data, orders, and the like. Those skilled in the art can, upon reading this specification, utilize the concepts of the present invention to construct more embodiments than those specifically described herein.

Example one

Referring to fig. 2, the present embodiment provides a synchronization and equalization apparatus for high-speed burst signals, which includes an equalizer, a time synchronizer, and an equalization controller.

Wherein the equalizer is configured to: receiving an uplink burst signal, and transmitting the calculated balance output to a time synchronizer in a blind balance mode or a training balance mode under the control of a balance controller; the PSBu data pattern of the uplink burst signal comprises two parts, namely A + and A-, and the A + and the A-are in a negative correlation characteristic. For example, taking a 32-bit PSBu data pattern as an example, if the a + portion is represented by binary: [1,1, -1,1, -1, -1,1, -1,1,1,1, -1,1,1,1, -1], then the A-moiety is represented as binary: [ -1, -1,1, -1,1,1, -1,1, -1, -1, -1,1, -1, -1, -1,1]. It can be understood that the PSBu data pattern designed above has a better autocorrelation characteristic, which facilitates the time synchronizer to be able to effectively identify (detect) the pattern boundary, and the specific identification (detection) process is detailed later, and is not described herein again.

Specifically, as shown in fig. 2, in this embodiment, the input signal of the equalizer is an uplink burst signal, and the output of the equalizer is connected to the time synchronizer; the equalizer is a mixed-mode equalizer and has two working modes: the blind equalization mode and the training equalization mode can be switched according to a control signal of the equalization controller. The method has the advantages that the higher net throughput of the system can be obtained in the blind equalization mode, the adaptive equalization convergence can be rapidly realized in the training equalization mode, and the effective load bandwidth of the system can be effectively ensured by combining the advantages of the two equalization modes. And the device is used as a receiver to negotiate the data mode of the PSBu frame of the uplink burst signal with the transmitter in advance, so that the PSBu data mode of the uplink burst signal consists of two parts, namely A + and A-, and the A + and the A-are in negative correlation characteristics. Because the PSBu data pattern is composed of symmetrical data blocks and has a good Peak detection characteristic (the output of a Peak Detector PD-Peak Detector has obvious periodicity and periodically changes between a Peak and a trough), the designed PSBu data pattern has a good autocorrelation characteristic, and a time synchronizer can effectively confirm (or detect) the pattern boundary.

A time synchronizer to: outputting the output of the equalizer as a self output signal; and meanwhile, discovering the uplink burst signal based on the PSBu data mode, performing PSBu data mode boundary identification, and feeding back a discovery result and an identification result to the equalizer controller. Specifically, as shown in fig. 2, in the present embodiment, the input of the time synchronizer is the equalization output of the equalizer, and the output of the time synchronizer includes: an output signal and a feedback signal. The output signal of the time synchronizer is equal to the output signal of the equalizer, and the feedback signal of the time synchronizer comprises a discovery result signal for determining whether the uplink burst signal is discovered or not and a determination result signal for determining whether the PSBu data pattern boundary is successfully determined or not.

An equalization controller to: and controlling the equalizer to switch between a blind equalization mode and a training equalization mode according to the feedback of the time synchronizer and a preset equalization control state machine.

As can be seen from the above, the present embodiment provides a mixed-mode equalizer and an equalization controller. The equalization controller can control the equalizer to switch between a blind equalization mode and a training equalization mode based on a preset state machine model, so that the equalizer can combine the advantages of the two equalization modes, realize high-efficiency equalization and effectively ensure the effective load bandwidth of the system, thereby improving the net throughput of the system. In addition, the embodiment also provides an optimized PSBu data pattern and a corresponding time synchronizer. The PSBu data mode consists of two symmetrical data blocks A + and A-, wherein A + and A-are in negative correlation characteristics and have good autocorrelation characteristics, so that a correspondingly designed time synchronizer can effectively confirm the mode boundary based on the PSBu data mode, thereby integrally improving the synchronization and training quality and meeting the actual application requirements.

Further, as an optional implementation manner, the equalizer is an N-tap forward equalizer, and the equalizer calculates an equalized output OUT at the current time according to N tap coefficients W [1,2, …, N ] of the equalizer and input signal samples IN [1,2, …, N ] corresponding to N taps at the current time, where the operation formula is:

OUT＝P(W,IN)；

in the equation, the operator P (.) represents a dot product operation of two vector signals, that is: the sum of the products of each corresponding element in the vector signal.

On the basis, the equalizer updates the tap coefficient by calculating the error E, and the updating formula is as follows:

W’＝W+u*E*IN；

When the equalizer is in the blind equalization mode, the calculation formula of the error E is as follows: 1-abs (out); in the equation, the operator ABS (.) represents an absolute value operation. It will be appreciated that IN the blind equalization mode, since the input signal samples IN have been normalized, the error E can be determined by the constant modulus "1" and the absolute value of the equalized output OUT signal. When the equalizer is in the training equalization mode, the calculation formula of the error E is as follows: e is Ts-OUT; in the equation, Ts represents a training sequence Sample (Sample Value) corresponding to the equalized output OUT signal at the current time. It can be understood that, under the control of the equalization control state machine of the equalization controller, the equalizer of the embodiment first enters the blind equalization mode, and completes synchronization in the blind equalization mode. After synchronization, when entering a training equalization mode, the output OUT signal of the equalizer can correspond to the Ts sample value of the training sequence, thereby realizing training equalization. Therefore, the error E can be calculated by Ts and OUT.

Further, as a preferred embodiment, the time synchronizer performs PSBu data pattern boundary identification based on the PSBu data pattern, and feeds back an identification result to the equalizer controller, specifically including the following operations:

the method comprises the steps of carrying out correlation operation on a locally stored PSBu data mode (when the device serves as a receiver and negotiates with a transmitter in advance about the data mode of a PSBu frame of an uplink burst signal, the PSBu data mode is locally stored) and the received PSBu data mode to detect the correlation between the locally stored PSBu data mode and the received PSBu data mode;

if the peak value or the valley value is output by the correlation detection, and the time interval between the current peak value/valley value and the previous valley value/peak value is T/2(T represents a data mode period), the identification result is that the PSBu data mode boundary identification is successful, and the identification result is fed back to the equalizer controller; otherwise, the identification result is that the PSBu data mode boundary identification fails, and the identification result is fed back to the equalizer controller.

Specifically, as shown in fig. 3, since the PSBu data pattern is composed of two symmetric data blocks a + and a-, and a + and a-are negative correlation characteristics and have good autocorrelation characteristics, when the received PSBu data pattern is completely aligned with the locally stored PSBu data pattern within one data pattern period T, the correlation between the received PSBu data pattern and the locally stored PSBu data pattern is the highest, and the correlation detection output peak value is obtained; when the received PSBu data pattern is offset from the locally stored PSBu data pattern by T/2, the correlation between the received PSBu data pattern and the locally stored PSBu data pattern is the lowest, and a valley value is output through correlation detection. It can be seen that when the time synchronizer performs correlation operation to detect the correlation between the two signals, the correlation detection output signal changes periodically, wherein the peak occurs at the time when the data patterns are completely aligned, and the valley occurs at the time when the data patterns are relatively shifted by T/2. According to the above features, the boundary of the data pattern can be effectively identified, i.e. the PSBu data pattern boundary identification is successful when the correlation detection output satisfies the following two conditions: 1) the occurrence of peaks or valleys; 2) the time interval between the current peak/valley and the previous valley/peak is T/2.

Further, as a preferred embodiment, the equalization control state machine of the equalization controller includes: s1-ready state, S2-blind equalization state, S3-transition state, S4-training equalization state, S5-sync state. Referring to fig. 4, the equalization controller controls the equalizer to switch between the blind equalization mode and the training equalization mode according to a preset equalization control state machine, and specifically includes the following operations:

1) initially, an equalization control state machine of the equalization controller is in an S1 state, and controls an equalizer to be in an initial state, and at this time, the time synchronizer performs related detection based on a PSBu data mode to find an uplink burst signal; when the time synchronizer feeds back a discovery result of discovering an uplink burst signal, the equalization control state machine enters the state of S2.

2) After entering the state of S2, the equalization controller controls the equalizer to be in a blind equalization mode, and at this time, the time synchronizer performs correlation detection based on the PSBu data mode to identify PSBu data mode boundaries; when the time synchronizer feeds back the identification result of the PSBu data pattern boundary identification success, the equilibrium control state machine enters the state of S3, otherwise, the equilibrium control state machine is continuously in the state of S2.

3) After entering the state of S3, the equalization controller continues to control the equalizer to be in the blind equalization mode, and at this time, the time synchronizer continues to perform correlation detection based on the PSBu data mode, so as to identify the PSBu data mode boundary; meanwhile, the balance controller initializes a Count value Count, when the time synchronizer feeds back an identification result that the PSBu data mode boundary identification is successful, the Count value is added with 1, if the Count value is smaller than a blind balance threshold value, the state of S3 is kept, and once the Count value is equal to the blind balance threshold value, the state of S4 is entered; when the time synchronizer feeds back the authentication result that the PSBu data pattern boundary authentication fails, the state of S2 is returned. In practical operation, the blind equalization threshold may preferably be 3, but the specific selection is determined according to practical situations, and the embodiment is not particularly limited.

4) After entering the state of S4, the equalization controller controls the equalizer to switch to the training equalization mode, and at the moment, the time synchronizer continues to perform related detection based on the PSBu data mode and is used for identifying the PSBu data mode boundary; meanwhile, the balance controller initializes the Count, when the time synchronizer feeds back an authentication result that the PSBu data mode boundary authentication is successful, the Count value is added with 1, if the Count value is smaller than the training balance threshold value, the state of S4 is kept, and once the Count value is equal to the training balance threshold value, the state of S5 is entered; when the time synchronizer feeds back the authentication result that the PSBu data pattern boundary authentication fails, the state of S3 is returned. Similarly, in practical operation, the training equalization threshold may preferably be 3, but the specific choice also needs to be determined according to practical situations, and this embodiment is not particularly limited.

5) After entering the state S5, the equalization controller controls the equalizer to be in the training equalization mode until PSBu ends, wherein the end of PSBu is bounded by a terminator.

As can be seen from the above operation, in the preferred embodiment, the equalization control state machine will start from the S1 ready state, enter the S2 blind equalization state, then enter the S4 training equalization state from the S3 transition state, and finally go through the S5 synchronization state until the synchronization is finished. Based on the optimally designed state machine model, the equalization controller can control the equalizer to switch between a blind equalization mode and a training equalization mode, and equalization and synchronization are simultaneously carried out in the blind equalization mode, so that the utilization rate of PSBu is improved; once the synchronization is successful, the convergence speed and accuracy of the equalizer can be greatly improved by entering a training equalization mode; in the synchronization loss-of-lock state, the system can switch back to the blind equalization state to continuously perform channel equalization and gradually restore synchronization. The above characteristics ensure that the system can rapidly complete the functions of synchronization and signal equalizer parameter initialization under the condition of shorter PSBu.

In addition, it will be appreciated that the specific content design of the PSBu data pattern determines the efficiency of boundary qualification. Therefore, on the basis of the first embodiment, in order to achieve higher equalization and peak/valley detection efficiency, the present solution performs optimized design selection on the a + and a-parts of the PSBu data pattern. That is, the PSBu data pattern achieves higher equalization and peak/valley detection efficiency when its a + and a-portions satisfy the following rules: 1) the peak value/valley value of the correlation detection output is easy to identify, and the correlation values at other moments except the peak value/valley value are obviously distinguished from the peak value/valley value; 2) longer consecutive "1" or "-1" should be avoided. Usually, 3 to 5 or more continuous pieces are considered to be "long", but 3 to 5 or more continuous pieces are not usable at all, and may be usable in practice, and the effect is not optimal. For example, taking a 32-bit PSBu data pattern as an example, the a + portion of the PSBu data pattern may be represented by binary: [1,1, -1,1,1, -1,1,1,1,1, -1,1,1, -1, -1], then the A-moiety may be represented in binary form as: [ -1, -1,1, -1, -1,1, -1, -1, -1, -1,1, -1, -1,1,1,1]. Taking a 64-bit PSBu data pattern as an example, the a + portion of the PSBu data pattern may be represented by binary: [ -1, -1, -1, -1, -1,1,1, -1, -1,1, -1,1,1, -1,1, -1, -1, -1, -1, -1,1, -1,1,1,1, -1, -1, -1], then the a-moiety can be represented in binary form as: [1,1,1,1,1, -1, -1,1,1, -1,1, -1, -1,1, -1,1,1,1,1, -1,1, -1,1, -1, -1, -1,1, -1, -1, -1,1,1].

Further, in order to better demonstrate the technical feasibility and the advancement of the a + and a-data patterns, specific numerical examples and corresponding periodic correlation diagrams are illustrated below in the second embodiment and the third embodiment, respectively.

Example two

The basic structure of a high-speed burst signal synchronization and equalization apparatus provided in this embodiment is the same as that of the first embodiment, except that, in this embodiment, a 32-bit PSBu data pattern is taken as an example, as shown in table 1, an a + portion of the PSBu data pattern is preferably represented by binary: [1,1, -1,1, -1, -1,1, -1,1,1,1, -1,1,1,1, -1], then the A-moiety is preferably represented as binary: [ -1, -1,1, -1,1,1, -1,1, -1, -1, -1,1, -1, -1, -1,1].

Table 1: 32-bit PSBu data pattern

Inx	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16
																	Bit	1	1	-1	1	-1	-1	1	-1	1	1	1	-1	1	1	1	-1
Inx	17	18	19	20	21	22	23	24	25	26	27	28	29	30	31	32
																	Bit	-1	-1	1	-1	1	1	-1	1	-1	-1	-1	1	-1	-1	-1	1

Based on the 32-bit PSBu data pattern in table 1, a PSBu and a local data pattern (see fig. 3) are constructed, and then a sliding window-based correlation operation pattern is performed, so as to obtain a periodic correlation diagram of the 32-bit PSBu data pattern shown in fig. 5, which shows a sliding window-based correlation operation result for one data period.

Referring to table 1 (32-bit PSBu data pattern) and fig. 5 (periodic correlation diagram of 32-bit PSBu data pattern), it can be seen that: the 32-bit PSBu data pattern employs the above-mentioned preferred a + and a-portions, the peak/valley values of the corresponding periodic correlation detection outputs are easy to identify, and the correlation values (correlation intermediate values) at other times than the peak/valley values are significantly distinguished from the peak/valley values (taking fig. 5 as an example: the "values" of the peak and valley are 30 and 0, respectively, and the "values" at all other places are around 15, then the peak and valley are significantly distinguished from other correlation intermediate values, which are very easy to distinguish); and, the A + part and the A-part both avoid long continuous '1' or '-1', and satisfy the rule design of the PSBu data pattern. In practical application, higher equalization and peak/valley detection efficiency can be achieved.

EXAMPLE III

The basic structure of a high-speed burst signal synchronization and equalization apparatus provided in this embodiment is the same as that of the first embodiment, except that, in this embodiment, a 64-bit PSBu data pattern is taken as an example, as shown in table 2, an a + portion of the PSBu data pattern is preferably represented by binary: [1, -1,1, -1, -1, -1,1,1, -1,1,1,1, -1, -1,1,1,1,1, -1, -1,1, -1,1, -1,1, -1, -1, -1,1], then part A-is preferably represented in binary form as: [ -1,1, -1,1,1,1, -1, -1,1, -1, -1, -1,1,1, -1, -1, -1, -1,1,1, -1,1, -1, -1,1,1, -1,1, -1,1,1,1].

Table 2: 64-bit PSBu data pattern

Inx	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16
																	Bit	1	-1	1	-1	-1	-1	1	1	-1	1	1	1	-1	-1	1	1
Inx	17	18	19	20	21	22	23	24	25	26	27	28	29	30	31	32
																	Bit	1	1	-1	-1	1	-1	1	1	-1	-1	1	-1	1	-1	-1	-1
Inx	33	34	35	36	37	38	39	40	41	42	43	44	45	46	47	48
																	Bit	-1	1	-1	1	1	1	-1	-1	1	-1	-1	-1	1	1	-1	-1
Inx	49	50	51	52	53	54	55	56	57	58	59	60	61	62	63	64
																	Bit	-1	-1	1	1	-1	1	-1	-1	1	1	-1	1	-1	1	1	1

Based on the 64-bit PSBu data pattern in table 2, a PSBu and a local data pattern (see fig. 3) are constructed, and then a sliding window-based correlation operation pattern is performed, so as to obtain a periodic correlation diagram of the 64-bit PSBu data pattern shown in fig. 6, which shows a sliding window-based correlation operation result for one data period.

Referring to table 2 (64-bit PSBu data pattern) and fig. 6 (periodic correlation diagram of 64-bit PSBu data pattern), it can be seen that: the 64-bit PSBu data pattern employs the above-mentioned preferred a + and a-portions, the peak/valley values of the corresponding periodic correlation detection outputs are easy to identify, and the correlation values (correlation intermediate values) at other times than the peak/valley values are significantly distinguished from the peak/valley values (taking fig. 6 as an example: the "values" of the peak and valley are 60 and 0, respectively, and the "values" at all other places are around 30, then the peak and valley are significantly distinguished from other correlation intermediate values, which are very easy to distinguish); and, the A + part and the A-part both avoid long continuous '1' or '-1', and satisfy the rule design of the PSBu data pattern. In practical application, higher equalization and peak/valley detection efficiency can be achieved.

Example four

Referring to fig. 7, based on the same inventive concept, an embodiment of the present invention further provides a synchronization and equalization method for a high-speed burst signal, where the method is based on the synchronization and equalization apparatus for a high-speed burst signal, and specifically includes the following steps:

step A, an equalizer receives an uplink burst signal, wherein a PSBu data mode of the uplink burst signal comprises an A + part and an A-part, and the A + part and the A-part are in a negative correlation characteristic; the equalizer transmits the calculated equalization output to the time synchronizer in a blind equalization mode or a training equalization mode under the control of the equalization controller;

step B, the time synchronizer outputs the output of the equalizer as a self output signal; meanwhile, an uplink burst signal is found based on the PSBu data mode, PSBu data mode boundary identification is carried out, and a found result and an identification result are fed back to an equalizer controller;

and step C, the equalization controller controls the equalizer to switch between a blind equalization mode and a training equalization mode according to the feedback of the time synchronizer and a preset equalization control state machine.

It should be noted that various changes and specific examples in the embodiments of the apparatus described above are also applicable to the method of the present embodiment, and those skilled in the art can clearly understand various implementation methods of the method in the present embodiment through the detailed description of the apparatus described above, so that the detailed description is omitted here for the brevity of the description.

Note that: the above-described embodiments are merely examples and are not intended to be limiting, and those skilled in the art can combine and combine some steps and devices from the above-described separately embodiments to achieve the effects of the present invention according to the concept of the present invention, and such combined and combined embodiments are also included in the present invention, and such combined and combined embodiments are not described herein separately.

Advantages, effects, and the like, which are mentioned in the embodiments of the present invention, are only examples and are not limiting, and they cannot be considered as necessarily possessed by the various embodiments of the present invention. Furthermore, the foregoing specific details disclosed herein are merely for purposes of example and for purposes of clarity of understanding, and are not intended to limit the embodiments of the invention to the particular details which may be employed to practice the embodiments of the invention.

The block diagrams of devices, apparatuses, systems involved in the embodiments of the present invention are only given as illustrative examples, and are not intended to require or imply that the connections, arrangements, configurations, etc. must be made in the manner shown in the block diagrams. These devices, apparatuses, devices, systems may be connected, arranged, configured in any manner, as will be appreciated by those skilled in the art. Words such as "including," "comprising," "having," and the like are open-ended words that mean "including, but not limited to," and are used interchangeably therewith. As used in connection with embodiments of the present invention, the terms "or" and "refer to the term" and/or "and are used interchangeably herein unless the context clearly dictates otherwise. The word "such as" is used in connection with embodiments of the present invention to mean, and is used interchangeably with, the word "such as but not limited to".

The flow charts of steps in the embodiments of the present invention and the above description of the methods are merely illustrative examples and are not intended to require or imply that the steps of the various embodiments must be performed in the order presented. As will be appreciated by those skilled in the art, the order of the steps in the above embodiments may be performed in any order. Words such as "thereafter," "then," "next," etc. are not intended to limit the order of the steps; these words are only used to guide the reader through the description of these methods. Furthermore, any reference to an element in the singular, for example, using the articles "a," "an," or "the" is not to be construed as limiting the element to the singular.

In addition, the steps and devices in the embodiments of the present invention are not limited to be implemented in a certain embodiment, and in fact, some steps and devices in the embodiments of the present invention may be combined according to the concept of the present invention to conceive new embodiments, and these new embodiments are also included in the scope of the present invention.

The respective operations in the embodiments of the present invention may be performed by any appropriate means capable of performing the corresponding functions. The means may comprise various hardware and/or software components and/or modules including, but not limited to, hardware circuitry or a processor.

The method of an embodiment of the invention includes one or more acts for implementing the method described above. The methods and/or acts may be interchanged with one another without departing from the scope of the claims. In other words, unless a specific order of actions is specified, the order and/or use of specific actions may be modified without departing from the scope of the claims.

Various changes, substitutions and alterations to the techniques described herein may be made by those skilled in the art without departing from the techniques of the teachings as defined by the appended claims. Moreover, the scope of the claims of the present disclosure is not limited to the particular aspects of the process, machine, manufacture, composition of matter, means, methods and acts described above. Processes, machines, manufacture, compositions of matter, means, methods, or acts, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding aspects described herein may be utilized. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or acts.

The previous description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects without departing from the scope of the invention. Thus, the present invention is not intended to be limited to the aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

The foregoing description has been presented for purposes of illustration and description. Furthermore, the description is not intended to limit embodiments of the invention to the form disclosed herein. While a number of example aspects and embodiments have been discussed above, those of skill in the art will recognize certain variations, modifications, alterations, additions and sub-combinations thereof. And those not described in detail in this specification are within the skill of the art.

Claims

1. A device for synchronizing and equalizing high-speed burst signals, comprising: the device comprises an equalizer, a time synchronizer and an equalization controller;

the equalization controller is configured to: controlling the equalizer to switch between a blind equalization mode and a training equalization mode according to the feedback of the time synchronizer and a preset equalization control state machine;

wherein the equalization control state machine of the equalization controller comprises: s1-ready state, S2-blind equalization state, S3-transition state, S4-training equalization state, S5-synchronization state; the equalization controller controls the equalizer to switch between a blind equalization mode and a training equalization mode according to a preset equalization control state machine, and the method specifically comprises the following operations:

2. The apparatus for synchronizing and equalizing a high-speed burst signal according to claim 1, wherein: the equalizer is an N-tap forward equalizer; the equalizer calculates an equalized output OUT at the current time according to N tap coefficients W [1,2, …, N ] and input signal samples IN [1,2, …, N ] corresponding to N taps at the current time, and the operation formula is as follows:

OUT＝P(W,IN)；

W’＝W+u*E*IN；

3. The apparatus for synchronizing and equalizing a high-speed burst signal according to claim 2, wherein: when the equalizer is in the blind equalization mode, the calculation formula of the error E is as follows:

E＝1–ABS(OUT)；

in the equation, the operator ABS (.) represents an absolute value operation.

4. The apparatus for synchronizing and equalizing a high-speed burst signal according to claim 2, wherein: when the equalizer is in a training equalization mode, the error E is calculated by the following formula:

E＝Ts–OUT；

5. The apparatus for synchronizing and equalizing a high-speed burst signal according to claim 1, wherein the time synchronizer performs PSBu data pattern boundary evaluation based on the PSBu data pattern and feeds back the evaluation result to the equalizer controller, comprising the following operations:

6. The apparatus for synchronizing and equalizing a high-speed burst signal as claimed in claim 1, wherein the a + portion and the a-portion of the PSBu data pattern satisfy the following rule:

1) the peak value/valley value of the correlation detection output is easy to identify, and the correlation values at other moments except the peak value/valley value are obviously distinguished from the peak value/valley value;

2) the A + and A-portions avoid longer consecutive "1" or "-1".

7. The apparatus for synchronizing and equalizing a high-speed burst signal according to claim 6, wherein: the PSBu data pattern is a 32-bit data pattern;

the A + part of the PSBu data pattern is represented by [1,1, -1,1, -1, -1,1, -1,1,1,1, -1] in a binary mode;

the A-portion of the PSBu data pattern is represented in binary as [ -1, -1,1, -1,1,1, -1,1, -1, -1, -1, 1.

8. The apparatus for synchronizing and equalizing a high-speed burst signal according to claim 6, wherein: the PSBu data pattern is a 64-bit data pattern;

the a + part of the PSBu data pattern is represented in binary as [1, -1,1, -1, -1, -1,1,1, -1,1,1,1, -1, -1,1, -1,1, -1, -1, -1;

the a-portion of the PSBu data pattern is represented in binary as [ -1,1, -1,1,1,1, -1, -1,1, -1, -1, -1,1,1, 1).

9. A method for synchronizing and equalizing a high-speed burst signal according to any one of claims 1 to 8, the method comprising the steps of:

the equalization controller controls the equalizer to switch between a blind equalization mode and a training equalization mode according to the feedback of the time synchronizer and a preset equalization control state machine;