CN112885855A - Deep silicon detector module integrated with pre-amplification circuit - Google Patents

Deep silicon detector module integrated with pre-amplification circuit Download PDF

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CN112885855A
CN112885855A CN202110056836.3A CN202110056836A CN112885855A CN 112885855 A CN112885855 A CN 112885855A CN 202110056836 A CN202110056836 A CN 202110056836A CN 112885855 A CN112885855 A CN 112885855A
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chip
detector
layer
detector chip
opening
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CN112885855B (en
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刘鹏
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Nuclear Core Optoelectronic Technology Shandong Co ltd
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Nuclear Core Optoelectronic Technology Shandong Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14634—Assemblies, i.e. Hybrid structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H01L27/14658—X-ray, gamma-ray or corpuscular radiation imagers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

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Abstract

The invention provides a deep silicon detector module integrated with a preamplification circuit, which comprises at least two detector chips; each detector chip is arranged in a stacked mode, and adjacent detector chips are arranged in an angle mode; the detector chip comprises a sensitive area, an integrated area, a bonding area and an opening area unit; the sensitive area unit comprises a silicon microstrip consisting of a plurality of photoelectric units; the integrated area unit comprises an ASIC chip, and the ASIC chip comprises an input pin and an output pin; the bonding area comprises input and output lead bonding pads and bonding aluminum wires; the input lead bonding pad is connected with the photoelectric unit and the input pin; the output lead bonding pad is connected with the output pins of the ASIC chips on the same layer, or the output lead pins of the ASIC chips on the adjacent layers; and the opening area is used for avoiding interlayer routing between the output pin of the ASIC chip and the output lead bonding pad of the adjacent layer, and avoiding the ASIC chip of the adjacent layer and the bonding aluminum wire between the bonding pad and the pin of the ASIC chip.

Description

Deep silicon detector module integrated with pre-amplification circuit
Technical Field
The invention belongs to the technical field of detectors, and particularly relates to a deep silicon detector module integrated with a preamplifier circuit.
Background
At present, a detector is used as a scintillator detector in the traditional CT, and a photodiode array is integrated below the detector, so that the scintillator detector has low imaging definition, cannot provide color images, and has large volume and heavy weight; and is limited by the size of the detector pixel, and the spatial resolution is limited.
The new generation of semiconductor detector for CT adopts a single chip as a minimum unit, adopts two-layer layout during arrangement, two layers are arranged in a staggered manner, and a two-side reading mode is adopted, wherein the semiconductor detector is limited by the arrangement layout, is divided into a front layer and a rear layer, occupies a large space, and a reading circuit is distributed on two sides, so that the detector is large in volume; secondly, the front layer and the rear layer of the semiconductor detector receive X-rays with optical path difference, and the received X-rays are inconsistent and influence the imaging definition; thirdly, the front layer and the rear layer of the semiconductor detector are distributed in a staggered mode, so that the semiconductor detector is not beneficial to installation.
This is a disadvantage of the prior art, and therefore, it is necessary to provide a deep silicon detector module with integrated preamplifier circuit to overcome the above-mentioned disadvantages of the prior art.
Disclosure of Invention
Aiming at the defects that the detector of the traditional CT in the prior art has low definition, large volume and limited resolution, and the new generation of semiconductor CT is arranged in two layers, has two-side reading, occupies large space, has large volume, influences definition and is complex to install, the invention provides a deep silicon detector module integrated with a preamplification circuit, so as to solve the technical problems.
The invention provides a deep silicon detector module integrated with a preamplification circuit, which comprises at least two detector chips;
each detector chip is stacked, and adjacent detector chips are arranged in an insulating manner;
the detector chips are provided with light receiving sides, the light receiving sides of the detector chips are arranged on the same cambered surface, the adjacent detector chips are arranged in an angle mode, and the included angle between the adjacent detector chips is smaller than a set threshold value;
the detector chip comprises a sensitive area unit, a preamplification processing chip integrated area unit, a bonding area unit and an opening area unit;
the sensitive area unit is arranged on the light receiving side of the detector chip; the sensitive area unit comprises a plurality of silicon micro-strips, and the silicon micro-strips are parallel and distributed towards the inner side of the detector chip along the edge of the light receiving side of the detector chip;
each silicon micro-strip comprises a plurality of photoelectric units, and all the photoelectric units of each detector chip form a photoelectric array; the photoelectric unit of the silicon microstrip arranged on the light receiving side of the detector chip forms a light receiving surface which is used for receiving X-ray;
the pre-amplification processing chip integrated area unit comprises an ASIC chip, and the ASIC chip is provided with an input pin and an output pin;
the bonding area unit comprises an input lead bonding pad, an output lead bonding pad and a bonding aluminum wire; the input lead bonding pad is connected with each photoelectric unit through a metal grid line and is connected with an ASIC chip input pin of the same layer of detector chips through a bonding aluminum wire; the output lead bonding pad is connected with the output pins of the ASIC chips of the same layer of detector chips or the output pins of the ASIC chips of the adjacent layer of detector chips through bonding aluminum wires;
and the opening area unit is used for avoiding interlayer routing of the bonding aluminum wire connected between the output pin of the ASIC chip and the output lead bonding pad of the adjacent detector chip. And the photosensitive area unit is a working area and is used for converting the X-rays received by the light receiving surface into carriers.
Furthermore, the detector chip is divided into a main detector chip and a slave detector chip;
the number of the main detector chips is one;
the bonding area of the main detector chip comprises an input lead bonding pad, an output lead bonding pad on the same layer, a cross-layer output lead bonding pad and a bonding aluminum wire;
the bonding area of the slave detector chip comprises an input lead bonding pad and a bonding aluminum wire;
the output lead bonding pad on the same layer of the main detector chip is connected with the output pin of the ASIC chip of the detector chip where the main detector chip is located through a bonding aluminum wire;
and the cross-layer output lead bonding pad of the main detector chip is connected with the output pin of the ASIC chip of the adjacent detector chip through a bonding aluminum wire penetrating through the opening area.
Furthermore, a main output bonding pad is arranged on the main detector chip;
the number of the main output bonding pads is equal to the sum of the number of the output lead bonding pads on the same layer and the number of the output lead bonding pads across layers;
the main output bonding pad is arranged at the edge of the main detector chip, the main output bonding pad is arranged on the opposite side of the light receiving side of the main detector chip, and the main output bonding pad is connected with the same-layer output lead bonding pad and the cross-layer output lead bonding pad in a one-to-one correspondence mode through metal grid lines.
Further, the opening area unit comprises a routing opening;
when the main detector chip is positioned on the upper layer of the auxiliary detector chip, the wiring opening is arranged on the main detector chip, and the cross-layer output lead bonding pad is arranged on one side of the wiring opening;
when the main detector chip is positioned on the lower layer of the auxiliary detector chip, the wiring open hole is arranged on the auxiliary detector chip, is arranged on one side of the output pin of the ASIC chip and corresponds to the cross-layer output lead bonding pad of the main detector chip.
Furthermore, the hole area unit is also used for avoiding an ASIC chip of an adjacent layer and a bonding aluminum wire thereof; the opening area unit also comprises a chip avoiding opening;
and a chip avoiding opening is arranged on the upper detector chip, the chip avoiding opening corresponds to the ASIC chip and the bonding aluminum wire of the adjacent detector chip, and the size of the chip avoiding opening is larger than that of the corresponding ASIC chip and the bonding aluminum wire.
Further, when the upper-layer detector chip is a main detector chip, the chip avoidance open hole is set as a first composite open hole;
the first composite opening is a wiring opening of a lower layer of a cross-layer output lead bonding pad bonding aluminum wire from the detector chip to the main detector chip and is an avoiding opening of a lower layer of an ASIC chip.
Furthermore, the opening area unit is also used for avoiding bonding aluminum wires of the cross-layer output lead bonding pad; the opening area also comprises a cross-layer avoiding opening;
when the detector chips are at least three layers, the bonded aluminum wires of the main detector chip and the slave detector chip are wired in a cross-layer mode, a cross-layer avoiding opening is formed in the position, corresponding to the other detector chip, of the other detector chip, and the cross-layer avoiding opening is larger than the size of the bonded aluminum wires corresponding to the cross layers.
Further, when the slave detector chip provided with the cross-layer avoidance hole is positioned at the lower layer, the cross-layer avoidance hole is set as a second composite hole;
the second composite opening is a cross-layer avoidance opening from the upper-layer slave detector chip to the main detector chip and a chip avoidance opening of an ASIC chip of the upper-layer slave detector chip;
the size of the second composite opening is larger than the size of an ASIC chip of the slave detector chip and the size of a bonding aluminum wire spanning the ASIC chip and the master detector chip.
Further, the number of input pins, the number of output pins, and the number of photoelectric cells of the ASIC chip on each detector chip are equal.
Furthermore, the light receiving surfaces of the detector chips are arranged on the same cambered surface, the distances from the light receiving surfaces to the X-ray source are equal, and the included angle between the adjacent detector chips is set according to the distance between the X-ray source and the light receiving surfaces;
the photoelectric arrays of the detector chips are distributed in the same manner, the silicon micro-strips which are arranged on the detector chips and have the same distance with the X-ray source are positioned on the same cambered surface, and the X-ray penetrates through the light receiving surface and then sequentially penetrates through the silicon micro-strips on the same detector chip.
The beneficial effect of the invention is that,
according to the deep silicon detector module integrated with the pre-amplification circuit, the ASIC chip used for integrated pre-amplification processing is integrated into the detector chip through structural design, so that the size is small, and the size and the weight of the detector chip are reduced; according to the invention, the arrangement is tighter when the detector chip is assembled by the cross-layer bonding aluminum wire routing, the trouble and the labor are saved, and the reliability is better; a plurality of detector modules are assembled into a detection unit, so that the detector modules are closely arranged, the X-ray illuminated surface is on one surface, the optical path difference of the X-ray does not exist, and the imaging is clearer.
In addition, the invention has reliable design principle, simple structure and very wide application prospect.
Therefore, compared with the prior art, the invention has prominent substantive features and remarkable progress, and the beneficial effects of the implementation are also obvious.
Drawings
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of the structure of the bottom detector chip in one embodiment of the invention;
FIG. 2 is a schematic diagram of a primary detector chip configuration in accordance with an embodiment of the present invention;
FIG. 3 is a schematic diagram of the top detector chip configuration in accordance with an embodiment of the present invention;
FIG. 4 is a side view of a deep silicon detector module with integrated pre-amplification circuitry in use according to one embodiment of the invention;
in the figure, 1 — first slave detector chip; 2-a main detector chip; 3-a second slave detector chip; 4-sensitive area unit; 5-X-ray source; 6-X shooting; 7-a light-receiving surface; a1 — first ASIC chip; a2 — second ASIC chip; a3 — third ASIC chip; p11 — first input lead pad; p21 — second input lead pad; p31-third input lead pad; p12-first cross-layer output lead pad; p22-same layer output lead pad; p32-third cross-layer output lead pad; b11 — first input wire-bonded aluminum wire; b21 — second input wire-bonded aluminum wire; b31 — third input wire-bonded aluminum wire; k1 — a first trace opening; k2-second cross-layer avoidance opening; k3-third trace opening; k4-a fourth chip avoiding opening; k5-fifth cross-layer avoidance opening; f1-first metal grid line; f2-second metal grid line.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is only a part of the embodiment of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1:
the invention provides a deep silicon detector module integrated with a preamplification circuit, which comprises at least two detector chips;
each detector chip is stacked, and adjacent detector chips are arranged in an insulating manner;
the detector chips are provided with light receiving sides, the light receiving sides of the detector chips are arranged on the same cambered surface, the adjacent detector chips are arranged in an angle mode, and the included angle between the adjacent detector chips is smaller than a set threshold value;
the detector chip comprises a sensitive area unit, a preamplification processing chip integrated area unit, a bonding area unit and an opening area unit;
the sensitive area unit is arranged on the light receiving side of the detector chip; the sensitive area unit comprises a plurality of silicon micro-strips, and the silicon micro-strips are parallel and distributed towards the inner side of the detector chip along the edge of the light receiving side of the detector chip;
each silicon micro-strip comprises a plurality of photoelectric units, and all the photoelectric units of each detector chip form a photoelectric array; the photoelectric unit of the silicon microstrip arranged on the light receiving side of the detector chip forms a light receiving surface which is used for receiving X-ray;
the pre-amplification processing chip integrated area unit comprises an ASIC chip, and the ASIC chip is provided with an input pin and an output pin;
the bonding area unit comprises an input lead bonding pad, an output lead bonding pad and a bonding aluminum wire; the input lead bonding pad is connected with each photoelectric unit through a metal grid line and is connected with an ASIC chip input pin of the same layer of detector chips through a bonding aluminum wire; the output lead bonding pad is connected with the output pins of the ASIC chips of the same layer of detector chips or the output pins of the ASIC chips of the adjacent layer of detector chips through bonding aluminum wires;
and the opening area unit is used for avoiding interlayer routing of the bonding aluminum wire connected between the output pin of the ASIC chip and the output lead bonding pad of the adjacent detector chip.
In some embodiments, the detector chips are divided into master detector chips and slave detector chips;
the number of the main detector chips is one;
the bonding area of the main detector chip comprises an input lead bonding pad, an output lead bonding pad on the same layer, a cross-layer output lead bonding pad and a bonding aluminum wire;
the bonding area of the slave detector chip comprises an input lead bonding pad and a bonding aluminum wire;
the output lead bonding pad on the same layer of the main detector chip is connected with the output pin of the ASIC chip of the detector chip where the main detector chip is located through a bonding aluminum wire;
and the cross-layer output lead bonding pad of the main detector chip is connected with the output pin of the ASIC chip of the adjacent detector chip through a bonding aluminum wire penetrating through the opening area.
In some embodiments, a primary output pad is also disposed on the primary detector chip;
the number of the main output bonding pads is equal to the sum of the number of the output lead bonding pads on the same layer and the number of the output lead bonding pads across layers;
the main output bonding pad is arranged at the edge of the main detector chip, the main output bonding pad is arranged on the opposite side of the light receiving side of the main detector chip, and the main output bonding pad is connected with the same-layer output lead bonding pad and the cross-layer output lead bonding pad in a one-to-one correspondence mode through metal grid lines.
In some embodiments, the opening area unit includes a trace opening;
when the main detector chip is positioned on the upper layer of the auxiliary detector chip, the wiring opening is arranged on the main detector chip, and the cross-layer output lead bonding pad is arranged on one side of the wiring opening;
when the main detector chip is positioned on the lower layer of the auxiliary detector chip, the wiring open hole is arranged on the auxiliary detector chip, is arranged on one side of the output pin of the ASIC chip and corresponds to the cross-layer output lead bonding pad of the main detector chip.
In some embodiments, the opening area unit is also used for avoiding the ASIC chip of the adjacent layer and the bonding aluminum wire thereof; the opening area unit also comprises a chip avoiding opening;
and a chip avoiding opening is arranged on the upper detector chip, the chip avoiding opening corresponds to the ASIC chip and the bonding aluminum wire of the adjacent detector chip, and the size of the chip avoiding opening is larger than that of the corresponding ASIC chip and the bonding aluminum wire.
In some embodiments, when the upper detector chip is a main detector chip, the chip avoidance opening is set as a first compound opening;
the first composite opening is a wiring opening of a lower layer of a cross-layer output lead bonding pad bonding aluminum wire from the detector chip to the main detector chip and is an avoiding opening of a lower layer of an ASIC chip.
In some embodiments, the opening area unit is also used for avoiding bonding aluminum wires of the cross-layer output lead bonding pad; the opening area also comprises a cross-layer avoiding opening;
when the detector chips are at least three layers, the bonded aluminum wires of the main detector chip and the slave detector chip are wired in a cross-layer mode, a cross-layer avoiding opening is formed in the position, corresponding to the other detector chip, of the other detector chip, and the cross-layer avoiding opening is larger than the size of the bonded aluminum wires corresponding to the cross layers.
In some embodiments, when the slave detector chip provided with the cross-layer avoidance opening is positioned at a lower layer, the cross-layer avoidance opening is set as a second composite opening;
the second composite opening is a cross-layer avoidance opening from the upper-layer slave detector chip to the main detector chip and a chip avoidance opening of an ASIC chip of the upper-layer slave detector chip;
the size of the second composite opening is larger than the size of an ASIC chip of the slave detector chip and the size of a bonding aluminum wire spanning the ASIC chip and the master detector chip.
In some embodiments, the number of input pins, the number of output pins, and the number of optoelectronic units of the ASIC chip on each detector chip are equal.
In some embodiments, the light receiving surfaces of the detector chips are arranged on the same cambered surface, the distances from the light receiving surfaces to the X-ray source are equal, and the included angle between the adjacent detector chips is set according to the distance between the X-ray source and the light receiving surfaces;
the photoelectric arrays of the detector chips are distributed in the same manner, the silicon micro-strips which are arranged on the detector chips and have the same distance with the X-ray source are positioned on the same cambered surface, and the X-ray penetrates through the light receiving surface and then sequentially penetrates through the silicon micro-strips on the same detector chip.
In some embodiments, the detector chip adopts a high-purity silicon wafer as a substrate material, and the thickness of the detector chip is greater than or equal to 200 microns;
the thickness of the input lead bonding aluminum wire and the thickness of the output lead bonding aluminum wire on the same layer are 0.1-0.5 mm, namely the height of the protruding detector chip is 0.1-0.5 mm;
the thickness of the cross-layer output lead bonding aluminum wire is 0.1-0.5 mm, namely the width of the wiring opening is larger than 0.1-0.5 mm.
Example 2:
as shown in fig. 1, 2 and 3, the present invention provides a deep silicon detector module integrated with a preamplifier circuit, which includes three detector chips; the detector chip is divided into a main detector chip and a slave detector chip; the three detector chips are a main detector chip 1, a first slave detector chip 2 and a second slave detector chip 3;
three detector chips are stacked, wherein a first slave detector chip 2 is positioned at the lowest layer, a main detector chip 1 is positioned at the middle layer, a second slave detector chip 3 is positioned at the uppermost layer, and adjacent detector chips are arranged in an insulating manner;
the three detector chips are provided with light receiving sides, the light receiving sides of the three detector chips are arranged on the same arc surface, the main detector chip 1, the first slave detector chip 2 and the second slave detector chip 3 are arranged in an angle mode, and the included angle between every two adjacent detector chips is smaller than a set threshold value;
the three detector chips comprise a sensitive area unit 4, a preamplification processing chip integrated area unit, a bonding area unit and a hole opening area unit;
the sensitive area unit 4 is arranged on the light receiving side of the detector chip; the sensitive area unit 4 comprises a plurality of silicon micro-strips, and the silicon micro-strips are parallel and distributed towards the inner side of the detector chip along the edge of the light receiving side of the detector chip;
each silicon micro-strip comprises a plurality of photoelectric units, and all the photoelectric units of each detector chip form a photoelectric array; the photoelectric unit of the silicon microstrip arranged on the light receiving side of the detector chip forms a light receiving surface 7, and the light receiving surface 7 is used for receiving the X-ray 6; the light receiving surfaces 7 of the detector chips are arranged on the same cambered surface, the distances from the light receiving surfaces 7 to the X-ray source 5 are equal, and the included angle between the adjacent detector chips is set according to the distance between the X-ray source 5 and the light receiving surfaces 7;
the photoelectric arrays of the detector chips are distributed in the same manner, the silicon micro-strips which are arranged on the detector chips and have the same distance with the X-ray source 5 are positioned on the same cambered surface, and the X-ray 6 passes through the light receiving surface 7 and then sequentially passes through the silicon micro-strips on the same detector chip;
the pre-amplification processing chip integrated area unit of the first slave detector chip 2 comprises a first ASIC chip A1, and the number of the first ASIC chips A1 is two; the preamplification processing chip integrated area unit of the main detector chip 1 comprises two second ASIC chips A2, and the number of the second ASIC chips A2 is two; the pre-amplification processing chip integrated area unit of the second slave detector chip 3 comprises a third ASIC chip A3, and the number of the third ASIC chips A3 is two; each ASIC chip comprises an input pin and an output pin;
the bonding region unit of the main detector chip 1 comprises two groups of second input lead bonding pads P21, two groups of same-layer output lead bonding pads P22, two groups of first cross-layer output lead bonding pads P12, two groups of third cross-layer output lead bonding pads P32 and bonding aluminum wires;
the bonding pad unit of the first slave probe chip 2 includes a first input lead pad P11 and a bonding aluminum wire;
the bonding pad unit of the second slave probe chip 3 includes a third input lead pad P31 and a bonding aluminum wire;
two groups of second input lead bonding pads P21 of the main detector chip 1 are connected with each photoelectric unit of the main detector chip 1 through a first metal grid line F1 and are connected with input pins of two second ASIC chips A2 through bonding aluminum wires;
two groups of first input lead bonding pads P11 of the first slave detector chip 2 are connected with each photoelectric unit of the first slave detector chip 2 through a first metal grid line F1 and are connected with input pins of two pieces of first ASIC chips A1 through bonding aluminum wires;
two groups of second input lead bonding pads P31 of the second slave detector chip 3 are connected with each photoelectric unit of the second slave detector chip 3 through a first metal grid line F1 and are connected with input pins of two pieces of third ASIC chips A3 through bonding aluminum wires;
two groups of same-layer output lead bonding pads P22 of the main detector chip 1 are connected with an output pin of a second ASIC chip A2 through bonding aluminum wires;
two groups of first cross-layer output lead bonding pads P12 of the main detector chip 1 are connected with output pins of a first ASIC chip A1 of the first slave detector chip 2 through bonding aluminum wires penetrating through the opening area;
two groups of third cross-layer output lead bonding pads P32 of the main detector chip 1 are connected with output pins of a third ASIC chip A3 of the second slave detector chip 3 through bonding aluminum wires penetrating through the opening area;
the opening area unit is used for connecting an output pin of the ASIC chip and an interlayer routing of a bonding aluminum wire of an output lead bonding pad of an adjacent layer of detector chip;
the opening area unit comprises a wiring opening;
the main detector chip 1 is positioned on the upper layer of the first slave detector chip 2, two groups of first routing open holes K1 are formed in the main detector chip 2, and two groups of second cross-layer output lead bonding pads P12 are respectively arranged on one sides of the two groups of first routing open holes K1;
the main detector chip 1 is positioned at the lower layer of the second slave detector chip 3, two groups of third wiring openings K3 are arranged on the second slave detector chip 3, and two groups of third wiring openings K3 are arranged at one side of the output pins of the two third ASIC chips A3 and respectively correspond to the positions of two groups of third cross-layer output lead bonding pads P32 of the main detector chip 2;
the opening area unit is also used for avoiding an ASIC chip and a bonding aluminum wire of the adjacent layer; the opening area unit also comprises a chip avoiding opening;
a chip avoiding opening is formed in the upper detector chip, the chip avoiding opening corresponds to the ASIC chip and the bonding aluminum wire of the adjacent detector chip, and the size of the chip avoiding opening is larger than that of the corresponding ASIC chip and the bonding aluminum wire of the ASIC chip;
a fourth chip avoiding opening K4 is formed in the second slave detector chip 3, the fourth chip avoiding opening K4 corresponds to the positions of the two groups of first ASIC chips A1 and bonding aluminum wires of the main detector chip 1, and the size of the fourth chip avoiding opening K4 is larger than the sizes of the two groups of first ASIC chips A1 and the bonding aluminum wires thereof;
the main detector chip 1 is an upper layer of the first slave detector chip 2, and the two groups of first routing open holes K1 are first composite open holes;
the first composite opening is a routing opening of a cross-layer output lead bonding pad aluminum wire from the first slave detector chip 2 to the main detector chip 1 and is also a chip avoiding opening of two groups of first ASIC chips A1 of the first slave detector chip 2;
two groups of second cross-layer avoiding holes K2 are formed in the second slave detector chip 3, and two groups of second cross-layer avoiding holes K2 are respectively used for avoiding cross-layer output bonding aluminum wires connected from two groups of first cross-layer output lead bonding pads P12 of the master detector chip 1 to output pins of two first ASIC chips A1 of the first slave detector chip 2;
two groups of fifth cross-layer avoiding holes K5 are formed in the first slave detector chip 2, and the two groups of fifth cross-layer avoiding holes K5 are respectively used for cross-layer output bonding aluminum wires connected from two groups of third cross-layer output lead bonding pads P32 of the master detector chip 2 to output pins of two third ASIC chips A3 of the second detector chip 3;
the two groups of fifth cross-layer avoidance holes K5 are second compound holes and are also used for avoiding two groups of third ASIC chips A3.
In the above embodiment 2, each ASIC chip is integrated in the dead zone of the detector chip where the ASIC chip is located, and the number of input pins and the number of corresponding input lead pads of each ASIC chip are equal to the number of photoelectric cells of the photoelectric array of the detector chip where the ASIC chip is located, that is, the number of input pins and the number of corresponding input lead pads of each ASIC chip are matched with the number of pixels of the detector chip.
In the above embodiment 2, the main detector chip 1 is further provided with a main output pad;
the number of the main output bonding pads is equal to the sum of the number of the output lead bonding pads on the same layer and the number of the output lead bonding pads across layers;
the main output bonding pad is arranged at the edge of the main detector chip 1, the main output bonding pad is arranged on the opposite side of the light receiving side of the main detector chip, and the main output bonding pad is connected with the same-layer output lead bonding pad and the cross-layer output lead bonding pad in a one-to-one correspondence mode through the second metal grid lines F2.
Although the present invention has been described in detail by referring to the drawings in connection with the preferred embodiments, the present invention is not limited thereto. Various equivalent modifications or substitutions can be made on the embodiments of the present invention by those skilled in the art without departing from the spirit and scope of the present invention, and these modifications or substitutions are within the scope of the present invention/any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims (10)

1. A deep silicon detector module integrated with a preamplification circuit is characterized by comprising at least two detector chips;
each detector chip is stacked, and adjacent detector chips are arranged in an insulating manner;
the detector chips are provided with light receiving sides, the light receiving sides of the detector chips are arranged on the same cambered surface, the adjacent detector chips are arranged in an angle mode, and the included angle between the adjacent detector chips is smaller than a set threshold value;
the detector chip comprises a sensitive area unit, a preamplification processing chip integrated area unit, a bonding area unit and an opening area unit;
the sensitive area unit is arranged on the light receiving side of the detector chip; the sensitive area unit comprises a plurality of silicon micro-strips, and the silicon micro-strips are parallel and distributed towards the inner side of the detector chip along the edge of the light receiving side of the detector chip;
each silicon micro-strip comprises a plurality of photoelectric units, and all the photoelectric units of each detector chip form a photoelectric array; the photoelectric unit of the silicon microstrip arranged on the light receiving side of the detector chip forms a light receiving surface which is used for receiving X-ray;
the pre-amplification processing chip integrated area unit comprises an ASIC chip, and the ASIC chip is provided with an input pin and an output pin;
the bonding area unit comprises an input lead bonding pad, an output lead bonding pad and a bonding aluminum wire; the input lead bonding pad is connected with each photoelectric unit through a metal grid line and is connected with an ASIC chip input pin of the same layer of detector chips through a bonding aluminum wire; the output lead bonding pad is connected with the output pins of the ASIC chips of the same layer of detector chips or the output pins of the ASIC chips of the adjacent layer of detector chips through bonding aluminum wires;
and the opening area unit is used for avoiding interlayer routing of the bonding aluminum wire connected between the output pin of the ASIC chip and the output lead bonding pad of the adjacent detector chip.
2. The deep silicon detector module with integrated preamplification circuit of claim 1, wherein the detector chip is divided into a master detector chip and a slave detector chip;
the number of the main detector chips is one;
the bonding area of the main detector chip comprises an input lead bonding pad, an output lead bonding pad on the same layer, a cross-layer output lead bonding pad and a bonding aluminum wire;
the bonding area of the slave detector chip comprises an input lead bonding pad and a bonding aluminum wire;
the output lead bonding pad on the same layer of the main detector chip is connected with the output pin of the ASIC chip of the detector chip where the main detector chip is located through a bonding aluminum wire;
and the cross-layer output lead bonding pad of the main detector chip is connected with the output pin of the ASIC chip of the adjacent detector chip through a bonding aluminum wire penetrating through the opening area.
3. The integrated preamp circuit deep silicon detector module as claimed in claim 2, wherein a primary output pad is further disposed on the primary detector chip;
the number of the main output bonding pads is equal to the sum of the number of the output lead bonding pads on the same layer and the number of the output lead bonding pads across layers;
the main output bonding pad is arranged on the edge of the main detector chip, the main output bonding pad is arranged on one side, opposite to the sensitive area unit photoelectric array, of the main detector chip, and the main output bonding pad is connected with the same-layer output lead bonding pad and the cross-layer output lead bonding pad in a one-to-one correspondence mode through the metal grid lines.
4. The deep silicon detector module of integrated preamp circuit of claim 2, wherein the open area unit includes a trace opening;
when the main detector chip is positioned on the upper layer of the auxiliary detector chip, the wiring opening is arranged on the main detector chip, and the cross-layer output lead bonding pad is arranged on one side of the wiring opening;
when the main detector chip is positioned on the lower layer of the auxiliary detector chip, the wiring open hole is arranged on the auxiliary detector chip, is arranged on one side of the output pin of the ASIC chip and corresponds to the cross-layer output lead bonding pad of the main detector chip.
5. The deep silicon detector module with integrated preamplification circuit as claimed in claim 4, wherein the opening area unit is further used for avoiding the ASIC chip of the adjacent layer and the bonding aluminum wire thereof; the opening area unit also comprises a chip avoiding opening;
and a chip avoiding opening is arranged on the upper detector chip, the chip avoiding opening corresponds to the ASIC chip and the bonding aluminum wire of the adjacent detector chip, and the size of the chip avoiding opening is larger than that of the corresponding ASIC chip and the bonding aluminum wire.
6. The deep silicon detector module with integrated preamplification circuit of claim 5, wherein when the upper detector chip is a main detector chip, the chip avoidance opening is set to be a first compound opening;
the first composite opening is a wiring opening of a lower layer of a cross-layer output lead bonding pad bonding aluminum wire from the detector chip to the main detector chip and is an avoiding opening of a lower layer of an ASIC chip.
7. The deep silicon detector module with integrated preamplification circuit as claimed in claim 5, wherein the opening area unit is further used for avoiding bonding aluminum wires of the cross-layer output lead bonding pad; the opening area also comprises a cross-layer avoiding opening;
when the detector chips are at least three layers, the bonded aluminum wires of the main detector chip and the slave detector chip are wired in a cross-layer mode, a cross-layer avoiding opening is formed in the position, corresponding to the other detector chip, of the other detector chip, and the cross-layer avoiding opening is larger than the size of the bonded aluminum wires corresponding to the cross layers.
8. The deep silicon detector module with integrated preamplification circuit of claim 7, wherein the cross-layer avoidance opening is set to a second compound opening when the slave detector chip with the cross-layer avoidance opening is positioned at a lower layer;
the second composite opening is a cross-layer avoidance opening from the upper-layer slave detector chip to the main detector chip and a chip avoidance opening of an ASIC chip of the upper-layer slave detector chip;
the size of the second composite opening is larger than the size of an ASIC chip of the slave detector chip and the size of a bonding aluminum wire spanning the ASIC chip and the master detector chip.
9. The deep silicon detector module with integrated preamp circuit of claim 1, wherein the number of input pins, the number of output pins and the number of photo cells of the ASIC chip on each detector chip are equal.
10. The deep silicon detector module with integrated preamplification circuit as claimed in claim 1, wherein the light receiving surfaces of each detector chip are arranged on the same arc surface, the distance between each light receiving surface and the X-ray source is equal, and the included angle between adjacent detector chips is set according to the distance between the X-ray source and the light receiving surface;
the photoelectric arrays of the detector chips are distributed in the same manner, the silicon micro-strips which are arranged on the detector chips and have the same distance with the X-ray source are positioned on the same cambered surface, and the X-ray penetrates through the light receiving surface and then sequentially penetrates through the silicon micro-strips on the same detector chip.
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CN102844680A (en) * 2010-04-15 2012-12-26 浜松光子学株式会社 Radiation detector module
CN102856324A (en) * 2012-09-18 2013-01-02 厦门大学 Silicon-based uniwafer photoelectricity integrated receiving chip for plastic optical fiber communication
CN109196385A (en) * 2016-05-26 2019-01-11 皇家飞利浦有限公司 Multifunctional radiation detector
CN109891589A (en) * 2016-10-27 2019-06-14 株式会社理学 Detector
CN111129046A (en) * 2018-10-31 2020-05-08 台湾积体电路制造股份有限公司 Semiconductor structure and forming method thereof

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1304048A (en) * 2000-01-07 2001-07-18 株式会社岛津制作所 Two dimension array type radiographic detector
CN102844680A (en) * 2010-04-15 2012-12-26 浜松光子学株式会社 Radiation detector module
CN102856324A (en) * 2012-09-18 2013-01-02 厦门大学 Silicon-based uniwafer photoelectricity integrated receiving chip for plastic optical fiber communication
CN109196385A (en) * 2016-05-26 2019-01-11 皇家飞利浦有限公司 Multifunctional radiation detector
CN109891589A (en) * 2016-10-27 2019-06-14 株式会社理学 Detector
CN111129046A (en) * 2018-10-31 2020-05-08 台湾积体电路制造股份有限公司 Semiconductor structure and forming method thereof

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