CN112885832A - Semiconductor structure and manufacturing method thereof - Google Patents

Semiconductor structure and manufacturing method thereof Download PDF

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Publication number
CN112885832A
CN112885832A CN201911205669.3A CN201911205669A CN112885832A CN 112885832 A CN112885832 A CN 112885832A CN 201911205669 A CN201911205669 A CN 201911205669A CN 112885832 A CN112885832 A CN 112885832A
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silicon
bit line
layer
group
rows
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刘忠明
白世杰
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to CN201911205669.3A priority Critical patent/CN112885832A/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines

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  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)

Abstract

The present disclosure provides a semiconductor structure and a method of manufacturing the same. The structure includes: a substrate; the first capacitor layer is positioned on the substrate and comprises a plurality of first capacitors; the second bit line layer is positioned above the first capacitor layer and comprises a plurality of second bit lines which are arranged in parallel; the word line layer is positioned above the second bit line layer and comprises a plurality of word lines arranged in parallel; the first bit line layer is positioned above the word line layer and comprises a plurality of first bit lines arranged in parallel; the second capacitance layer is positioned above the first bit line layer and comprises a plurality of second capacitances; a plurality of first and second silicon pillars perpendicular to the second bit line layer, the word line layer, the first bit line layer, wherein: the first doping area of each first silicon column is electrically connected with a first capacitor, and the second doping area is electrically connected with a first bit line; the first doped region of each second silicon column is electrically connected with a second capacitor, and the second doped region is electrically connected with a second bit line; the plurality of word lines wrap the middle of the first silicon pillar and/or the second silicon pillar. The present disclosure has a higher element density.

Description

Semiconductor structure and manufacturing method thereof
Technical Field
The present disclosure relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure with a higher element density and a method for manufacturing the same.
Background
As the memory demand increases, increasing the density of devices placed during the fabrication of memory devices is a significant issue in the field.
In the related art, there is 4F for building a vertical transistor2Techniques to vertically dispose transistors on a substrate to increase the number of transistors per unit area. However, as the demand for increased storage density further escalates, 4F2Technology has reached the density limit and continuing to shorten the spacing between transistors will create serious cross-talk problems that greatly affect the performance of the memory element. Accordingly, there is a need for a semiconductor structure for memory devices that can address new requirements.
It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
It is an object of the present disclosure to provide a semiconductor structure and method of fabricating the same that overcomes, at least to some extent, the problem of limited density of elements in a memory array due to the limitations and disadvantages of the related art.
According to a first aspect of the present disclosure, there is provided a semiconductor structure comprising:
a substrate on which a logic circuit is formed, the logic circuit including a plurality of logic elements;
a first capacitor layer located above the substrate and including a plurality of first capacitors;
the second bit line layer is positioned above the first capacitor layer and comprises a plurality of second bit lines arranged in parallel;
the word line layer is positioned above the second bit line layer and comprises a plurality of word lines arranged in parallel;
the first bit line layer is positioned above the word line layer and comprises a plurality of first bit lines arranged in parallel;
a second capacitor layer located above the first bit line layer and including a plurality of second capacitors;
a plurality of first silicon pillars and a plurality of second silicon pillars perpendicular to the second bit line layer, the word line layer, the first bit line layer, wherein:
the first doped region of each first silicon pillar is electrically connected with one first capacitor and the second doped region is electrically connected with one first bit line;
the first doped region of each second silicon pillar is electrically connected with one second capacitor and the second doped region is electrically connected with one second bit line;
the plurality of word lines wrap the middle of the first silicon pillar and/or the second silicon pillar.
In an exemplary embodiment of the present disclosure, the second bit line wraps around at least a portion of the second doped region of the second silicon pillar.
In an exemplary embodiment of the present disclosure, an upper surface of the second bit line is connected to the second doping region of the second silicon pillar.
In an exemplary embodiment of the present disclosure, the second bit line layer and the word line layer further include in between:
a first intermediate layer wrapping at least a portion of the first doped region of the first silicon pillar and at least a portion of the second doped region of the second silicon pillar.
In an exemplary embodiment of the present disclosure, the first bit line wraps around at least a portion of the second doped region of the first silicon pillar.
In an exemplary embodiment of the present disclosure, a lower surface of the first bit line is connected to the second doping region of the first silicon pillar.
In an exemplary embodiment of the present disclosure, the middle of the first bit line layer and the word line layer further includes:
and the second intermediate layer wraps at least part of the first doped region of the second silicon column and at least part of the second doped region of the first silicon column.
In an exemplary embodiment of the present disclosure, an insulating layer is present between the word line and the first and second silicon pillars.
In one exemplary embodiment of the present disclosure, the first silicon pillars and the second silicon pillars are arranged in m rows and n columns in the same layer, the first silicon pillars are divided into a first group and a second group, and the second silicon pillars are divided into a third group and a fourth group, wherein,
the first silicon pillars are positioned in odd rows and the second silicon pillars are positioned in even rows, the first silicon pillars of the first group are positioned in odd columns of the odd rows, and the first silicon pillars of the second group are positioned in even columns of the adjacent odd rows; the second silicon pillars of the third group are all positioned in even-numbered rows and even-numbered columns, and the second silicon pillars of the fourth group are all positioned in odd-numbered columns of adjacent even-numbered rows;
or the first silicon pillars are positioned in even rows and the second silicon pillars are positioned in odd rows, the first silicon pillars of the first group are positioned in even rows and even columns, and the first silicon pillars of the second group are positioned in odd columns of adjacent even rows; the second silicon columns of the third group are all positioned in odd-numbered columns of the odd-numbered rows, and the second silicon columns of the fourth group are all positioned in even-numbered columns of the adjacent odd-numbered rows.
According to a second aspect of the present disclosure, there is provided a method of manufacturing a semiconductor structure, comprising:
providing a substrate, wherein a logic circuit is formed on the substrate and comprises a plurality of logic elements;
manufacturing a first capacitor layer above the substrate, wherein the first capacitor layer comprises a plurality of first capacitors, and the position of each first capacitor corresponds to the position of one first silicon pillar;
manufacturing a second bit line layer above the first capacitor layer, wherein the second bit line layer comprises a plurality of second bit lines arranged in parallel, and each second bit line is connected with a second doping region of a second silicon column;
manufacturing a word line layer above the second bit line layer, wherein the word line layer comprises a plurality of word lines which are arranged in parallel, the word lines wrap the middle parts of the first silicon pillars and the second silicon pillars, and each first silicon pillar is connected with one first capacitor;
manufacturing a first bit line layer above the word line layer, wherein the first bit line layer comprises a plurality of first bit lines arranged in parallel, and each first bit line is connected with a second doping region of one first silicon column;
and manufacturing a second capacitor layer above the first bit line layer, wherein the second capacitor layer comprises a plurality of second capacitors, and each second capacitor is connected with one second silicon pillar.
In an exemplary embodiment of the present disclosure, the second bit line wraps around at least a portion of the second doped region of the second silicon pillar.
In an exemplary embodiment of the present disclosure, an upper surface of the second bit line is connected to the second doping region of the second silicon pillar.
In an exemplary embodiment of the present disclosure, further comprising:
and manufacturing a first middle layer above the second word line layer, wherein the first middle layer wraps at least part of the first doped region of the first silicon column and at least part of the second doped region of the second silicon column.
In an exemplary embodiment of the present disclosure, the first bit line wraps around at least a portion of the second doped region of the first silicon pillar.
In an exemplary embodiment of the present disclosure, a lower surface of the first bit line is connected to the second doping region of the first silicon pillar.
In an exemplary embodiment of the present disclosure, further comprising:
and manufacturing a second intermediate layer above the word line layer, wherein the second intermediate layer wraps at least part of the first doped region of the second silicon column and at least part of the second doped region of the first silicon column.
In an exemplary embodiment of the present disclosure, an insulating layer is present between the word line and the first and second silicon pillars.
In one exemplary embodiment of the present disclosure, the first silicon pillar and the second silicon pillar are arranged in m rows and n columns in the same layer,
the first silicon pillars are divided into a first group and a second group, and the second silicon pillars are divided into a third group and a fourth group, wherein,
the first silicon pillars are positioned in odd rows and the second silicon pillars are positioned in even rows, the first silicon pillars of the first group are positioned in odd columns of the odd rows, and the first silicon pillars of the second group are positioned in even columns of the adjacent odd rows; the second silicon pillars of the third group are all positioned in even-numbered rows and even-numbered columns, and the second silicon pillars of the fourth group are all positioned in odd-numbered columns of adjacent even-numbered rows;
or the first silicon pillars are positioned in even rows and the second silicon pillars are positioned in odd rows, the first silicon pillars of the first group are positioned in even rows and even columns, and the first silicon pillars of the second group are positioned in odd columns of adjacent even rows; the second silicon columns of the third group are all positioned in odd-numbered columns of the odd-numbered rows, and the second silicon columns of the fourth group are all positioned in even-numbered columns of the adjacent odd-numbered rows.
The embodiment of the disclosure can effectively improve the density of the storage units in a unit area by arranging the five-layer structure comprising two storage units above the logic circuit layer, and effectively overcome the difficulty of improving the density of elements in the prior art.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.
Fig. 1 is a schematic structural diagram of a semiconductor structure in an exemplary embodiment of the present disclosure.
Fig. 2 is a flow chart of a method of fabricating the semiconductor structure shown in fig. 1.
Fig. 3 is a process diagram of the manufacturing method corresponding to steps S1 and S2.
Fig. 4A to 4C are process diagrams of the manufacturing method corresponding to step S3.
Fig. 5A and 5B are process diagrams of the manufacturing method corresponding to step S4.
Fig. 6A to 6C are process diagrams of the manufacturing method corresponding to step S5.
Fig. 7A to 7C are process diagrams of the manufacturing method corresponding to step S6.
Fig. 8A to 8C are process diagrams of the manufacturing method corresponding to step S7.
Fig. 9 is a schematic diagram of a semiconductor structure 900 provided in another embodiment of the present disclosure.
Fig. 10A to 10E are schematic views of a method of manufacturing the semiconductor structure 900.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the subject matter of the present disclosure can be practiced without one or more of the specific details, or with other methods, components, devices, steps, and the like. In other instances, well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.
Further, the drawings are merely schematic illustrations of the present disclosure, in which the same reference numerals denote the same or similar parts, and thus, a repetitive description thereof will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in the form of software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor devices and/or microcontroller devices.
The following detailed description of exemplary embodiments of the disclosure refers to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a semiconductor structure in an exemplary embodiment of the present disclosure.
Referring to fig. 1, a semiconductor structure 100 may include, from a cross-sectional view:
a substrate 1, a logic circuit formed on the substrate 1, the logic circuit including a plurality of logic elements 11;
a first capacitor layer 2, located above the substrate 1, comprising a plurality of first capacitors 21;
the second bit line layer 3 is positioned above the first capacitor layer 2 and comprises a plurality of second bit lines 31 arranged in parallel;
a word line layer 4, which is located above the second bit line layer 3 and includes a plurality of word lines 41 arranged in parallel;
a first bit line layer 5, which is located above the word line layer 4 and includes a plurality of first bit lines 51 arranged in parallel, wherein the projections of the first bit lines 51 and the second bit lines 31 are parallel;
a second capacitor layer 6, which is located above the first bit line layer 5 and includes a plurality of second capacitors 61;
a plurality of first silicon pillars a and a plurality of second silicon pillars B perpendicular to the second bit line layer 3, the word line layer 4, the first bit line layer 4, wherein:
the first doped region of each first silicon pillar A is electrically connected with a first capacitor 21 and the second doped region is electrically connected with a first bit line 51;
the first doped region of each second silicon pillar B is electrically connected with a second capacitor 61 and the second doped region is electrically connected with a second bit line 31;
the plurality of word lines wrap the middle of the first silicon pillar A and/or the second silicon pillar B.
Fig. 2 is a flow chart of a method of fabricating the semiconductor structure shown in fig. 1.
Referring to fig. 2, the manufacturing method 200 may include:
step S1, providing a substrate on which a logic circuit is formed, the logic circuit including a plurality of logic elements;
step S2, manufacturing a first capacitor layer above the substrate, wherein the first capacitor layer comprises a plurality of first capacitors, and the position of each first capacitor corresponds to the position of one first silicon pillar;
step S3, manufacturing a second bit line layer above the first capacitor layer, wherein the second bit line layer comprises a plurality of second bit lines arranged in parallel, and each second bit line is connected with a second doping region of a second silicon pillar;
step S4, a word line layer is manufactured above the second bit line layer, the word line layer comprises a plurality of word lines which are arranged in parallel, the word lines wrap the middle parts of the first silicon pillars and the second silicon pillars, and each first silicon pillar is connected with a first capacitor;
step S5, manufacturing a first bit line layer above the word line layer, wherein the first bit line layer comprises a plurality of first bit lines arranged in parallel, and each first bit line is connected with a second doped region of a first silicon pillar;
step S6, a second capacitor layer is formed over the first bit line layer, the second capacitor layer including a plurality of second capacitors, each second capacitor being connected to a second silicon pillar.
Fig. 3 to 8 are process diagrams of the manufacturing method shown in fig. 2.
Fig. 3 is a schematic diagram corresponding to step S1.
Referring to fig. 3, in the embodiment of the present disclosure, a substrate 1 is provided first, an insulating layer is formed on a surface of the substrate 1, and a logic circuit is disposed over the insulating layer, and the logic circuit includes a plurality of logic elements 11. In other embodiments, the logic circuit may be formed directly on the substrate surface without forming an insulating layer, and the substrate may be silicon, germanium, silicon-on-insulator, or the like. The present disclosure is not limited thereto.
The logic circuit may be formed by first fabricating a plurality of logic elements 11 on the surface of the insulating layer, connecting the logic elements 11 to a plurality of word lines and bit lines fabricated in the following processes for controlling reading and writing of a plurality of memory cells, and then depositing a medium on and around the logic elements 11 to wrap the plurality of logic elements 11.
Fig. 4A to 4C are process diagrams of the manufacturing method corresponding to step S2.
Before the first capacitor is manufactured, the position of the first capacitor needs to be located first. The disclosed embodiments arrange the memory cells (including transistors and corresponding capacitors) in an inverted configuration to increase the storage density. Therefore, it is necessary to properly arrange the different storage units to avoid the collision of the storage units arranged upside down on a certain layer. For simplicity of explanation, the relative positions of two memory cells with the capacitor position above and the capacitor position below will be explained below, with only the position of the silicon pillar of the transistor in the memory cell being representative of the transistor position.
In one embodiment, a first silicon pillar a (corresponding to the memory cell with the capacitor located below in fig. 1) and a second silicon pillar B (corresponding to the memory cell with the capacitor located above in fig. 1) may be disposed in the same layer in an array arrangement to avoid interference. However, in the embodiments of the present disclosure, in order to further increase the arrangement density of the memory cells, the first silicon pillars and the second silicon pillars are arranged in a staggered manner to provide a higher arrangement density and avoid the distance between the memory cells from being too small. It is to be understood that the pitch of the silicon pillars in the drawings of the present disclosure is relatively large for easy reference, and the pitch between the silicon pillars may be relatively small in the actual manufacturing process, and the specific value may be determined by those skilled in the art according to the process requirements, which is not limited by the present disclosure.
Referring to fig. 4A, in the same layer (e.g., in a second bit line layer, a word line layer, a first bit line layer), first silicon pillars a and second silicon pillars B may be arranged in m rows and n columns, the first silicon pillars a being divided into a first group and a second group, the second silicon pillars B being divided into a third group and a fourth group, wherein,
the first silicon columns A are positioned in odd rows and the second silicon columns B are positioned in even rows, the first silicon columns A of the first group are positioned in odd columns of the odd rows, and the first silicon columns A of the second group are positioned in even columns of the adjacent odd rows; the second silicon columns B of the third group are all positioned in even columns of even rows, and the second silicon columns B of the fourth group are all positioned in odd columns of adjacent even rows;
or the first silicon columns A are positioned in even rows and the second silicon columns B are positioned in odd rows, the first silicon columns A of the first group are positioned in even columns of the even rows, and the first silicon columns A of the second group are positioned in odd columns of the adjacent even rows; the second silicon pillars B of the third group are all positioned in odd columns of the odd rows, and the second silicon pillars B of the fourth group are all positioned in even columns of the adjacent odd rows.
Specifically, three first silicon pillars a or three second silicon pillars B adjacent to each other in the row position and also adjacent to each other in the column position are arranged in a triangular shape, one second silicon pillar B is present in a triangular region formed by the three first silicon pillars a adjacent to each other in the row position, and one first silicon pillar a is present in a triangular region formed by the three second silicon pillars B adjacent to each other in the column position, that is, two triangles can be regarded as being intersected with each other.
The row spacing between the silicon pillars may be equal or unequal, the column spacing may be equal or unequal, and the row spacing and the column spacing may be equal or unequal when the row spacing is equal or the column spacing is equal. In addition, in an embodiment, it is also possible to arrange that the triangle formed by the three adjacent rows and columns of the first silicon pillars a is an equilateral triangle, and the triangle formed by the three adjacent rows and columns of the second silicon pillars B is an equilateral triangle, which is not limited by the present disclosure.
Referring to fig. 4B, a conductive layer may first be deposited on the substrate 1 as the plates of the plurality of first capacitors 21. In some embodiments, the conductive layer may be, for example, polysilicon, silicon germanium, tungsten, TiN, or the like. Next, an inter-capacitor dielectric layer, which may be a high-k material, may be deposited on the conductive layer, and then a conductive layer may be formed over the inter-capacitor dielectric layer as another plate of the plurality of first capacitors. The specific form of the first capacitor 21 is not limited in this disclosure, and may be a cup type or a column type commonly used in DRAM chips, and can be determined by those skilled in the art according to the process and performance requirements, and the disclosure is not limited thereto.
Fig. 4C is a schematic top view of the first capacitor layer 2 after the fabrication. The labeling of the location of the first capacitor 21 in fig. 4C is for illustration only.
Fig. 5A and 5B are process diagrams of the manufacturing method corresponding to step S3.
It is understood that the second bit line 31 in the second bit line layer 3 is used to control the memory cell where the second capacitor 61 in fig. 1 is located, i.e. the second bit line 31 corresponds to the second capacitor 61 and the second silicon pillar B.
Referring to fig. 5A, a dielectric may be first deposited on the first capacitance layer 2, and then a recess may be etched at a position corresponding to the second bit line 31 and filled to fabricate a second bit line.
In an embodiment of the present disclosure, the second bit line 31 wraps the second doped region of the second silicon pillar B, and at this time, a hole may be drilled and a heavily doped silicon material (for example, N + -type silicon) may be filled in a position of the second bit line 31 corresponding to the second silicon pillar B to form the second doped region of the second silicon pillar B. Finally, through holes with the bottoms connected with the first capacitor 21 can be etched in the dielectric region at positions corresponding to the first silicon pillars a, and the through holes are filled with heavily doped silicon material to form first doped regions of the first silicon pillars a.
Referring to fig. 5B, after the second bit line layer 3 is fabricated, the second bit lines 31 are connected to only the second silicon pillars B as seen from the top view.
Fig. 6A to 6C are process diagrams of the manufacturing method corresponding to step S4.
Referring to fig. 6A, in fabricating word line layer 4, a dielectric layer may be first deposited, and grooves may be etched on the dielectric layer at positions corresponding to word lines 41, and then the grooves may be filled with metal to form a plurality of word lines 41. Next, holes are formed in the word line 41 at positions corresponding to the first silicon pillar a and the second silicon pillar B, the holes being through holes, and the bottom portions of the holes being connected to the first silicon pillar a and the second silicon pillar B in the second bit line layer 3. It is understood that since the word line is connected to the gate of the transistor, an insulating layer is present between the word line 41 and both the first and second silicon pillars a and B as a gate insulating layer. In some embodiments, the gate insulating layer is, for example, silicon dioxide.
When the gate insulating layer is silicon dioxide, a silicon dioxide deposition process may be performed on an inner surface of the via hole on the word line 41 to form the gate insulating layer. Then, silicon material is deposited in the through holes to serve as a channel region of the transistor. For the silicon pillar as a whole, the word line wraps the middle of the first silicon pillar A and the second silicon pillar B.
In one embodiment of the present disclosure, one word line connects only the first silicon pillar a and the second silicon pillar B located in the same column, as shown in fig. 6B. In this case, the word line 41 is a straight line, and the process is simple and the control efficiency is high.
In another embodiment of the present disclosure, one word line may also simultaneously connect the first silicon pillar a and the second silicon pillar B of two adjacent columns as the process conditions allow, as shown in fig. 6C. In this case, the word line 41 is, for example, a curved line. The number of the memory units controlled by one word line can be greatly increased in the same area by connecting two memory units simultaneously, and the space between the word lines is enlarged.
It is understood that there may be an insulating material between second bit line layer 3 and word line layer 4 for isolation, and this disclosure is not limited thereto.
Fig. 7A to 7C are process diagrams of the manufacturing method corresponding to step S5.
It will be appreciated that the first bit line 51 in the first bit line layer 5 is used to control the memory cell in which the first capacitor is located in fig. 1, i.e. the first bit line 51 corresponds to the first capacitor 21, the first silicon pillar a.
Referring to fig. 7A, a process of manufacturing the first bit line layer 5 is similar to a process of manufacturing the second bit line layer 3. First a dielectric needs to be deposited to form a dielectric region, and then a recess is etched and filled in the dielectric region at a position corresponding to the first bit line 51 to fabricate the first bit line 51.
In one embodiment, the first bit line 51 wraps the second doped region of the first silicon pillar a, and at this time, a hole may be drilled and filled with a heavily doped silicon material (e.g., N + type silicon) at a position corresponding to the first bit line a to form the second doped region of the first silicon pillar a. Finally, through holes can be etched in the dielectric region at positions corresponding to the second silicon pillars B, and the through holes are filled with heavily doped silicon material to form first doped regions of the second silicon pillars B.
It is understood that there may be an insulating substance between the first bit line layer 5 and the word line layer 4 for isolation, and this disclosure is not limited thereto.
In other embodiments of the present disclosure, the upper portion, the middle portion, and the lower portion of the first silicon pillar a and the second silicon pillar B may also be formed in one step, for example, after the second bit line layer 3, the word line layer 4, and the first bit line layer 5 are manufactured, the corresponding positions of the first silicon pillar a and the second silicon pillar B are punched and filled to form the silicon pillars, which is not limited by the present disclosure, and a person skilled in the art may select a specific process according to the process.
Referring to fig. 7B, after the first bit line layer 5 is fabricated, the first bit lines 51 are connected to only the silicon pillars located in the same column when viewed from the top. For ease of understanding, the positions of the second bit lines 31, word lines 41 are shown in the figures. The word lines are straight lines in fig. 7B and curved lines in fig. 7C (details correspond to the description of fig. 6C).
Fig. 8A to 8C are process diagrams of the manufacturing method corresponding to step S6.
Referring to fig. 8A, a metal layer may first be deposited on the first bit line layer 5 to fabricate the lower plate of the second capacitor 61. Next, a dielectric layer is deposited on the metal layer, and a groove is etched in the dielectric layer at a position corresponding to the second capacitor 61, so as to fill the dielectric layer of the second capacitor 61. Finally, a metal layer is deposited on the dielectric layer to fabricate the top plate of the second capacitor 61.
It is understood that the planarization process is necessary in the manufacturing process of the above layers, and the disclosure is not repeated herein.
In the embodiments shown in fig. 5A and 7A, the manner of connecting the second bit line 31 to the second doped region of the second silicon pillar B and the manner of connecting the first bit line 51 to the second doped region of the first silicon pillar a are both wrapped, and in another embodiment of the present disclosure, the manner of connecting the second bit line 31 to the second doped region of the second silicon pillar B and the manner of connecting the first bit line 51 to the second doped region of the first silicon pillar a may also be surface-connected. At this time, it is necessary to provide an intermediate layer capable of accommodating the second doped region of the first silicon pillar a and the second doped region of the second silicon pillar B on the upper and lower surfaces of the word line layer 4.
Fig. 9 is a schematic diagram of a semiconductor structure 900 provided in another embodiment of the present disclosure.
In an embodiment, the manner in which the second bit line 31 is connected to the second doped region of the second silicon pillar B and the manner in which the first bit line 51 is connected to the second doped region of the first silicon pillar a may be surface-connected, and for simplifying the description, only the manner in which the second bit line 31 is connected to the second doped region of the second silicon pillar B and the manner in which the first bit line 51 is connected to the second doped region of the first silicon pillar a are shown in surface-connected drawings.
Referring to fig. 9, when the second bit line 31 is connected to the second doped region of the second silicon pillar B, and the first bit line 51 is connected to the second doped region of the first silicon pillar a, both of them have their surfaces connected to each other, a first intermediate layer 7 may be disposed between the second bit line layer 3 and the word line layer 4, and the first intermediate layer wraps the first doped region of the first silicon pillar a and the second doped region of the second silicon pillar B; the middle of the first bit line layer 5 and the word line layer 4 further includes a second middle layer 8 wrapping the first doped region of the second silicon pillar B and the second doped region of the first silicon pillar a.
Correspondingly, the manufacturing method also comprises the manufacture of the first intermediate layer 7 and the second intermediate layer 8.
Fig. 10A to 10E are schematic views of a method of manufacturing the semiconductor structure 900.
Since the process before the second bit line layer 3 is manufactured is the same as the process of manufacturing the semiconductor structure 900, the description will not be repeated in this disclosure.
Referring to fig. 10A, different from the process shown in fig. 5A, when the second bit line layer 3 is manufactured, after the plurality of second bit lines 31 and the first doped regions of the first silicon pillars a are manufactured through the etching and filling processes, the second bit lines 31 do not need to be punched, and only the surface planarization process is applied to planarize the upper surface of the second bit line layer 3.
Referring to fig. 10B, a dielectric layer 71 may be deposited on the second bit line layer 3, and grooves may be etched in the dielectric layer 71 at positions corresponding to the first silicon pillar a and the second silicon pillar B, and after the grooves are filled with a heavily doped silicon material, a portion of the first doped region of the first silicon pillar a and the second doped region of the second silicon pillar B are simultaneously formed, and after a surface planarization process is performed, the first intermediate layer 7 is formed.
Referring to fig. 10C, the method of fabricating the word line layer 4 on the first interlayer 7 is the same as that shown in fig. 6A to 6C, and the disclosure is not repeated here.
Referring to fig. 10D, when the second interlayer 8 is manufactured, a dielectric layer 81 may be deposited on the word line layer 4, and grooves may be etched in the dielectric layer 81 at positions corresponding to the first silicon pillar a and the second silicon pillar B, and after the grooves are filled with a heavily doped silicon material, the second doped region of the first silicon pillar a and a portion of the first doped region of the second silicon pillar B are simultaneously manufactured, and after a surface planarization process is performed, the second interlayer 8 is formed.
Referring to fig. 10E, finally, the first bit line layer 5 is fabricated on the second interlayer 8 in the same manner as shown in fig. 7A to 7C, and the disclosure is not repeated here.
It is understood that the upper, middle and lower portions of the first and second silicon pillars a and B may be formed in one step, which is not limited by the disclosure, and a person skilled in the art may select a specific process according to the process.
In summary, in the embodiment of the present disclosure, five layers of structures are disposed above the logic circuit layer, and two types of memory cells with capacitors above and below are accommodated, so that the element density of the memory cells can be greatly increased, the memory capacity is further increased, and the bottleneck of the element density in the prior art is effectively overcome.
It should be noted that although in the above detailed description several modules or units of the device for action execution are mentioned, such a division is not mandatory. Indeed, the features and functionality of two or more modules or units described above may be embodied in one module or unit, according to embodiments of the present disclosure. Conversely, the features and functions of one module or unit described above may be further divided into embodiments by a plurality of modules or units.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims (18)

1. A semiconductor structure, comprising:
a substrate on which a logic circuit is formed, the logic circuit including a plurality of logic elements;
a first capacitor layer located above the substrate and including a plurality of first capacitors;
the second bit line layer is positioned above the first capacitor layer and comprises a plurality of second bit lines arranged in parallel;
the word line layer is positioned above the second bit line layer and comprises a plurality of word lines arranged in parallel;
the first bit line layer is positioned above the word line layer and comprises a plurality of first bit lines arranged in parallel;
a second capacitor layer located above the first bit line layer and including a plurality of second capacitors;
a plurality of first silicon pillars and a plurality of second silicon pillars perpendicular to the second bit line layer, the word line layer, the first bit line layer, wherein:
the first doped region of each first silicon pillar is electrically connected with one first capacitor and the second doped region is electrically connected with one first bit line;
the first doped region of each second silicon pillar is electrically connected with one second capacitor and the second doped region is electrically connected with one second bit line;
the plurality of word lines wrap the middle of the first silicon pillar and/or the second silicon pillar.
2. The semiconductor structure of claim 1, wherein the second bit line wraps around at least a portion of the second doped region of the second silicon pillar.
3. The semiconductor structure of claim 1, wherein an upper surface of the second bitline connects to the second doped region of the second silicon pillar.
4. The semiconductor structure of claim 3, wherein the second bit line layer and the word line layer further comprise, intermediate:
a first intermediate layer wrapping at least a portion of the first doped region of the first silicon pillar and at least a portion of the second doped region of the second silicon pillar.
5. The semiconductor structure of claim 1, wherein the first bit line wraps around at least a portion of the second doped region of the first silicon pillar.
6. The semiconductor structure of claim 1, wherein a lower surface of the first bitline connects to the second doped region of the first silicon pillar.
7. The semiconductor structure of claim 6, wherein the middle of the first bit line layer and the word line layer further comprises:
and the second intermediate layer wraps at least part of the first doped region of the second silicon column and at least part of the second doped region of the first silicon column.
8. The semiconductor structure of claim 1, wherein an insulating layer is present between the word line and both the first and second silicon pillars.
9. The semiconductor structure of claim 1, wherein said first silicon pillars and said second silicon pillars are arranged in m rows and n columns in the same layer, said first silicon pillars are divided into a first group and a second group, and said second silicon pillars are divided into a third group and a fourth group, wherein,
the first silicon pillars are positioned in odd rows and the second silicon pillars are positioned in even rows, the first silicon pillars of the first group are positioned in odd columns of the odd rows, and the first silicon pillars of the second group are positioned in even columns of the adjacent odd rows; the second silicon pillars of the third group are all positioned in even-numbered rows and even-numbered columns, and the second silicon pillars of the fourth group are all positioned in odd-numbered columns of adjacent even-numbered rows;
or the first silicon pillars are positioned in even rows and the second silicon pillars are positioned in odd rows, the first silicon pillars of the first group are positioned in even rows and even columns, and the first silicon pillars of the second group are positioned in odd columns of adjacent even rows; the second silicon columns of the third group are all positioned in odd-numbered columns of the odd-numbered rows, and the second silicon columns of the fourth group are all positioned in even-numbered columns of the adjacent odd-numbered rows.
10. A method of fabricating a semiconductor structure, comprising:
providing a substrate, wherein a logic circuit is formed on the substrate and comprises a plurality of logic elements;
manufacturing a first capacitor layer above the substrate, wherein the first capacitor layer comprises a plurality of first capacitors, and the position of each first capacitor corresponds to the position of one first silicon pillar;
manufacturing a second bit line layer above the first capacitor layer, wherein the second bit line layer comprises a plurality of second bit lines arranged in parallel, and each second bit line is connected with a second doping region of a second silicon column;
manufacturing a word line layer above the second bit line layer, wherein the word line layer comprises a plurality of word lines which are arranged in parallel, the word lines wrap the middle parts of the first silicon pillars and the second silicon pillars, and each first silicon pillar is connected with one first capacitor;
manufacturing a first bit line layer above the word line layer, wherein the first bit line layer comprises a plurality of first bit lines arranged in parallel, and each first bit line is connected with a second doping region of one first silicon column;
and manufacturing a second capacitor layer above the first bit line layer, wherein the second capacitor layer comprises a plurality of second capacitors, and each second capacitor is connected with one second silicon pillar.
11. The method of claim 10, wherein the second bit line wraps around at least a portion of the second doped region of the second silicon pillar.
12. The method of claim 10, wherein an upper surface of the second bitline is connected to the second doped region of the second silicon pillar.
13. The method of manufacturing of claim 12, further comprising:
and manufacturing a first middle layer above the second word line layer, wherein the first middle layer wraps at least part of the first doped region of the first silicon column and at least part of the second doped region of the second silicon column.
14. The method of claim 10, wherein the first bit line wraps around at least a portion of the second doped region of the first silicon pillar.
15. The method of claim 10, wherein a lower surface of the first bitline is connected to the second doped region of the first silicon pillar.
16. The method of manufacturing of claim 15, further comprising:
and manufacturing a second intermediate layer above the word line layer, wherein the second intermediate layer wraps at least part of the first doped region of the second silicon column and at least part of the second doped region of the first silicon column.
17. The method of claim 10, wherein an insulating layer is present between the word line and the first and second silicon pillars.
18. The method of claim 10, wherein the first silicon pillars and the second silicon pillars are arranged in m rows and n columns in the same layer,
the first silicon pillars are divided into a first group and a second group, and the second silicon pillars are divided into a third group and a fourth group, wherein,
the first silicon pillars are positioned in odd rows and the second silicon pillars are positioned in even rows, the first silicon pillars of the first group are positioned in odd columns of the odd rows, and the first silicon pillars of the second group are positioned in even columns of the adjacent odd rows; the second silicon pillars of the third group are all positioned in even-numbered rows and even-numbered columns, and the second silicon pillars of the fourth group are all positioned in odd-numbered columns of adjacent even-numbered rows;
or the first silicon pillars are positioned in even rows and the second silicon pillars are positioned in odd rows, the first silicon pillars of the first group are positioned in even rows and even columns, and the first silicon pillars of the second group are positioned in odd columns of adjacent even rows; the second silicon columns of the third group are all positioned in odd-numbered columns of the odd-numbered rows, and the second silicon columns of the fourth group are all positioned in even-numbered columns of the adjacent odd-numbered rows.
CN201911205669.3A 2019-11-29 2019-11-29 Semiconductor structure and manufacturing method thereof Pending CN112885832A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023065546A1 (en) * 2021-10-18 2023-04-27 长鑫存储技术有限公司 Storage device and preparation method therefor

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5571730A (en) * 1993-11-24 1996-11-05 Samsung Electronics Co., Ltd. Semiconductor device having vertical metal oxide semiconductors and a method for manufacturing the same
CN1213834A (en) * 1997-09-29 1999-04-14 西门子公司 High density semiconductor memory having diagonal bit lines and dual word lines
US5929477A (en) * 1997-01-22 1999-07-27 International Business Machines Corporation Self-aligned diffused source vertical transistors with stack capacitors in a 4F-square memory cell array
US6150687A (en) * 1997-07-08 2000-11-21 Micron Technology, Inc. Memory cell having a vertical transistor with buried source/drain and dual gates
US20050199932A1 (en) * 2004-03-11 2005-09-15 Abbott Todd R. Semiconductor constructions, and methods of forming semiconductor structures
US20070284623A1 (en) * 2006-05-24 2007-12-13 Sang-Jin Kim Semiconductor device having vertical channel transistor
CN102201410A (en) * 2010-03-26 2011-09-28 尔必达存储器株式会社 Semiconductor device
US20130161710A1 (en) * 2011-12-27 2013-06-27 Yun-Hyuck Ji Semiconductor device having buried bit line and method for fabricating the same
US20130334583A1 (en) * 2012-06-13 2013-12-19 SK Hynix Inc. Semiconductor devices including vertical transistors, electronic systems including the same and methods of manufacturing the same
CN107104104A (en) * 2016-02-22 2017-08-29 三星电子株式会社 Semiconductor devices and its manufacture method
CN107579087A (en) * 2016-07-04 2018-01-12 中芯国际集成电路制造(上海)有限公司 A kind of memory cell array structure and electronic installation
US10283565B1 (en) * 2017-12-21 2019-05-07 International Business Machines Corporation Resistive memory with a plurality of resistive random access memory cells each comprising a transistor and a resistive element
CN210640252U (en) * 2019-11-29 2020-05-29 长鑫存储技术有限公司 Semiconductor structure

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5571730A (en) * 1993-11-24 1996-11-05 Samsung Electronics Co., Ltd. Semiconductor device having vertical metal oxide semiconductors and a method for manufacturing the same
US5929477A (en) * 1997-01-22 1999-07-27 International Business Machines Corporation Self-aligned diffused source vertical transistors with stack capacitors in a 4F-square memory cell array
US6150687A (en) * 1997-07-08 2000-11-21 Micron Technology, Inc. Memory cell having a vertical transistor with buried source/drain and dual gates
CN1213834A (en) * 1997-09-29 1999-04-14 西门子公司 High density semiconductor memory having diagonal bit lines and dual word lines
US20050199932A1 (en) * 2004-03-11 2005-09-15 Abbott Todd R. Semiconductor constructions, and methods of forming semiconductor structures
US20070284623A1 (en) * 2006-05-24 2007-12-13 Sang-Jin Kim Semiconductor device having vertical channel transistor
CN102201410A (en) * 2010-03-26 2011-09-28 尔必达存储器株式会社 Semiconductor device
US20130161710A1 (en) * 2011-12-27 2013-06-27 Yun-Hyuck Ji Semiconductor device having buried bit line and method for fabricating the same
US20130334583A1 (en) * 2012-06-13 2013-12-19 SK Hynix Inc. Semiconductor devices including vertical transistors, electronic systems including the same and methods of manufacturing the same
CN107104104A (en) * 2016-02-22 2017-08-29 三星电子株式会社 Semiconductor devices and its manufacture method
CN107579087A (en) * 2016-07-04 2018-01-12 中芯国际集成电路制造(上海)有限公司 A kind of memory cell array structure and electronic installation
US10283565B1 (en) * 2017-12-21 2019-05-07 International Business Machines Corporation Resistive memory with a plurality of resistive random access memory cells each comprising a transistor and a resistive element
CN210640252U (en) * 2019-11-29 2020-05-29 长鑫存储技术有限公司 Semiconductor structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023065546A1 (en) * 2021-10-18 2023-04-27 长鑫存储技术有限公司 Storage device and preparation method therefor

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