CN112885813A - Monitoring structure of contact hole chain resistance of field effect transistor - Google Patents
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Abstract
The invention discloses a monitoring structure of contact hole chain resistance of a field effect transistor, wherein a partial region is added in an N + hole chain, especially P + injection is added in a hole contact region, the monitoring structure is compatible with the original hole chain structure, the structure is simple to realize, the comparison of monitoring results is obvious, and if the hole chain resistance of a novel structure is smaller and the P + hole chain resistance is normal, an abnormal process can be easily positioned. The PN junction hole chain structure can reflect the fluctuation of the technological process better in the same technological process, and can reflect the change of the technological process more sensitively relative to the N + hole chain and P + hole chain structures, thereby truly reflecting the change trend of the on-resistance among product batches.
Description
Technical Field
The invention belongs to the technical field of transistors, and particularly relates to a monitoring structure of contact hole chain resistance of a field effect transistor.
Background
In order to reflect the stable condition of the chip technological process, a process monitoring graph is added during the manufacture of a photoetching plate, and the change direction or failure of the electrical parameters of the device is predicted in advance. The addition of a process monitoring graph is indispensable in the wafer production process, the ohmic hole chain structure is directly reflected by the contact resistance and the ohmic hole etching process, and the ohmic hole resistance directly reflects the change of the contact hole resistance.
Generally, the ohmic pore chain structure mainly comprises an N-type pore chain structure and a P-type pore chain structure, and the N-type pore chain structure and the P-type pore chain structure are respectively used for monitoring ohmic contact of an N-type pore and a P-type pore. However, for a VDMOS product, the structure is special, and in the case of an N-type VDMOS, the device is configured such that the source lead-out hole includes a P + body lead-out contact resistance, a P + body ohmic contact resistance, an N + source contact resistance, and an N + source ohmic contact resistance. In the process, only monitoring an N-type hole chain structure and a P-type hole chain structure is far from enough, because the contact resistance of an N + source ohmic hole in the device structure comprises two factors, one of which is the contact resistance after the ohmic hole is etched; the other is caused by the contact concentration change of the ohmic hole after the contact resistance is neutralized by the silicon of the contact hole as the N + source ohmic contact resistance and the P + body.
The phenomenon is more prominent to be reflected in a P-type device, a conventional hole chain monitoring structure is adopted in the initial stage of development of a P-type VDMOS product, the monitoring data of the process is consistent with the historical batch, but the actual on-resistance of the product has obvious dispersion and large variation, even out of tolerance.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides a monitoring structure of the contact hole chain resistance of a field effect transistor, which can truly reflect the change trend of the on-resistance among product batches.
In order to solve the technical problems, the invention is realized by the following technical scheme:
a monitoring structure of contact hole chain resistance of a field effect transistor comprises an N well formed on a P-type epitaxial layer, wherein the upper end surface of the N well is covered with a passivation layer;
n N + body regions are formed in the N well, each N + body region is arranged at intervals, the depth of each N + body region is the same, and N is a positive integer not less than 2;
a P + source region is formed in the middle of each N + body region, the depth of each P + source region is the same, and each P + source region does not completely cover the corresponding N + body region;
two contact holes penetrating through the passivation layer are formed above each N + body region, and each contact hole is overlapped with the P + source region corresponding to the N + body region;
two contact holes in each N + body region are conducted through an N + body region, one contact hole in the 1 st N + body region is used as a leading-out end through metal, the other contact hole in the 1 st N + body region is conducted with one contact hole in the 2 nd N + body region through metal, the other contact hole in the 2 nd N + body region is conducted with one contact hole in the 3 rd N + body region through metal, and so on, the other contact hole in the N-1 th N + body region is conducted with one contact hole in the N + body region through metal, and the other contact hole in the N + body region is used as a leading-out end through metal.
Further, the doping impurity in each N + body region is phosphorus, and the doping impurity in each P + source region is boron.
Furthermore, the junction depth of each N + body region is 1-1.5 μm, and the junction depth of each P + source region is 0.1-0.5 μm.
A monitoring structure of contact hole chain resistance of a field effect transistor comprises a P well formed on an N-type epitaxial layer, wherein the upper end surface of the P well is covered with a passivation layer;
n P + body regions are formed in the P well, each P + body region is arranged at intervals, the depth of each P + body region is the same, and n is a positive integer not less than 2;
an N + source region is formed in the middle of each P + body region, the depth of each N + source region is the same, and each N + source region does not completely cover the corresponding P + body region;
two contact holes penetrating through the passivation layer are formed above each P + body region, and each contact hole is overlapped with the N + source region corresponding to the P + body region;
two contact holes on each P + body region are conducted through a P + body region, one contact hole on the 1 st P + body region is used as a leading-out end through metal, the other contact hole on the 1 st P + body region is conducted with one contact hole on the 2 nd P + body region through metal, the other contact hole on the 2 nd P + body region is conducted with one contact hole on the 3 rd P + body region through metal, and so on, the other contact hole on the n-1 st P + body region is conducted with one contact hole on the n P + body region through metal, and the other contact hole on the n P + body region is used as a leading-out end through metal.
Further, the doping impurity in each P + body region is boron, and the doping impurity in each N + source region is arsenic.
Furthermore, the junction depth of each P + body region is 1-1.5 μm, and the junction depth of each N + source region is 0.1-0.5 μm.
Compared with the prior art, the invention has at least the following beneficial effects: according to the monitoring structure of the contact hole chain resistance of the field effect transistor, a partial region is added in an N + hole chain, especially P + injection is added in a hole contact region, the monitoring structure is compatible with an original hole chain structure, the structure is simple to realize, the monitoring result is obvious in comparison, and if the hole chain resistance with a novel structure is smaller and the P + hole chain resistance is normal, an abnormal process can be easily positioned. The PN junction hole chain structure can reflect the fluctuation of the technological process better in the same technological process, and can reflect the change of the technological process more sensitively relative to the N + hole chain and P + hole chain structures, thereby truly reflecting the change trend of the on-resistance among product batches.
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a top view of a monitoring structure for contact hole chain resistance of a field effect transistor of the present invention;
FIG. 2 is a longitudinal cross-sectional view of FIG. 1;
fig. 3 to 15 are schematic diagrams illustrating the formation process of the monitoring structure of the contact hole chain resistance of the field effect transistor according to the present invention.
A 1-P type epitaxial layer; 101-N well; a 102-N + body region; 103-P + source region;
5-N type epitaxial layer; 501-P trap; 502-P + body region; 503-N + source region;
2-a passivation layer; 3-a contact hole; 4-a metal; 6-photoresist; 7-oxide layer.
Detailed Description
To make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The N-type hole chain and the P-type hole chain are normal through multi-party exclusion, and do not represent that the contact hole formed after the N + source ohmic contact resistance and the P + body leading-out contact resistance are neutralized is normal, and because the Schottky contact formed by the low concentration of the contact impurities cannot be monitored, a hole chain structure capable of reflecting the PN junction contact is required to be set, is consistent with the actual structure of a product, reflects the change condition of the contact resistance of the product more truly, finds problems in advance, reduces the research and development period and has less walking.
As an embodiment of the present invention, referring to fig. 1 and fig. 2, a monitoring structure for contact hole chain resistance of a field effect transistor includes an N well 101 formed on a P-type epitaxial layer 1, and an upper end surface of the N well 101 is covered with a passivation layer 2.
N + body regions 102 are formed in the N well 101, each N + body region 102 is arranged at intervals, the depth of each N + body region 102 is the same, and N is a positive integer not less than 2; specifically, in this embodiment, taking a P-type VDMOS as an example, a total of 50N + body regions 102 are formed.
A P + source region 103 is formed in the middle of each N + body region 102, the depth of each P + source region 103 is the same, and each P + source region 103 does not completely cover the corresponding N + body region 102.
Preferably, the doping impurity in each N + body region 102 is phosphorus, and the doping impurity in each P + source region 103 is boron; the junction depth of each N + body region 102 is 1-1.5 μm, and the junction depth of each P + source region 103 is 0.1-0.5 μm.
Two contact holes 3 penetrating the passivation layer 2 are formed above each N + body region 102, and each contact hole 3 is overlapped with the P + source region 103 corresponding to the N + body region 102.
Two contact holes 3 on each N + body region 102 are conducted through the N + body region 102, one contact hole 3 on the 1 st N + body region 102 is used as a leading-out terminal through a metal 4, the other contact hole 3 on the 1 st N + body region 102 is conducted with one contact hole 3 on the 2 nd N + body region 102 through a metal 4, the other contact hole 3 on the 2 nd N + body region 102 is conducted with one contact hole 3 on the 3 rd N + body region 102 through a metal 4, and the like, the other contact hole 3 on the 49 th N + body region 102 is conducted with one contact hole 3 on the 50 th N + body region 102 through a metal 4, and the other contact hole 3 on the 50 th N + body region 102 is used as a leading-out terminal through a metal 4.
Compared with the traditional structure, the structure of the invention is that one time of P + source injection is added on the basis of a P-type epitaxy and N + hole chain resistance structure in an N well, the P + source injection does not completely cover an N + body, the lower end of a contact hole is connected by the N + body, the contact hole is connected with the upper end of the contact hole by metal, and the preparation steps of the structure are as follows:
step 1, growing an implanted pad oxygen layer of 70nm on the surface of the P-type epitaxial layer;
step 3, after the well is re-expanded, photoetching is carried out to form an N + body injection window, and the injection energy and the dosage are set to be the same as the structure of the device;
step 5, forming a P + source injection window by photoetching, wherein the injection energy and the dosage are set to be the same as the structure of the device;
step 8, depositing metal;
and 9, photoetching and etching to form metal interconnection.
As an embodiment of the present invention, referring to fig. 1 and fig. 2, a monitoring structure for contact hole chain resistance of a field effect transistor includes a P-well 501 formed on an N-type epitaxial layer 5, and an upper end surface of the P-well 501 is covered with a passivation layer 2.
N P + body regions 502 are formed in the P well 501, each P + body region 502 is arranged at intervals, the depth of each P + body region 502 is the same, and n is a positive integer not less than 2; similarly, in this embodiment, a total of 50P + body regions 502 are formed.
An N + source region 503 is formed in the middle of each P + body region 502, the depth of each N + source region 503 is the same, and each N + source region 503 does not completely cover the corresponding P + body region 502.
Preferably, the doping impurity in each P + body region 502 is boron, and the doping impurity in each N + source region 503 is arsenic; the junction depth of each P + body region 502 is 1-1.5 μm, and the junction depth of each N + source region 503 is 0.1-0.5 μm.
Two contact holes 3 penetrating the passivation layer 2 are formed above each P + body region 502, and each contact hole 3 overlaps with the N + source region 503 corresponding to the P + body region 502.
Two contact holes 3 on each P + body region 502 are conducted through the P + body region 502, one contact hole 3 on the 1 st P + body region 502 is used as a leading-out terminal through metal 4, the other contact hole 3 on the 1 st P + body region 502 is conducted with one contact hole 3 on the 2 nd P + body region 502 through metal 4, the other contact hole 3 on the 2 nd P + body region 502 is conducted with one contact hole 3 on the 3 rd P + body region 502 through metal 4, and so on, the other contact hole 3 on the n-1 st P + body region 502 is conducted with one contact hole 3 on the nth P + body region 502 through metal 4, and the other contact hole 3 on the nth P + body region 502 is used as a leading-out terminal through metal 4.
Example 1:
the monitoring structure of the contact hole chain resistance of the field effect transistor is as follows:
on the P-type epitaxial layer, an N-well photoetching plate defines a well region, photoresist is adopted for masking and injection, and N-type impurities P are injected according to the product setting requirement; and (3) 50 pairs of N + holes with the diameter of 5.0 mu m multiplied by 4.0 mu m are arranged in the N well, the bottom of each hole is connected with an N + body, and the top of each hole is connected with a metal.
In the traditional hole chain structure, after an N + hole is formed, an ohmic hole with the size of 3.0 mu m multiplied by 2.0 mu m is opened in the N + hole and is led to a pressure point area by metal interconnection; the structure of the invention is that P + source injection is added in the N + hole region of the traditional structure to form a contact similar to the structure of a device, and the P + source injection and the hole are overlapped by 1.0 mu m.
Because the structure of the invention is consistent with the source contact structure of the P-type VDMOS product, the possible abnormity of the wafer in the process of process flow and the deviation situation of the on-resistance of the packaged product can be predicted by monitoring the change of the resistance value.
With reference to fig. 3 to 15, the structure of the present invention is specifically realized by the following method:
1. forming the resistivity and thickness required by the product through epitaxial deposition at the temperature of 1150 ℃;
2. growing a silicon dioxide layer with the thickness of 70nm on the surface of the P-type epitaxial layer by hydrogen-oxygen synthesis oxidation at the temperature of 900 ℃;
3. coating photoresist 6 with the thickness of 3.0 mu m on the surface of the oxide layer, and forming an N-well pattern through exposure and development;
4. doping the N-well by high-energy ion implantation, implanting impurities31P+Implant energy 400keV, implant dose 1.5E13cm-2；
5. By plasma etching and H2SO4+H2O2Removing the photoresist on the surface of the silicon wafer by using the solution;
6. forming an N well by annealing at 1100 ℃ for 40min and impurity redistribution;
7. coating photoresist with the thickness of 1.71 mu m on the surface of the oxide layer, and forming an N + body leading-out pattern through exposure and development;
8. doping the N + body by high-energy ion implantation, implanting impurities31P+Implant energy 120keV, implant dose 1.0E15cm-2；
9. By plasma etching and H2SO4+H2O2Removing the photoresist on the surface of the silicon wafer by using the solution;
10. oxidizing an oxide layer with the thickness of 80nm at 900 ℃, adding 60min at 1000 ℃, annealing, and redistributing impurities to form an N + hole;
11. coating photoresist with the thickness of 1.08 mu m on the surface of the oxide layer, and forming a P + source pattern through exposure and development;
12. doping P + source crystal item by high-energy ion implantation, implanting impurity11B+Implant energy 30keV, implant dose 1.5E15cm-2；
13. By plasma etching and H2SO4+H2O2Removing the photoresist on the surface of the silicon wafer by using the solution;
14. annealing at 900 ℃ for 20min, redistributing impurities and forming N + -P + contact, namely the N + body region is contacted with the P + source region.
Example 2:
the monitoring structure of the contact hole chain resistance of the field effect transistor can be popularized to an N-type VDMOS, and the monitoring structure is as follows:
on the N-type epitaxy, defining a well region by a P-well photoetching plate, adopting photoresist to mask and inject, and injecting a P-type impurity B according to the product setting requirement; and (3) a P + hole 50 pair of 5.0 micron multiplied by 4.0 micron is arranged in the P well, the hole is connected with the P + body at the bottom of the hole, and the hole is connected with the top of the hole by metal.
The traditional hole chain structure is that after a P + hole is formed, ohmic holes with the size of 3.0 mu m multiplied by 2.0 mu m are opened in the P + hole and are led to a pressure point area by metal interconnection; the structure of the invention is that N + source injection is added in the P + hole area of the traditional structure to form a contact similar to the structure of a device, and the N + source injection and the hole are overlapped by 1.0 mu m.
Because the structure is consistent with the source electrode contact structure of the N-type VDMOS product, the possible abnormity of the wafer in the process of process flow and the on-resistance deviation situation after the product is packaged are reflected by monitoring the change of the resistance value.
As shown in fig. 3 to 15, the present structure can be realized by the following method:
1. forming the resistivity and thickness required by the product through epitaxial deposition at the temperature of 1150 ℃;
2. growing a 70nm silicon dioxide layer on the surface of the N-type substrate silicon by hydrogen-oxygen synthesis oxidation at the temperature of 900 ℃;
3. coating photoresist with the thickness of 3.0 mu m on the surface of the oxide layer, and forming a P-well pattern through exposure and development;
4. doping the P-well by high-energy ion implantation, implanting impurities11B+Implantation energy 200keV, implantation dose 3.0E13cm-2；
5. By plasma etching and H2SO4+H2O2Removing the photoresist on the surface of the silicon wafer by using the solution;
6. annealing at 1100 ℃ for 40min and impurity redistribution to form a P well;
7. coating photoresist with the thickness of 1.38 mu m on the surface of the oxide layer, and forming a P + body leading-out pattern through exposure and development;
8. doping the P + body by high-energy ion implantation, implanting impurities11B+Implant energy 120keV, implant dose 1.0E15cm-2；
9. By plasma etching and H2SO4+H2O2Removing the photoresist on the surface of the silicon wafer by using the solution;
10. oxidizing a 90nm oxide layer at 900 ℃, adding 60min at 1000 ℃, annealing, and redistributing impurities to form an N + hole;
11. coating photoresist with the thickness of 1.08 mu m on the surface of the oxide layer, and forming an N + source pattern through exposure and development;
12. doping N + source crystal item by high-energy ion implantation, implanting impurity75As+Implant energy 120keV, implant dose 4.0E15cm-2；
13. By plasma etching and H2SO4+H2O2Removing the photoresist on the surface of the silicon wafer by using the solution;
14. annealing at 900 ℃ for 20min, redistributing the impurities and forming P + -N + contact.
Aiming at the problem that a monitoring graph cannot reflect the real condition of a product, the invention provides a monitoring structure of contact hole chain resistance of a field effect transistor, wherein the structure mainly reflects PN junction contact hole chain resistance and is mainly used for representing the resistance condition after N-type and P-type impurities are neutralized. The realization of this structure can satisfy the effective control of 6 inches power field effect transistor on-resistance change chip level, promotes the technological control level of military integrated circuit production line product, improves production line processing control ability. The invention can actually reflect the resistance change condition of the contact hole chain in the device structure by monitoring the hole chain resistance structure.
Finally, it should be noted that: the above-mentioned embodiments are only specific embodiments of the present invention, which are used for illustrating the technical solutions of the present invention and not for limiting the same, and the protection scope of the present invention is not limited thereto, although the present invention is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: any person skilled in the art can modify or easily conceive the technical solutions described in the foregoing embodiments or equivalent substitutes for some technical features within the technical scope of the present disclosure; such modifications, changes or substitutions do not depart from the spirit and scope of the embodiments of the present invention, and they should be construed as being included therein. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (6)
1. The monitoring structure of the contact hole chain resistance of the field effect transistor is characterized by comprising an N well (101) formed on a P-type epitaxial layer (1), wherein the upper end surface of the N well (101) is covered with a passivation layer (2);
n N + body regions (102) are formed in the N well (101), each N + body region (102) is arranged at intervals, the depth of each N + body region (102) is the same, and N is a positive integer not less than 2;
a P + source region (103) is formed in the middle of each N + body region (102), the depth of each P + source region (103) is the same, and each P + source region (103) does not completely cover the corresponding N + body region (102);
two contact holes (3) penetrating through the passivation layer (2) are formed above each N + body region (102), and each contact hole (3) is overlapped with the P + source region (103) corresponding to the N + body region (102);
two contact holes (3) on each N + body region (102) are conducted through an N + body region (102), one contact hole (3) on the 1 st N + body region (102) serves as a leading-out end through a metal (4), the other contact hole (3) on the 1 st N + body region (102) is conducted with one contact hole (3) on the 2 nd N + body region (102) through a metal (4), the other contact hole (3) on the 2 nd N + body region (102) is conducted with one contact hole (3) on the 3 rd N + body region (102) through a metal (4), and in the same way, the other contact hole (3) on the N-1 th N + body region (102) is conducted with one contact hole (3) on the nth N + body region (102) through metal (4), and the other contact hole (3) on the nth N + body region (102) is used as a leading-out terminal through the metal (4).
2. The monitoring structure of contact hole chain resistance of a field effect transistor according to claim 1, characterized in that the doping impurity in each N + body region (102) is phosphorus and the doping impurity in each P + source region (103) is boron.
3. The monitoring structure of contact hole chain resistance of a field effect transistor according to claim 1, characterized in that the junction depth of each N + body region (102) is 1-1.5 μm, and the junction depth of each P + source region (103) is 0.1-0.5 μm.
4. A monitoring structure of contact hole chain resistance of a field effect transistor is characterized by comprising a P well (501) formed on an N-type epitaxial layer (5), wherein the upper end surface of the P well (501) is covered with a passivation layer (2);
n P + body regions (502) are formed in the P well (501), each P + body region (502) is arranged at intervals, the depth of each P + body region (502) is the same, and n is a positive integer not less than 2;
an N + source region (503) is formed in the middle of each P + body region (502), the depth of each N + source region (503) is the same, and each N + source region (503) does not completely cover the corresponding P + body region (502);
two contact holes (3) penetrating through the passivation layer (2) are formed above each P + body region (502), and each contact hole (3) is overlapped with the N + source region (503) corresponding to the P + body region (502);
two contact holes (3) on each P + body area (502) are conducted through a P + body area (502), one contact hole (3) on the 1 st P + body area (502) serves as a leading-out end through metal (4), the other contact hole (3) on the 1 st P + body area (502) is conducted with one contact hole (3) on the 2 nd P + body area (502) through metal (4), the other contact hole (3) on the 2 nd P + body area (502) is conducted with one contact hole (3) on the 3 rd P + body area (502) through metal (4), and in the same way, the other contact hole (3) on the n-1 th P + body area (502) is conducted with the contact hole (3) on the nth P + body area (502) through the metal (4), and the other contact hole (3) on the nth P + body area (502) serves as a leading-out terminal through the metal (4).
5. The monitoring structure of contact hole chain resistance of a field effect transistor according to claim 4, characterized in that the doping impurity in each P + body region (502) is boron and the doping impurity in each N + source region (503) is arsenic.
6. The monitoring structure of contact hole chain resistance of a field effect transistor according to claim 4, characterized in that the junction depth of each P + body region (502) is 1-1.5 μm, and the junction depth of each N + source region (503) is 0.1-0.5 μm.
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| CN106558509A (en) * | 2015-09-25 | 2017-04-05 | 中芯国际集成电路制造(上海)有限公司 | A kind of measurement structure and measuring method, electronic installation of FinFET contact resistance |
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