CN112883681A - Electronic design automation EDA simulation method and device - Google Patents
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Abstract
The embodiment of the application provides an electronic design automation EDA simulation method and device, initial distribution grids are distributed to each thread according to the vertex quantity of a first graph and the operation speed of each thread, wherein the number of the initial distribution grids is related to the vertex quantity of the first graph in a target layout, namely the initial grid quantity distributed to each thread is determined according to the graph characteristics in the target layout.
Description
Technical Field
The invention relates to the field of Electronic Design Automation (EDA) simulation, in particular to an EDA simulation method and device for electronic design automation.
Background
As the chip industry has advanced in technology, the chip industry has entered the nanometer level, and in order to better perform chip manufacturing and improve product yield, Electronic Design Automation (EDA) tools are used to perform simulation of the chip manufacturing process before chip manufacturing, so as to predict possible problems and results in the manufacturing process according to the simulation results. In the process of manufacturing chips, in order to make the chips light and thin, the chips are usually polished by chemical mechanical polishing, but after chemical mechanical polishing, unevenness of the wafer surface may be caused, which affects the reliability of the chips, so that the wafer surface may be filled with redundant metal to improve the flatness of the wafer surface.
In the simulation process of performing the dummy metal filling by using the EDA tool, in order to ensure the reliability of the simulation, a large amount of data may be processed, and the simulation result may be performed as fast as possible so as to perform the chip manufacturing as fast as possible, and therefore, there is a demand for increasing the speed of the EDA tool simulation.
Disclosure of Invention
In view of the above, an object of the present application is to provide an electronic design automation EDA simulation method that improves the speed of EDA tool simulation as a whole.
In order to achieve the purpose, the technical scheme is as follows:
an Electronic Design Automation (EDA) simulation method, the method comprising:
obtaining a target layout, wherein the target layout comprises a first graph and a second graph, the first graph corresponds to a metal material, and the second graph corresponds to a dielectric material;
equally dividing the target layout into a plurality of grids to be distributed;
and allocating an initial allocation grid for each thread according to the number of the vertexes of the first graph and the operation speed of each thread in the multiple threads so that each thread in the multiple threads can process the first graph or the second graph included in the allocated initial allocation grid, and the operation speed of each thread is matched with the number of the initial allocation grids.
Optionally, the allocating an initial distribution grid to each thread according to the number of vertices of the first graph and the operation speed of each thread in the plurality of threads includes:
determining the number of vertexes included in each mesh on average according to the number of vertexes of the first graph and the number of the meshes to be distributed;
determining the ratio of the maximum number of the vertexes processed in the unit time of each thread to the average number of the vertexes included in each mesh as the maximum mesh number processed by each thread;
and determining the maximum grid number processed by each thread as the number of the initial distribution grids.
Optionally, the determining the maximum number of grids processed by each thread as the number of the initial distribution grids includes:
and if the maximum grid number processed by each thread is smaller than the preset minimum grid number processed by each thread, setting the number of the initial distribution grids as the preset minimum grid number processed by each thread.
Optionally, the determining the maximum number of grids processed by each thread as the number of the initial distribution grids includes:
and if the maximum grid number processed by each thread is smaller than the average grid number processed by each thread, setting the number of the initial distribution grids as the average grid number processed by each thread, wherein the average grid number processed by each thread is determined according to the number of grids to be distributed and the number of a plurality of threads.
Optionally, each of the multiple threads processes the first graph or the second graph included in the allocated initial allocation grid, including:
and each thread in the multiple threads sequentially carries out intersection operation on the first graph in each grid of the allocated initial allocation grid to obtain graph information of the multiple first graphs.
Optionally, if each grid includes a plurality of first graphs, and the plurality of first graphs are overlapped with each other, after each thread in the plurality of threads performs an intersection operation on the first graph in each grid of the allocated initial allocation grid in sequence, the method further includes:
and each thread in the multiple threads performs parallel operation according to the first graph in each grid, removes the overlapping area of the multiple first graphs, and obtains the grid density of the area of the multiple first graphs with the overlapping area removed occupying the area of the grid where the multiple first graphs are located.
Optionally, each of the multiple threads processes the first graph or the second graph included in the allocated initial allocation grid, including:
and each thread in the multiple threads performs subtraction operation on the first graph in each grid of the distributed initial distribution grid in sequence to obtain the position of the second graph in each grid.
An Electronic Design Automation (EDA) simulation apparatus, the apparatus comprising:
the device comprises an acquisition unit, a detection unit and a processing unit, wherein the acquisition unit is used for acquiring a target layout, the target layout comprises a first graph and a second graph, the first graph corresponds to a metal material, and the second graph corresponds to a dielectric material;
the dividing unit is used for equally dividing the target layout into a plurality of grids to be distributed;
and the allocation unit is used for allocating an initial allocation grid to each thread according to the number of the vertexes of the first graph and the operation speed of each thread in the multiple threads so that each thread in the multiple threads can process the first graph or the second graph included in the allocated initial allocation grid, and the operation speed of each thread is matched with the number of the initial allocation grids.
Optionally, the allocation unit is specifically configured to:
determining the number of vertexes included in each mesh on average according to the number of vertexes of the first graph and the number of the meshes to be distributed;
determining the ratio of the maximum number of the vertexes processed in the unit time of each thread to the average number of the vertexes included in each mesh as the maximum mesh number processed by each thread;
and determining the maximum grid number processed by each thread as the number of the initial distribution grids.
Optionally, the determining, by the allocation unit, the maximum number of grids processed by each thread as the number of the initial allocation grids includes:
if the maximum grid number processed by each thread is smaller than the preset minimum grid number processed by each thread, the allocation unit sets the number of the initial allocation grids as the preset minimum grid number processed by each thread.
Optionally, the determining, by the allocation unit, the maximum number of grids processed by each thread as the number of the initial allocation grids includes:
if the maximum grid number processed by each thread is smaller than the grid number processed by each thread on average, the allocation unit sets the number of the initial allocation grids as the grid number processed by each thread on average, wherein the grid number processed by each thread on average is determined according to the number of the grids to be allocated and the number of the multiple threads.
Optionally, each of the multiple threads processes the first graph or the second graph included in the allocated initial allocation grid, including:
and each thread in the multiple threads sequentially carries out intersection operation on the first graph in each grid of the allocated initial allocation grid to obtain graph information of the multiple first graphs.
Optionally, if each grid includes a plurality of first graphs, and the plurality of first graphs overlap with each other, after each thread in the plurality of threads performs an intersection operation on the first graph in each grid of the allocated initial allocation grid in sequence, the method further includes:
and each thread in the multiple threads performs parallel operation according to the first graph in each grid, removes the overlapping area of the multiple first graphs, and obtains the grid density of the area of the multiple first graphs with the overlapping area removed occupying the area of the grid where the multiple first graphs are located.
Optionally, each of the multiple threads processes the first graph or the second graph included in the allocated initial allocation grid, including:
and each thread in the multiple threads performs subtraction operation on the first graph in each grid of the distributed initial distribution grid in sequence to obtain the position of the second graph in each grid.
The embodiment of the application provides an Electronic Design Automation (EDA) simulation method, which comprises the following steps: obtaining a target layout, wherein the target layout comprises a first graph and a second graph, the first graph corresponds to a metal material, and the second graph corresponds to a dielectric material; equally dividing the target layout into a plurality of grids to be distributed; and allocating an initial allocation grid for each thread according to the number of the vertexes of the first graph and the operation speed of each thread in the multiple threads so that each thread in the multiple threads can process the first graph or the second graph included in the allocated initial allocation grid, and the operation speed of each thread is matched with the number of the initial allocation grids.
According to the EDA simulation method provided by the embodiment of the application, the initial distribution grids are distributed to each thread according to the vertex quantity of the first graphs and the operation speed of each thread, wherein the number of the initial distribution grids is related to the vertex quantity of the first graphs included in the target layout, namely, the initial grid quantity distributed to each thread is determined according to the graph features included in the target layout.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic diagram illustrating grid allocation in a layout according to the prior art;
FIG. 2 is a flow chart of an EDA simulation method for electronic design automation provided by the embodiment of the application;
fig. 3 shows a block diagram of an electronic design automation EDA simulation apparatus provided according to an embodiment of the present application.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, embodiments accompanying the present application are described in detail below with reference to the accompanying drawings.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, but the present application may be practiced in other ways than those described herein, and it will be apparent to those of ordinary skill in the art that the present application is not limited by the specific embodiments disclosed below.
At present, as technology develops, the chip industry has entered into the nanometer level, and in order to better perform chip manufacturing and improve product yield, Electronic Design Automation (EDA) tools are used to perform simulation of a chip manufacturing process before chip manufacturing, so as to predict possible problems and results in the manufacturing process according to simulation results. In the process of manufacturing chips, in order to make the chips light and thin, the chips are usually polished by chemical mechanical polishing, but after chemical mechanical polishing, unevenness of the wafer surface may be caused, which affects the reliability of the chips, so that the wafer surface may be filled with redundant metal to improve the flatness of the wafer surface.
In the simulation process of filling the redundant metal by using the EDA tool, the EDA tool can acquire blank regions of the whole chip simulation layout except for the metal interconnection lines, cut the blank regions and fill the redundant metal into the blank regions, so that the density of metal patterns in the layout is increased, the uniformity of the layout patterns is improved, and the purpose of improving the flatness of the chip is achieved.
Referring to fig. 1, a diagram of allocating a plurality of grids to a plurality of threads in a layout in the prior art is shown. It can be seen from the figure that, a plurality of grids in the layout are allocated to 6 threads, and the number of grids processed by each thread is fixed, that is, no matter how the graphic features in the layout change, the number of grids processed by each thread does not change, which may result in that, if the graphic features of the layout are complicated, because the number of grids processed by each thread is determined, some threads in different threads may have a higher processing speed, some threads have a lower processing speed, the threads with a higher processing speed may enter a wait, and finally, the overall speed of simulation by the EDA tool becomes slower, thereby increasing the simulation time.
In order to ensure the reliability of the simulation during the simulation, a large amount of data may be processed, and the simulation results may be performed as quickly as possible in order to perform the chip manufacturing as quickly as possible, so there is a need to increase the speed of the simulation of the EDA tool.
Based on the above technical problems, the embodiments of the present application provide an electronic design automation EDA simulation method, by assigning an initial allocation grid to each thread based on the number of vertices of the first graph and the operating speed of each thread, wherein the number of initial distribution grids is related to the number of vertices of the first graph included in the target layout, that is, in the embodiment of the present application, the initial number of grids allocated to each thread is determined according to the graphic features included in the target layout, and compared with the scheme in the prior art in which the number of grids allocated to each thread is fixed when the target layout with different graphic features is processed by each thread without considering the graphic features of the target layout, and the number of grids matched with the operation speed of each thread is distributed to each thread according to the graphic features of different layouts, so that the simulation speed of the EDA tool can be integrally improved, and the integral simulation time is shortened.
For a better understanding of the technical solutions and effects of the present application, specific embodiments will be described in detail below with reference to the accompanying drawings.
Referring to fig. 2, a flow chart of an electronic design automation EDA simulation method provided in an embodiment of the present application is shown, and the method includes the following steps:
s201, obtaining a target layout, wherein the target layout comprises a first graph and a second graph, the first graph corresponds to a metal material, and the second graph corresponds to a dielectric material.
In the embodiment of the application, the target layout may be obtained by an EDA simulation tool, and the target layout may be a layout to be filled with a redundant metal, that is, a layout of a chip after chemical mechanical polishing.
In an embodiment of the present application, the target layout is a layout to be filled with a redundant metal, the target layout may include a plurality of patterns, a first pattern and a second pattern, and the second pattern may be obtained by subtracting the first pattern from the grid, where the first pattern may correspond to a metal material, such as a metal interconnection line, and the second pattern may correspond to a dielectric material.
S202, equally dividing the target layout into a plurality of grids to be distributed.
In the embodiment of the application, the target layout can be equally divided into a plurality of grids to be allocated, so that the grids to be allocated are allocated to a plurality of threads for processing. Specifically, the size of the grid to be distributed can be configured by the user of the EDA simulation tool, and preferably, the grid to be distributed can be square with an area of 400 square microns.
S203, allocating an initial allocation grid for each thread according to the number of the vertexes of the first graph and the operation speed of each thread in the multiple threads, so that each thread in the multiple threads can process the first graph or the second graph included in the allocated initial allocation grid, and the operation speed of each thread is matched with the number of the initial allocation grids.
In the embodiment of the present application, each thread has its own computation speed, and the computation speed may be the amount of tasks processed by the thread per unit time when the utilization rate of the CPU of the thread has reached the maximum value. Alternatively, the operating speeds of multiple threads in the same device may be the same.
In practical application, when the EDA simulation tool is used to perform simulation of filling the redundant metal, the process can be mainly divided into the following processes: reading in layout data, calculating grid density, converting polygons, externally expanding, acquiring blank regions, segmenting the blank regions and filling the blank regions. The grid density calculation is to calculate the ratio of the metal material to the area of each grid, i.e. the ratio of the first pattern occupying each grid. The grid density calculation and blank area acquisition module performs data calculation by taking a grid as a unit, the grid processing performed by a plurality of threads is mainly to process a polygon in a target layout, and the polygon is composed of a plurality of vertexes, so that the operation speed of each thread is finally closely related to the number of graph vertexes contained in the grid. The number of graphs contained in different layouts is different from the number of grids, the number of graphs contained in each grid is also different, the larger the number of graph vertexes contained in the grids is, and the slower the grid processing speed of the thread is. In the embodiment of the application, an initial allocation grid may be allocated to each thread according to the number of vertices of the first graph and the operation speed of each thread in the plurality of threads, where the number of initial allocation grids matches the operation speed of each thread. Specifically, the number of initially allocated grids is the number of grids to be processed when the CPU of each thread is fully loaded. The number of the vertices of the first graph may represent the graph features in the target layout, that is, the number of the initial distribution grids allocated to each thread may be obtained according to the graph features of the target layout in the embodiment of the present application. For different target layouts, the graphic features of each target layout are different, so that the number of the initial distribution grids obtained by each target layout is different.
In practical applications, an initial allocation grid may be assigned to each thread according to the number of vertices of the graph matching the operation speed of each thread. Alternatively, the number of vertices included in each mesh is determined on average according to the number of vertices of the first graph and the number of meshes to be allocated, then the maximum number of vertices processed by each thread in unit time is determined as the maximum number of meshes processed by each thread by using the ratio of the maximum number of vertices processed by each thread to the average number of vertices included in each mesh, and the maximum number of meshes processed by each thread is determined as the number of meshes to be initially allocated.
As an example, the number of vertices of the first graph is 1000, the number of meshes to be allocated is 100, each mesh includes 1000/100 ═ 10 vertices on average, the maximum number of vertices processed by each thread in a unit time is 20, the maximum number of meshes processed by each thread is the ratio of the maximum number of vertices processed by each thread in a unit time to the number of vertices included in each mesh, that is, 20/10 ═ 2, and the maximum number of meshes processed by each thread may be determined as the number of initially allocated meshes, that is, the number of initially allocated meshes is 2.
In practical applications, if the calculated maximum number of grids processed by each thread does not meet the requirement, the maximum number of grids processed by each thread may not be determined as the number of the initial distribution grids.
As a possible implementation manner, if the maximum number of meshes processed by each thread is smaller than the preset minimum number of meshes processed by each thread, the number of the initial allocation meshes is set to the preset minimum number of meshes processed by each thread. The reason why the minimum number of meshes to be processed per thread is set in advance is to prevent the maximum number of meshes to be processed per thread from being equal to 0, and when the maximum number of meshes to be processed per thread is equal to 0, it is described that the number of vertices of a graphic included in each mesh exceeds the maximum number of vertices to be processed per thread per unit time, and it takes a long time for each mesh to be processed. The minimum grid number processed by each thread can be set according to actual conditions.
As another possible implementation manner, if the maximum number of grids processed by each thread is smaller than the average number of grids processed by each thread, the number of initial allocation grids is set as the average number of grids processed by each thread, wherein the average number of grids processed by each thread is determined according to the number of grids to be allocated and the number of multiple threads. And if the maximum grid number processed by each thread is smaller than the value, the thread is idle, and in order to better utilize the thread, the maximum grid number processed by each thread is reset to be the average grid number processed by each thread.
In the embodiment of the application, some grids to be allocated may remain after the initial allocation grid is allocated to each thread, and after the initial allocation grid is processed by at least one thread, a subsequent allocation grid matched with the number of the initial allocation grids is continuously allocated to the at least one thread for processing, so that the thread continues to work and is not idle. This reduces the latency after each thread finishes processing the currently allocated grid, further reducing the simulation time of the EDA.
In the embodiment of the application, when each thread processes the allocated initial allocation grid, the first graph or the second graph in the grid is mainly processed. When each thread processes the allocated grids, the processing is carried out one by one according to the sequence, and the next processing is continued until the current grid is processed.
In the embodiment of the present application, when the EDA simulation tool performs simulation of filling the redundant metal, the grid density calculation and the blank area acquisition are processes that take a long time and require processing of the graphics included in the grid.
When performing the grid density calculation, the following steps may be used for processing:
and each thread in the multiple threads sequentially carries out intersection operation on the first graph in each grid of the allocated initial allocation grid to obtain graph information of the multiple first graphs. That is, each thread performs intersection operation on the first graph in each grid and the current grid in sequence to obtain a plurality of intersected first graphs.
If each grid comprises a plurality of first graphs, and the first graphs are mutually overlapped, each thread in the threads performs parallel operation on the first graphs in each grid, and an area where the first graphs are overlapped is removed, so that the grid density of the area of the first graphs with the overlapped area removed occupying the area of the grid where the first graphs are located is obtained. That is, if a plurality of mutually overlapped first patterns are included in a mesh, the first patterns are subjected to a merging operation and then continued to be merged so as to remove an overlapped region, and an area ratio of the mesh occupied by the areas of the first patterns after the overlapped region is removed is calculated, and the ratio is the mesh density.
When the blank area is acquired, the following steps may be used to perform the processing:
and each thread in the multiple threads performs subtraction operation on the first graph in each grid of the allocated initial allocation grid in sequence to obtain the position of the second graph in each grid. That is, when the blank area is obtained, the mesh and the first graph may be subtracted according to the information of the first graph obtained in the mesh density calculation step, so as to obtain an area of the second graph of the current mesh, that is, the blank area.
In the embodiment of the application, when two steps of grid density calculation and blank area acquisition are performed, a plurality of grids to be allocated in a target layout need to be allocated to a plurality of threads for processing, and the number of the grids allocated to each thread in the two steps is the same as the number of the grids initially allocated. That is, no matter the step of grid density calculation or the step of blank area acquisition, an initial allocation grid is allocated to each thread, and the number of grids allocated to each thread by the two steps is the same.
According to the EDA simulation method provided by the embodiment of the application, the initial distribution grids are distributed to each thread according to the vertex quantity of the first graphs and the operation speed of each thread, wherein the number of the initial distribution grids is related to the vertex quantity of the first graphs included in the target layout, namely, the initial grid quantity distributed to each thread is determined according to the graph features included in the target layout.
Based on the electronic design automation EDA simulation method provided by the above embodiment, the embodiment of the present application further provides an electronic design automation EDA simulation apparatus, and the working principle thereof is described in detail below with reference to the accompanying drawings.
Referring to fig. 3, the figure is a block diagram of an electronic design automation EDA simulation apparatus according to an embodiment of the present application.
The electronic design automation EDA simulation apparatus 300 provided in this embodiment includes:
an obtaining unit 310, configured to obtain a target layout, where the target layout includes a first graph and a second graph, the first graph corresponds to a metal material, and the second graph corresponds to a dielectric material;
a dividing unit 320, configured to equally divide the target layout into a plurality of grids to be allocated;
the allocating unit 330 is configured to allocate an initial allocation grid to each thread according to the number of vertices of the first graph and the computation speed of each thread in the multiple threads, so that each thread in the multiple threads processes the first graph or the second graph included in the allocated initial allocation grid, and the computation speed of each thread is matched with the number of the initial allocation grids.
Optionally, the allocating unit 330 is specifically configured to:
determining the number of vertexes included in each mesh on average according to the number of vertexes of the first graph and the number of the meshes to be distributed;
determining the ratio of the maximum number of the vertexes processed in the unit time of each thread to the average number of the vertexes included in each mesh as the maximum mesh number processed by each thread;
and determining the maximum grid number processed by each thread as the number of the initial distribution grids.
Optionally, the determining, by the allocating unit 330, the maximum number of grids processed by each thread as the number of the initial allocation grids includes:
if the maximum grid number processed by each thread is smaller than the preset minimum grid number processed by each thread, the allocation unit sets the number of the initial allocation grids as the preset minimum grid number processed by each thread.
Optionally, the determining, by the allocating unit 330, the maximum number of grids processed by each thread as the number of the initial allocation grids includes:
if the maximum grid number processed by each thread is smaller than the grid number processed by each thread on average, the allocation unit sets the number of the initial allocation grids as the grid number processed by each thread on average, wherein the grid number processed by each thread on average is determined according to the number of the grids to be allocated and the number of the multiple threads.
Optionally, each of the multiple threads processes the first graph or the second graph included in the allocated initial allocation grid, including:
and each thread in the multiple threads sequentially carries out intersection operation on the first graph in each grid of the allocated initial allocation grid to obtain graph information of the multiple first graphs.
Optionally, if each grid includes a plurality of first graphs, and the plurality of first graphs overlap with each other, after each thread in the plurality of threads performs an intersection operation on the first graph in each grid of the allocated initial allocation grid in sequence, the method further includes:
and each thread in the multiple threads performs parallel operation according to the first graph in each grid, removes the overlapping area of the multiple first graphs, and obtains the grid density of the area of the multiple first graphs with the overlapping area removed occupying the area of the grid where the multiple first graphs are located.
Optionally, each of the multiple threads processes the first graph or the second graph included in the allocated initial allocation grid, including:
and each thread in the multiple threads performs subtraction operation on the first graph in each grid of the distributed initial distribution grid in sequence to obtain the position of the second graph in each grid.
When introducing elements of various embodiments of the present application, the articles "a," "an," "the," and "said" are intended to mean that there are one or more of the elements. The terms "comprising," "including," and "having" are intended to be inclusive and mean that there may be additional elements other than the listed elements.
It should be noted that, as one of ordinary skill in the art would understand, all or part of the processes of the above method embodiments may be implemented by a computer program to instruct related hardware, where the computer program may be stored in a computer readable storage medium, and when executed, the computer program may include the processes of the above method embodiments. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like.
The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the apparatus embodiment, since it is substantially similar to the method embodiment, it is relatively simple to describe, and reference may be made to some descriptions of the method embodiment for relevant points.
The foregoing is merely a preferred embodiment of the present application and, although the present application discloses the foregoing preferred embodiments, the present application is not limited thereto. Those skilled in the art can now make numerous possible variations and modifications to the disclosed embodiments, or modify equivalent embodiments, using the methods and techniques disclosed above, without departing from the scope of the claimed embodiments. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application still fall within the protection scope of the technical solution of the present application without departing from the content of the technical solution of the present application.
Claims (10)
1. An Electronic Design Automation (EDA) simulation method, characterized in that the method comprises:
obtaining a target layout, wherein the target layout comprises a first graph and a second graph, the first graph corresponds to a metal material, and the second graph corresponds to a dielectric material;
equally dividing the target layout into a plurality of grids to be distributed;
and allocating an initial allocation grid for each thread according to the number of the vertexes of the first graph and the operation speed of each thread in the multiple threads so that each thread in the multiple threads can process the first graph or the second graph included in the allocated initial allocation grid, and the operation speed of each thread is matched with the number of the initial allocation grids.
2. The method of claim 1, wherein assigning an initial assignment grid to each thread based on the number of vertices of the first graph and the operating speed of each thread of the plurality of threads comprises:
determining the number of vertexes included in each mesh on average according to the number of vertexes of the first graph and the number of the meshes to be distributed;
determining the ratio of the maximum number of the vertexes processed in the unit time of each thread to the average number of the vertexes included in each mesh as the maximum mesh number processed by each thread;
and determining the maximum grid number processed by each thread as the number of the initial distribution grids.
3. The method of claim 2, wherein determining the maximum number of grids processed by each thread as the number of initial allocation grids comprises:
and if the maximum grid number processed by each thread is smaller than the preset minimum grid number processed by each thread, setting the number of the initial distribution grids as the preset minimum grid number processed by each thread.
4. The method of claim 2, wherein determining the maximum number of grids processed by each thread as the number of initial allocation grids comprises:
and if the maximum grid number processed by each thread is smaller than the average grid number processed by each thread, setting the number of the initial distribution grids as the average grid number processed by each thread, wherein the average grid number processed by each thread is determined according to the number of grids to be distributed and the number of a plurality of threads.
5. The method of claim 1, wherein each thread of the plurality of threads processing the first graphic or the second graphic included in the allocated initial allocation grid comprises:
and each thread in the multiple threads sequentially carries out intersection operation on the first graph in each grid of the allocated initial allocation grid to obtain graph information of the multiple first graphs.
6. The method of claim 5, wherein if each grid includes a plurality of first graphics, and the plurality of first graphics overlap each other, after each thread in the plurality of threads performs an intersection operation on the first graphics in each grid of the allocated initial allocation grid in turn, the method further comprises:
and each thread in the multiple threads performs parallel operation according to the first graph in each grid, removes the overlapping area of the multiple first graphs, and obtains the grid density of the area of the multiple first graphs with the overlapping area removed occupying the area of the grid where the multiple first graphs are located.
7. The method of claim 1, wherein each thread of the plurality of threads processing the first graphic or the second graphic included in the allocated initial allocation grid comprises:
and each thread in the multiple threads performs subtraction operation on the first graph in each grid of the distributed initial distribution grid in sequence to obtain the position of the second graph in each grid.
8. An Electronic Design Automation (EDA) simulation apparatus, the apparatus comprising:
the device comprises an acquisition unit, a detection unit and a processing unit, wherein the acquisition unit is used for acquiring a target layout, the target layout comprises a first graph and a second graph, the first graph corresponds to a metal material, and the second graph corresponds to a dielectric material;
the dividing unit is used for equally dividing the target layout into a plurality of grids to be distributed;
and the allocation unit is used for allocating an initial allocation grid to each thread according to the number of the vertexes of the first graph and the operation speed of each thread in the multiple threads so that each thread in the multiple threads can process the first graph or the second graph included in the allocated initial allocation grid, and the operation speed of each thread is matched with the number of the initial allocation grids.
9. The apparatus according to claim 8, wherein the allocation unit is specifically configured to:
determining the number of vertexes included in each mesh on average according to the number of vertexes of the first graph and the number of the meshes to be distributed;
determining the ratio of the maximum number of the vertexes processed in the unit time of each thread to the average number of the vertexes included in each mesh as the maximum mesh number processed by each thread;
and determining the maximum grid number processed by each thread as the number of the initial distribution grids.
10. The apparatus of claim 9, wherein the allocation unit determines the maximum number of grids processed by each thread as the number of the initial allocation grids comprises:
if the maximum grid number processed by each thread is smaller than the preset minimum grid number processed by each thread, the allocation unit sets the number of the initial allocation grids as the preset minimum grid number processed by each thread.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000077694A1 (en) * | 1999-06-12 | 2000-12-21 | American Applied Research, Inc. | Improved simulation system for modeling the electromagnetic response of electronic design packages |
| US20060281221A1 (en) * | 2005-06-09 | 2006-12-14 | Sharad Mehrotra | Enhanced routing grid system and method |
| CN105808791A (en) * | 2014-12-29 | 2016-07-27 | 北京华大九天软件有限公司 | An acceleration method for resistance calculation mesh division |
| CN107346350A (en) * | 2016-05-06 | 2017-11-14 | 中国科学院微电子研究所 | Distribution method, device and cluster system for integrated circuit layout data processing tasks |
| US20180032648A1 (en) * | 2016-07-28 | 2018-02-01 | Yun Cao | Simulation method of cmp process |
| CN109002566A (en) * | 2017-06-07 | 2018-12-14 | 中国科学院微电子研究所 | Filling method and system for redundant metal |
| CN109284578A (en) * | 2018-02-27 | 2019-01-29 | 上海安路信息科技有限公司 | Logic circuit layout wiring method, graphic software platform method and its system |
-
2021
- 2021-03-25 CN CN202110319529.XA patent/CN112883681B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000077694A1 (en) * | 1999-06-12 | 2000-12-21 | American Applied Research, Inc. | Improved simulation system for modeling the electromagnetic response of electronic design packages |
| US20060281221A1 (en) * | 2005-06-09 | 2006-12-14 | Sharad Mehrotra | Enhanced routing grid system and method |
| CN105808791A (en) * | 2014-12-29 | 2016-07-27 | 北京华大九天软件有限公司 | An acceleration method for resistance calculation mesh division |
| CN107346350A (en) * | 2016-05-06 | 2017-11-14 | 中国科学院微电子研究所 | Distribution method, device and cluster system for integrated circuit layout data processing tasks |
| US20180032648A1 (en) * | 2016-07-28 | 2018-02-01 | Yun Cao | Simulation method of cmp process |
| CN109002566A (en) * | 2017-06-07 | 2018-12-14 | 中国科学院微电子研究所 | Filling method and system for redundant metal |
| CN109284578A (en) * | 2018-02-27 | 2019-01-29 | 上海安路信息科技有限公司 | Logic circuit layout wiring method, graphic software platform method and its system |
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