CN116205194A

CN116205194A - Method, apparatus and medium for graphics generation

Info

Publication number: CN116205194A
Application number: CN202211722855.6A
Authority: CN
Inventors: 请求不公布姓名
Original assignee: Advanced Manufacturing EDA Co Ltd
Current assignee: Advanced Manufacturing EDA Co Ltd
Priority date: 2022-12-30
Filing date: 2022-12-30
Publication date: 2023-06-02

Abstract

Methods, devices, and media for graphics generation are provided in accordance with example embodiments of the present disclosure. In the method, a first combined graph is added in a region of the layout to be updated based at least on a first constraint condition for the layout. The first combined pattern includes a plurality of sub-patterns connected. The first constraint is associated with a layout between different sub-graphs in the combined graph. The method further includes adjusting a position of the first combined pattern in the area to be updated based at least on a second constraint on the layout. The second constraint is associated with a layout between different combined patterns in the layout. In this way, a combined graph that satisfies a plurality of constraints can be generated in the layout.

Description

Method, apparatus and medium for graphics generation

Technical Field

Embodiments of the present disclosure relate generally to the field of integrated circuits and, more particularly, relate to methods, apparatuses, and media for graphics generation.

Background

A circuit layout (which may be simply referred to as a layout) is a series of geometric figures converted from a designed and simulated optimized circuit, and includes physical information data related to devices such as integrated circuit dimensions, topology definitions of various layers, and the like. The integrated circuit manufacturer manufactures a mask from this data. The layout pattern on the mask determines the size of the on-chip device or the connection physical layer.

With the reduction of technology nodes in the semiconductor chip manufacturing process, the transistor density and performance on the chip are greatly improved. On the other hand, along with the improvement of the process, the development difficulty is increased continuously, and the higher requirements are put on the production and design links of the integrated circuit. For this reason, it has been proposed to add random patterns to a layout, thereby increasing the diversity of the patterns of the layout, and thus improving the manufacturing capability of chips and the manufacturability of the layout.

Disclosure of Invention

In a first aspect of the present disclosure, a method for graphics generation is provided. In the method, a first combined graph is added in a region of the layout to be updated based at least on a first constraint condition for the layout. The first combined pattern includes a plurality of sub-patterns connected. The first constraint is associated with a layout between different sub-graphs in the combined graph. The method further includes adjusting a position of the first combined pattern in the area to be updated based at least on a second constraint on the layout. The second constraint is associated with a layout between different combined patterns in the layout. In this way, a combined graph that satisfies a plurality of constraints can be generated in the layout.

In a second aspect of the present disclosure, an electronic device is provided. The electronic device includes a processor, and a memory coupled to the processor. The memory has instructions stored therein that, when executed by the processor, cause the electronic device to perform a method for graphics generation according to the first aspect of the present disclosure.

In a third aspect of the present disclosure, a computer-readable storage medium is provided. The computer readable storage medium has a computer program stored thereon. The computer program, when executed by a processor, implements a method for graphics generation according to the first aspect of the present disclosure.

According to an embodiment of the present disclosure, a first combined graph composed of a plurality of connected sub-graphs is added in a region to be updated of a layout according to a first constraint condition for the layout. For example, the first combined pattern may include a plurality of rectangles connected. The first constraint is associated with a layout between different sub-graphs in the combined graph. And adjusting the position of the first combined graph in the area to be updated according to the second constraint condition aiming at the layout. The second constraint is associated with a layout between different combined patterns in the layout. In this way, embodiments of the present disclosure enable the combined patterns in the generated layout to satisfy a plurality of constraints, thereby forming satisfactory patterns on the wafer. The layout comprising a plurality of combined patterns can simulate the actual layout more truly.

It should be understood that what is described in this summary is not intended to limit the critical or essential features of the embodiments of the disclosure nor to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following description.

Drawings

The above and other features, advantages and aspects of embodiments of the present disclosure will become more apparent by reference to the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, wherein like or similar reference numerals designate like or similar elements, and wherein:

FIG. 1 illustrates a schematic diagram of an example environment in which embodiments of the present disclosure can be implemented;

FIG. 2 illustrates a flow chart of a method for graphics generation, according to some embodiments of the present disclosure;

fig. 3A-3C illustrate a system according to at least one DT2210003 in accordance with some embodiments of the present disclosure

Generating a schematic diagram of the graph by constraint conditions;

FIG. 4 shows a schematic diagram of a layout obtained according to the graph generation method of the present disclosure; and

fig. 5 illustrates a block diagram of an electronic device in which one or more embodiments of the disclosure may be implemented.

Detailed Description

Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present disclosure have been shown in the accompanying drawings, it is to be understood that the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for illustration purposes only and are not intended to limit the scope of the present disclosure.

In describing embodiments of the present disclosure, the term "comprising" and its like should be taken to be open-ended, i.e., including, but not limited to. The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first," "second," and the like, may refer to different or the same object. Other explicit and implicit definitions are also possible below.

As described above, with the reduction of technology nodes in semiconductor chip manufacturing processes, higher demands are placed on the production and design links of integrated circuits. At present, a scheme of adding random patterns on a layout is proposed, so that the diversity of the patterns of the layout is improved, and the manufacturing capacity of a chip and the manufacturability of the layout are improved. However, how to determine the layout of random patterns in a layout is a concern. On the one hand, the degree of freedom and randomness of the graphics generated by the conventional random graphics generation method are insufficient. On the other hand, conventional random pattern generation schemes cannot meet certain design rule requirements.

To this end, embodiments of the present disclosure propose a method for graphics generation. According to an embodiment of the present disclosure, a first combined graph composed of a plurality of connected sub-graphs is added in a region to be updated of a layout according to a first constraint condition for the layout. For example, the first combined pattern may include a plurality of rectangles connected. The first constraint is associated with a layout between different sub-graphs in the combined graph. And adjusting the position of the first combined graph in the area to be updated according to the second constraint condition aiming at the layout. The second constraint is associated with a layout between different combined patterns in the layout. In this way, embodiments of the present disclosure enable the combined patterns in the generated layout to satisfy a plurality of constraints, thereby forming satisfactory patterns on the wafer. The layout comprising a plurality of combined patterns can simulate the actual layout more truly.

Various example implementations of this scheme will be described in detail below with reference to the accompanying drawings.

Referring initially to FIG. 1, a schematic diagram of an example environment 100 in which embodiments of the present disclosure can be implemented is shown. The example environment 100 may generally include an electronic device 110. In some embodiments, electronic device 110 may be a computing-enabled device such as a personal computer, workstation, server, or the like. The scope of the present disclosure is not limited in this respect.

The electronic device 110 obtains as input the layout 120 to be processed. In some embodiments, the layout 120 to be processed may be a blank layout with no existing graphics thereon. Additionally or alternatively, in some embodiments, the layout 120 to be processed may also have one or more existing graphics (not shown) thereon. In embodiments where the layout 120 to be processed has an existing pattern thereon, the layout 120 to be processed has one or more blank areas thereon.

The electronic device 110 processes the layout 120 to be processed to obtain a processed layout 130. The processed layout 130 includes one or more combined graphics (also referred to as two-dimensional graphics), such as combined graphics 132, combined graphics 134, and combined graphics 136. The location and size of these combined

patterns

132, 134, and 136 in the processed layout 130 may be determined by the electronic device 110. This will be described in further detail below in connection with fig. 2-3C.

It should be understood that the shapes and sizes of the various layouts, masks, and combined patterns shown in FIG. 1 are exemplary only and not limiting. The number and layout of combined patterns in the layout are exemplary only and not limiting. The scope of the present disclosure is not limited in this respect.

Fig. 2 illustrates a flow chart of a method 200 for graphics generation, according to some embodiments of the present disclosure. In some embodiments, the method 200 may be performed by the electronic device 110 as shown in fig. 1. It should be understood that method 200 may also include additional blocks not shown and/or may omit certain block(s) shown, the scope of the present disclosure not being limited in this respect.

At block 210, the electronic device 110 adds a first combined pattern in a region of the layout to be updated based at least on a first constraint for the layout. The first combined pattern includes a plurality of sub-patterns connected. As an example, the plurality of sub-graphics may be rectangles or other suitable polygons. The first constraint is associated with a layout between different sub-graphs in the combined graph.

In some embodiments, the area of the layout to be updated may be the entire area of the layout. For example, if the layout does not have an existing pattern, the area to be updated may be the entire area of the layout. Taking the layout 120 to be processed in fig. 1 as an example, the electronic device 110 may determine the area to be updated of the layout 120 to be processed as the entire area of the layout 120 to be processed.

Additionally or alternatively, in some embodiments, the electronic device 110 may determine the area of the layout to update based on existing graphics in the layout. As an example, the electronic device 110 may determine a first boundary of the area to be updated based on boundaries of existing graphics in the layout. The electronic device 110 may determine the second boundary based on the boundaries of the layout. The electronic device 110 may in turn determine the area to update based at least on the first boundary and the second boundary. The area to be updated is separated from the area occupied by the existing pattern by a first boundary.

The electronic device 110 adds the first combined pattern in the area to be updated of the layout determined by the above procedure based on the first constraint condition. FIG. 3A illustrates an example of adding a first combined pattern to an area to be updated in a layout. The layout 120 of FIG. 1 is taken as the initial layout in FIG. 3A and a first combined pattern is added thereto. In this example, the area of the layout 120 to be updated is the entire area of the layout 120.

In some embodiments, the electronic device 110 may add the first sub-graphic to the area to be updated. As shown in the layout 310 of fig. 3A, the electronic device 110 adds a first sub-graphic 312 to the area to be updated. In some embodiments, the first sub-graphic 312 is randomly generated. As an example, the electronic device 110 may randomly generate a point in the area to be updated as the starting point of the first sub-graphic 312. The electronic device 110 in turn randomly generates a growth direction, e.g., a horizontal direction or a vertical direction, of the first sub-pattern 312. The electronic device 110 randomly generates the width and height of the first sub-pattern 312 based on the start point of the first sub-pattern 312 and the growth direction of the first sub-pattern 312. The first sub-graphic 312 may be a rectangle defined by randomly generated widths and heights. Additionally or alternatively, in some embodiments, vertex coordinate information for the first sub-graph 312 may be stored.

In some embodiments, the generated first sub-graph 312 may be required to satisfy a first constraint. For example, the first constraint may be associated with a predetermined range of graphics on the layout. The predetermined range of the graph may be a range to be updated or a sub-region having a predetermined size within the range to be updated. The first sub-graphic 312 needs to be within the predetermined range. For example, in some embodiments, a range of values for the length of the first combined pattern in the horizontal direction and in the vertical direction may be set. The first sub-graphic 312 may be located within a range defined by a range of values of lengths of the first combined graphic in the horizontal direction and in the vertical direction.

In some embodiments, the first constraint may also be associated with a size of the sub-graph. For example, the first constraint may indicate a predetermined range of values for the width and height of the sub-graph. The first sub-graph 312 needs to satisfy this range of values.

Additionally or alternatively, in some embodiments, the first sub-graphic 312 may also need to satisfy other constraints if there are already other sub-graphics in the layout before the first sub-graphic 312 is added. These constraints will be described below.

In some embodiments, the electronic device 110 may add a second sub-graphic connected to the first sub-graphic to the area to be updated based at least on the first constraint. The first combined graphic may include at least a first sub-graphic and a second sub-graphic. As shown in the layout 320 in fig. 3A, a second sub-graphic 322 connected to the first sub-graphic 312 is added to the layout 320.

In some embodiments, the second sub-graphic 322 may be randomly generated. For example, the electronic device 110 may randomly generate the growth direction of the second sub-graphic 322. As an example, the generation direction may be represented by an upward direction, a downward direction, a leftward direction, a rightward direction. The upward direction indicates that the second sub-graphic 322 of one vertical direction is generated upward based on the top line of the first sub-graphic 312. The downward direction indicates that a second sub-pattern 322 of one vertical direction is generated downward based on the bottom line of the first sub-pattern 312. The left direction indicates that a second sub-graphic 322 is generated in a horizontal direction toward the left based on the left line of the first sub-graphic 312. The right direction indicates that a second sub-graphic 322 in a horizontal direction is generated in the right direction based on the right line of the first sub-graphic 312.

In some embodiments, the electronic device 110 randomly generates the width and height of the second sub-graphic 322 based on the randomly generated direction. The electronic device 110 randomly generates bond points of the second sub-graphic 322 and the first sub-graphic 312 based on the width and height of the second sub-graphic 322 and the bond line of the first sub-graphic 312. Additionally or alternatively, in some embodiments, the electronic device 110 may also store vertex information (e.g., coordinates of one or more vertices) of the second sub-graph 322 randomly generated from above, and optionally the width and height of the second sub-graph 322.

The second sub-graphic 322 randomly generated by the electronic device 110 needs to satisfy the first constraint. As previously described, the first constraint may be associated with a predetermined range of graphics on the layout. The predetermined range of the graph may be a range to be updated or a sub-region having a predetermined size within the range to be updated. The second sub-graphic 314 needs to be within the predetermined range.

In some embodiments, the first constraint is associated with a first distance between different sub-graphs along a first direction. The first direction may be a horizontal direction. Additionally or alternatively, in some embodiments, the second constraint is associated with a second distance between different sub-graphs along a second direction. The second direction is perpendicular to the first direction. In an example where the first direction is a horizontal direction, the second direction is a vertical direction. As an example, the first constraint may limit the range of values of the first distance and/or the second distance. The second sub-graphic 322 and the first sub-graphic 312 randomly generated by the electronic device 110 need to satisfy the above-described range of values of the first distance and/or the second distance.

Additionally or alternatively, in some embodiments, the first constraint is associated with an angular diagonal distance between different sub-graphs. That is, the first constraint may limit the range of values of the angular diagonal distance between the sub-patterns. The angular diagonal distance refers to the distance between two angles of the two sub-patterns that are opposite in direction. The angular diagonal distance between the second sub-graphic 322 and the first sub-graphic 312, which the electronic device 110 randomly generates, needs to satisfy the range of values of the angular diagonal distance limited by the first constraint.

Additionally or alternatively, in some embodiments, the first constraint is associated with a parallel length (prl) between different sub-graphs. That is, the first constraint may limit the range of values of the parallel lengths between the sub-patterns. The parallel length may be the length of the parallel portion between the sub-patterns in the first direction or the length of the parallel portion between the sub-patterns in the second direction. The parallel length between the second sub-graphic 322 and the first sub-graphic 312 randomly generated by the electronic device 110 needs to satisfy the range of values of the parallel length limited by the first constraint.

In some embodiments, the electronic device 110, in randomly generating the first sub-graphic 312 and the second sub-graphic 322, may need to generate random values of attributes, such as width and height, for each sub-graphic according to the first constraint.

Additionally or alternatively, in some embodiments, the electronic device 110 generates candidate sub-graphics for the first combined graphic. For example, the electronic device 110 randomly generates attribute values, such as wide and high, for the candidate sub-graph without regard to the first constraint. The electronic device 110 in turn determines whether the generated candidate sub-graph satisfies the first constraint. If the electronic device 110 determines that the candidate sub-graph satisfies the first constraint, the candidate sub-graph is determined to be one of the plurality of sub-graphs. For example, the candidate sub-graphic may be determined as the second sub-graphic 322. Conversely, if the electronic device 110 determines that the candidate sub-graphic does not satisfy the first constraint, the electronic device 110 generates a new candidate sub-graphic for the first combined graphic. The above-described determination process is also performed for the newly generated candidate sub-graph.

In some embodiments, the electronic device 110 determines a number of times the candidate sub-graphic was generated for the first combined graphic. That is, the electronic device 110 randomly generates the candidate sub-graphic how many times in the process of generating the first combined graphic. If the electronic device 110 determines that the number of times the candidate sub-graphic was generated for the first combined graphic reaches the number of times threshold, the electronic device 110 stops generating the candidate sub-graphic for the first combined graphic. The number of times threshold may be preset. For example, the number of times threshold may be randomly generated by electronic device 110 in advance for the first combined pattern. The number of times threshold may also be set by the user. By setting the number of times threshold, the generation process of each sub-figure of the combined figure can be simplified.

As an example, if the number of times of generation of the candidate sub-graphic reaches the threshold number of times after the first sub-graphic 312 and the second sub-graphic 322 as shown are generated, generation of the candidate sub-graphic for the first combined graphic is stopped. That is, the first combined graphic is composed of the first sub-graphic 312 and the second sub-graphic 322. As another example, if only the first sub-graphic 312 is generated in the case where the number of times of generation of the candidate sub-graphic reaches the threshold value, the first combined graphic may include only the first sub-graphic 312.

Additionally or alternatively, in some embodiments, the first constraint further indicates a threshold number of sub-graphs in the combined graph. The threshold number may be preset, for example, randomly generated by the electronic device 110 or preset by a user. The first combined pattern includes no more than a threshold number of sub-patterns. As an example, the threshold number may be 3. In the case of generating the first set of graphics 312 and the second sub-graphics 322, the electronic device 110 may generate a third sub-graphics 332 using methods similar to the several examples described above, as shown by the layout 330 in FIG. 3A. In this example, a graphic composed of the first sub-graphic 312, the second sub-graphic 322, and the third sub-graphic 332 connected are combined as the first combined graphic 334. By setting the threshold number, the generation process of the combined pattern can be simplified.

It should be appreciated that the threshold numbers listed above are merely exemplary and not limiting, and that the threshold numbers may be set to any suitable value in excess of 1. It should be understood that the shape, size, number of sub-patterns shown in fig. 3A are merely exemplary and not limiting.

By adding the first combined graph according to the first constraint condition, the design rule can be satisfied between the sub-graphs in the added first combined graph. In this way, the graphics in the layout can be made to meet the process requirements or limitations of chip manufacturing.

In some embodiments, for the first combined graph, a perimeter-to-area ratio constraint (also referred to as an outer perimeter-to-area ratio constraint) is also provided. The perimeter-area ratio constraint indicates a range of values of the perimeter-area ratio of the combined pattern. Electronic device 110 may determine a first ratio between the outer perimeter and the effective area of first combined graphic 334. If the electronic device 110 determines that the first ratio does not satisfy the perimeter-to-area ratio constraint, the electronic device 110 regenerates the first combined graph. If the electronic device 110 determines that the first ratio satisfies the perimeter-to-area ratio constraint, the electronic device 110 may continue to generate the next combined graph.

The perimeter to area ratio constraint is set to enable the pattern in the layout to meet process requirements or limitations of chip fabrication, such as Chemical Mechanical Polishing (CMP) specifications. Specifically, the ratio of the peripheral area of each of the combined patterns satisfying the constraint of the ratio of the peripheral area is within a predetermined range of values. The values of the peripheral area ratios of the combined patterns are relatively similar. Patterns with similar perimeter to area ratios are more worn to similar degrees during the production process. Thus, by introducing a perimeter to area ratio constraint, a CMP friendly layout can be generated.

Several examples of adding the first combined graph according to the first constraint are described above in connection with fig. 3A. It should be understood that the examples of constraints listed above are merely exemplary and not limiting. Fewer or more constraints may be employed to add the first combined graph. Examples of other constraints may include sub-graphic area constraints, dimensions of sub-graphics in the first direction or the second direction, and other design rule constraints. The scope of the present disclosure is not limited in this respect. It should be appreciated that each of the ranges indicated by the respective constraints may be a continuous range or a discrete range, as the scope of the present disclosure is not limited in this respect.

By adding the first combined graph according to the first constraint condition, the combined graph with richer shapes can be added in the layout. The combined graph with rich shapes can simulate the actual layout more truly.

With continued reference to fig. 2. At block 220, the electronic device 110 adjusts the location of the first combined pattern in the area to be updated based at least on the second constraint on the layout. The second constraint is associated with a layout between different combined patterns in the layout.

In some embodiments, the second constraint is associated with at least one of: a distance between the different combined patterns in a first direction, a distance between the different combined patterns in a second direction perpendicular to the first direction, a diagonal distance between the different combined patterns, a parallel length between the different combined patterns, etc.

Specifically, the second constraint may indicate at least one of: a range of values of distances between the different combined patterns along a first direction, a range of values of distances between the different combined patterns along a second direction perpendicular to the first direction, a range of values of angular distances between the different combined patterns, a range of values of parallel lengths between the different combined patterns, and so forth. The corner-to-corner distance may be the distance between two corners of the layout where two combined patterns at different locations are opposite in direction. The parallel length may be the length of the parallel portion in the first direction between the different combined patterns or the length of the parallel portion in the second direction between the different combined patterns.

In some embodiments, if the first combined pattern 334 is the first combined pattern added in the layout 330, i.e., there are no other patterns in the layout 330, the electronic device 110 may not make a positional adjustment to the first combined pattern 334. In other words, for the first added combined graph in the layout, the electronic device 110 may not determine whether it satisfies the second constraint condition. Electronic device 110 may adjust the added combined graph after first combined graph 334 based on the second constraint. The adjustment process of the combined graph based on the second constraint will be described in detail below.

As previously described, after adding the first combined pattern 334, the electronic device 110 may add more combined patterns, such as a third combined pattern, to the layout. In some embodiments, the electronic device 110 may add a third combined graph in the area to be updated based on at least the first constraint and the second constraint. The third combined graph is also composed of a plurality of sub-graphs, which may be generated based on the first constraint. These sub-patterns are generated in a manner similar to the first sub-pattern 312, the second group of patterns 322, and the third sub-pattern 332 described above, and will not be described in detail herein. The third combined graph may be adjusted based on the second constraint.

In some embodiments, the electronic device 110 may redetermine the area of the layout 330 to be updated by taking the first combined pattern 334 as an existing pattern. The electronic device 110 in turn adds a combined pattern, e.g. a fourth combined pattern, in the redetermined area to be updated based on at least the first constraint and the second constraint. For example, the electronic device 110 adds a fourth combined pattern in the redetermined area to be updated based on the first constraint. The electronic device 110 further adjusts the position of the fourth combined pattern in the layout based on the second constraint.

As an example, electronic device 110 may determine a first boundary of the redetermined area to be updated based on the boundary of first combined graphic 334. For example, electronic device 110 may determine, based on the upper side of first combined graphic 334, that the first boundary is a line segment extending from the upper side to the left and right sides of layout 330. The electronic device 110 may take the area above the first boundary, which is formed by the first boundary and the boundary of the layout 330, as the redetermined area to be updated.

Additionally or alternatively, in some embodiments, the electronic device 110 may divide the redetermined area to be updated into a plurality of sub-areas. As shown in layout 340 of fig. 3B, the redetermined area to be updated is divided into

sub-areas

342 and 344. The sub-regions may be divided by the height of the upper side of the first combined pattern 334. The electronic device 110 may first add a fourth combined pattern within the sub-region 342 having the lower side. As shown in fig. 3B, the electronic device 110 adds a fourth combined graphic 346 within the sub-region 342. The fourth combined graph 346 is added based on the first constraint. The addition process of the fourth combined pattern 346 is similar to the first combined pattern 334 and will not be described in detail herein.

In some embodiments, in the event that the sub-region 342 is determined, the electronic device 110 also compares the width of the sub-region 342 in the horizontal direction to a threshold width. If the width of the sub-region 342 is less than the threshold width, then a fourth combined pattern is not added within the sub-region 342. By limiting the width of the sub-region 342, the addition of a combined pattern within a narrower sub-region may be prevented. In some embodiments, the threshold width may be preset. For example, the threshold width may be set to the sum of twice the minimum value of the width value range of the sub-pattern (e.g., rectangle) and twice the minimum value of the horizontal distance value range between the sub-patterns. It should be appreciated that the threshold width may also be determined in other ways, and the scope of the present disclosure is not limited in this respect.

In some embodiments, the electronic device 110 adjusts the position of the added fourth combined graphic 346 based on the second constraint. Specifically, the electronic device 110 may determine whether the fourth combined pattern 346 and the first combined pattern 334 satisfy the second constraint based on the current position of the fourth combined pattern 346 in the layout 340 and the known position of the first combined pattern 334 existing in the layout 340.

If the electronic device 110 determines that the fourth combined pattern 346 and the first combined pattern 334 do not satisfy the second constraint, the electronic device 110 determines a target direction in the layout that causes the second constraint to be satisfied. The electronic device 110 in turn moves the fourth combined graphic 346 in the target direction.

In some embodiments, if the distance in the first direction between the fourth combined graphic 346 and the first combined graphic 334 does not satisfy the range of values of the distance in the first direction between the different combined graphics indicated by the second constraint, the electronic device 110 may determine the target direction as horizontal to the right or vertical to the up. Similarly, if the distance in the second direction between the fourth combined graphic 346 and the first combined graphic 334 does not satisfy the range of values of the distance in the second direction between the different combined graphics indicated by the second constraint, the electronic device 110 may determine the target direction as horizontal right or vertical up. The electronic device 110 may determine the displacement amount of moving the fourth combined pattern 346 to the right or upward according to the range of the distance in the first direction or the second direction. By setting the distance constraint condition of the first direction or the second direction, the distance between the combined patterns can be prevented from being too close, so that the patterns can meet the technological requirements of chip manufacturing.

In some embodiments, if the angular diagonal distance between the fourth combined graphic 346 and the first combined graphic 334 does not satisfy the range of values of the angular diagonal distance between the different combined graphics indicated by the second constraint, the electronic device 110 may determine the target direction vertically upward. Additionally or alternatively, the electronic device 110 may calculate a required spacing of the two combined patterns in the vertical direction using a trigonometric relationship, thereby determining a displacement amount to move the fourth combined pattern 346 upward according to the required spacing. By setting the constraint condition of angular and diagonal distances, the situation that the angular and diagonal distances between the combined patterns are too close can be avoided, so that the patterns can meet the technological requirements of chip manufacturing.

In some embodiments, if the parallel length vertical direction space between the fourth combined graphic 346 and the first combined graphic 334 does not satisfy the range of values of the parallel length between the different combined graphics indicated by the second constraint, the electronic device 110 may determine the target direction vertically upward. Additionally or alternatively, the electronic device 110 may determine a magnitude of displacement to move the fourth combined graph 346 upward based on the range of values of the parallel lengths indicated by the second constraint.

Similarly, if the parallel length horizontal direction space between the fourth combined graphic 346 and the first combined graphic 334 does not satisfy the range of values of the parallel length between the different combined graphics indicated by the second constraint, the electronic device 110 may determine the target direction vertically upward. Additionally or alternatively, the electronic device 110 may determine a magnitude of displacement to move the fourth combined graphic 346 upward. The electronic device 110 may change the range of values of the parallel lengths by moving the fourth combined pattern 346 upward so as to be satisfactory. By setting the constraint condition of parallel length, the pattern can meet the technological requirement of chip manufacture.

Fig. 3C shows a process of performing position adjustment on the fourth combined pattern. If the electronic device 110 determines that the target direction of the fourth combined pattern 346 is vertically upward, as shown by the arrow in the layout 350 of fig. 3C, according to the second constraint listed above, the electronic device 110 may further determine the displacement magnitude of the fourth combined pattern 346. The electronic device 110 may move the fourth combined pattern 346 upward by the determined displacement magnitude to obtain an adjusted fourth combined pattern 356.

Taking the first combined pattern 334 and the adjusted fourth combined pattern 356 as examples above, several examples of adding combined patterns to the layout are shown. After adding and adjusting the first combined pattern 334 and the adjusted fourth combined pattern 356, the electronic device 110 may continue to add more combined patterns in the remaining to-be-updated area of the layout 350. For example, the electronic device 110 may gradually add more combined patterns in a bottom-up order until each region of the layout is filled (i.e., no new combined patterns satisfying the first constraint and the second constraint can be added). The mode of generating the combined graph from bottom to top region to region can ensure that each position region of the layout is filled with the combined graph.

It should be appreciated that while random patterns in the layout are generated herein in a bottom-up order, in some embodiments, any other order may be employed. For example, each combined graph may be generated from top to bottom. In addition, each of the combined patterns may be generated from left to right, or from right to left. The scope of the present disclosure is not limited in this respect.

The first or second constraints referred to herein relate to process requirements or limitations of integrated circuit or chip fabrication. It should be understood that the examples of the first or second constraints listed herein are merely exemplary and not limiting. More or fewer constraints may be employed to add or adjust the combined patterns in the layout. These constraints enable the combined patterns in the layout to meet the process requirements or limitations of integrated circuit or chip fabrication. The scope of the present disclosure is not limited in this respect.

By randomly generating individual combined patterns that meet a plurality of constraints by electronic device 110, the generated combined patterns can both satisfy a plurality of design rules or constraints and be automatically randomly generated. The combined graph has high randomness and diversity, and avoids the influence of subjective factors in the graph generation process. The layout comprising a plurality of combined patterns can simulate the actual layout more truly. In particular, in the case where the sample space is sufficiently large, a sufficient number of layouts composed of the combined patterns generated according to the embodiments of the present disclosure can be provided, thereby more effectively covering various scenes.

Fig. 4 shows a schematic diagram of a layout 400 resulting from the graph generation method of the present disclosure. The plurality of combined patterns fills the various regions of the layout 400. These combined patterns are added and repositioned according to aspects of the present disclosure. Each combined graph in the layout 400 can meet various design rules or constraints, and has high randomness and diversity.

By adopting the scheme to generate the combined graph in the layout, on one hand, the diversity of the layout graph can be improved, and therefore the manufacturing capacity of the existing production line can be explored and tested. On the other hand, the pattern generation method disclosed by the invention can be used for filling the blank area in the layout, so that the pattern distribution in the filled layout is more uniform, and the manufacturability of the layout is improved.

Fig. 5 illustrates a block diagram of an electronic device 500 in which one or more embodiments of the disclosure may be implemented. The electronic device 500 may be used, for example, to implement the electronic device 110 shown in fig. 1. It should be understood that the electronic device 500 shown in fig. 5 is merely exemplary and should not be construed as limiting the functionality and scope of the embodiments described herein.

As shown in fig. 5, the electronic device 500 is in the form of a general-purpose electronic device. The components of electronic device 500 may include, but are not limited to, one or more processors or processing units 510, memory 520, storage 530, one or more communication units 540, one or more input devices 550, and one or more output devices 560. The processing unit 510 may be a real or virtual processor and is capable of performing various processes according to programs stored in the memory 520. In a multiprocessor system, multiple processing units execute computer-executable instructions in parallel to improve the parallel processing capabilities of electronic device 500.

Electronic device 500 typically includes multiple computer storage media. Such a medium may be any available medium that is accessible by electronic device 500, including, but not limited to, volatile and non-volatile media, removable and non-removable media. The memory 520 may be volatile memory (e.g., registers, cache, random Access Memory (RAM)), non-volatile memory (e.g., read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory), or some combination thereof. Storage device 530 may be a removable or non-removable media and may include machine-readable media such as flash drives, magnetic disks, or any other media that may be capable of storing information and/or data (e.g., training data for training) and may be accessed within electronic device 500.

The electronic device 500 may further include additional removable/non-removable, volatile/nonvolatile storage media. Although not shown in fig. 5, a magnetic disk drive for reading from or writing to a removable, nonvolatile magnetic disk (e.g., a "floppy disk") and an optical disk drive for reading from or writing to a removable, nonvolatile optical disk may be provided. In these cases, each drive may be connected to a bus (not shown) by one or more data medium interfaces. Memory 520 may include a computer program product 525 having one or more program modules configured to perform the various methods or acts of the various embodiments of the present disclosure.

The communication unit 540 enables communication with other electronic devices through a communication medium. Additionally, the functionality of the components of electronic device 500 may be implemented in a single computing cluster or in multiple computing machines capable of communicating over a communication connection. Thus, the electronic device 500 may operate in a networked environment using logical connections to one or more other servers, a network Personal Computer (PC), or another network node.

The input device 550 may be one or more input devices such as a mouse, keyboard, trackball, etc. The output device 560 may be one or more output devices such as a display, speakers, printer, etc. The electronic device 500 may also communicate with one or more external devices (not shown), such as storage devices, display devices, etc., with one or more devices that enable a user to interact with the electronic device 500, or with any device (e.g., network card, modem, etc.) that enables the electronic device 500 to communicate with one or more other electronic devices, as desired, via the communication unit 540. Such communication may be performed via an input/output (I/O) interface (not shown).

According to an exemplary implementation of the present disclosure, a computer-readable storage medium is provided, on which one or more computer instructions are stored, wherein the one or more computer instructions are executed by a processor to implement the method described above.

Various aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer-readable program instructions.

These computer readable program instructions may be provided to a processing unit of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processing unit of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable medium having the instructions stored therein includes an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.

The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer, other programmable apparatus or other devices implement the functions/acts specified in the flowchart and/or block diagram block or blocks.

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various implementations of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

The foregoing description of implementations of the present disclosure has been provided for illustrative purposes, is not exhaustive, and is not limited to the implementations disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various implementations described. The terminology used herein was chosen in order to best explain the principles of each implementation, the practical application, or the improvement of technology in the marketplace, or to enable others of ordinary skill in the art to understand each implementation disclosed herein.

Claims

1. A pattern generation method, comprising:

adding a first combined graph in a region to be updated of the layout based at least on a first constraint condition for the layout, wherein the first combined graph comprises a plurality of connected sub-graphs, and the first constraint condition is associated with the layout among different sub-graphs in the combined graph; and

the position of the first combined graph in the area to be updated is adjusted based at least on a second constraint on the layout, the second constraint being associated with a layout between different combined graphs in the layout.

2. The pattern generation method according to claim 1, wherein adding the first combined pattern in the area to be updated includes:

adding a first sub-graph in the area to be updated; and

and adding a second sub-graph connected with the first sub-graph in the area to be updated based on at least the first constraint condition, wherein the first combined graph at least comprises the first sub-graph and the second sub-graph.

3. The graphics-generating method of claim 2, wherein the first constraint is associated with at least one of:

a first distance between different sub-patterns along a first direction,

a second distance of the different sub-patterns along a second direction, the second direction being perpendicular to the first direction,

angular diagonal distance between different sub-patterns,

the parallel length between the different sub-patterns,

and a predetermined range of graphics on the layout.

4. The pattern generation method according to claim 1, wherein the first constraint indicates a threshold number of sub-patterns in a combined pattern, and the number of sub-patterns included in the first combined pattern does not exceed the threshold number.

5. The pattern generation method according to claim 1, wherein adding a first combined pattern in a region to be updated of the layout comprises:

generating candidate sub-graphics for the first combined graphics;

determining the candidate sub-graph as one of the plurality of sub-graphs if it is determined that the candidate sub-graph satisfies the first constraint;

generating a new candidate sub-graph for the first combined graph if it is determined that the candidate sub-graph does not meet the first constraint; and

and stopping generating the candidate sub-graph for the first combined graph if the number of times of generating the candidate sub-graph for the first combined graph is determined to reach a threshold number of times.

6. The pattern generation method according to claim 1, characterized in that the method further comprises:

determining a first ratio between the outer perimeter and the effective area of the first combined pattern; and

and regenerating the first combined graph if the first ratio is determined not to meet the perimeter-area ratio constraint.

7. The graphics-generating method of claim 1, wherein the second constraint is associated with at least one of:

The distance between the different combined patterns along the first direction,

the distance between the different combined patterns along a second direction, the second direction being perpendicular to the first direction,

angular diagonal distance between different combined patterns,

parallel lengths between different combined patterns.

8. The pattern generation method according to claim 1, wherein adjusting the position of the first combined pattern in the area to be updated comprises:

determining whether the first combined graph and the second combined graph meet the second constraint condition based on the current position of the first combined graph in the layout and the known position of the second combined graph in the layout;

determining a target direction in the layout, in which the second constraint condition is satisfied, in response to the second constraint condition not being satisfied; and

the first combined pattern is moved in the target direction.

9. The pattern generation method according to claim 1, characterized by further comprising:

and adding a third combined graph in the area to be updated at least based on the first constraint condition and the second constraint condition.

10. The pattern generation method according to claim 1, characterized by further comprising:

Determining a first boundary of the area to be updated based on the boundary of the existing graph in the layout;

determining a second boundary based on the boundary of the layout; and

the area to be updated is determined based at least on the first boundary and the second boundary.

11. The pattern generation method according to claim 1, characterized by further comprising:

the first combined graph is used as an existing graph, and the area to be updated of the layout is redetermined; and

and adding a fourth combined graph in the redetermined area to be updated at least based on the first constraint condition and the second constraint condition.

12. An electronic device, comprising:

at least one processing unit; and

at least one memory coupled to the at least one processing unit and storing instructions for execution by the at least one processing unit, which when executed by the at least one processing unit, cause the electronic device to perform the method of any one of claims 1 to 11.

13. A computer readable storage medium having stored thereon a computer program, wherein the computer program is executable by a processor to implement the method of any of claims 1 to 11.