CN112882423B - Singlechip, singlechip control method and device, intelligent terminal and storage medium - Google Patents
Singlechip, singlechip control method and device, intelligent terminal and storage medium Download PDFInfo
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- G05B19/00—Programme-control systems
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Abstract
The invention discloses a single chip microcomputer, a single chip microcomputer control method, a single chip microcomputer control device, an intelligent terminal and a storage medium, wherein the single chip microcomputer comprises: the system comprises a target signal acquisition module, a target operation acquisition module and a target operation execution module; the target operation acquisition module is respectively in communication connection with the target signal acquisition module and the target operation execution module; the target signal acquisition module is used for acquiring a target signal; the target operation acquisition module is used for acquiring a target operation to be executed based on the target signal; the target operation execution module is used for executing the target operation. The single chip microcomputer provided by the scheme of the invention can acquire and execute the target operation to be executed through the target signal, thereby realizing the purpose of directly controlling the single chip microcomputer to execute the corresponding operation or enter the corresponding working mode through the target signal, being beneficial to reducing the complexity of the control of the single chip microcomputer and improving the stability and the reliability of the control.
Description
Technical Field
The invention relates to the technical field of integrated circuit chips, in particular to a single chip microcomputer, a single chip microcomputer control method, a single chip microcomputer control device, an intelligent terminal and a storage medium.
Background
The Micro Control Unit (MCU) is also called as a Micro Controller Unit (MCU) or a single chip microcomputer, and is a chip-level computer that appropriately reduces the frequency and specification of the cpu, and integrates the peripheral interfaces such as the memory, the counter, the USB, the a/D converter, the UART, the PLC, the DMA, and the LCD driver circuit on a single chip, thereby performing different combination Control for different applications. In the prior art, in order to meet the use requirements, a single chip microcomputer generally has abundant peripheral resources, and how to control the single chip microcomputer is realized, so that the realization of the reuse of the peripheral resources as required is more and more concerned.
In the prior art, a single chip microcomputer is generally controlled in a register configuration mode, so that the single chip microcomputer enters a special mode, and therefore, the purpose of multiplexing external resources as required is achieved. However, the scheme for controlling the configuration register is complex to operate, and when the single chip microcomputer is required to be adjusted back to the default state after entering some common special modes, the kernel can be maintained by a method only after the single chip microcomputer is powered on or reset, and a new program is written in, so that the operation requirement is high, and the success rate is low. Therefore, the prior art has the problems that the scheme for controlling the singlechip through the configuration register is complex in operation and low in stability and reliability.
Thus, there is still a need for improvement and development of the prior art.
Disclosure of Invention
The invention mainly aims to provide a single chip microcomputer, a single chip microcomputer control method and device, an intelligent terminal and a storage medium, and aims to solve the problems that in the prior art, a scheme for controlling the single chip microcomputer in a register configuration mode is complex in operation and low in stability and reliability.
In order to achieve the above object, a first aspect of the present invention provides a single chip microcomputer, wherein the single chip microcomputer includes:
the system comprises a target signal acquisition module, a target operation acquisition module and a target operation execution module;
the target operation acquisition module is respectively in communication connection with the target signal acquisition module and the target operation execution module;
the target signal acquisition module is used for acquiring a target signal;
the target operation acquisition module is used for acquiring a target operation to be executed based on the target signal;
the target operation execution module is used for executing the target operation.
Optionally, the single chip microcomputer further includes a target pin in communication connection with the target signal acquisition module, and the target signal acquisition module includes:
the pin monitoring unit is used for monitoring a target pin of the singlechip in real time;
and the target signal acquisition unit is used for receiving and acquiring the target signal based on the target pin.
Optionally, the target pin includes all non-power pins of the single chip.
Optionally, the target signal includes: a predetermined target sequence signal and/or a predetermined target enable signal.
Optionally, the target operation obtaining module includes:
a target signal analysis unit for analyzing the target signal to obtain an analysis result;
and the target operation matching unit is used for matching and acquiring the corresponding target operation in a preset operation function library based on the analysis result.
Optionally, the target operation includes: and restoring the burning interface multiplexed with the IO function into default configuration, restoring the reset pin multiplexed with the IO function into default configuration, and setting the power-on starting sequence of the single chip microcomputer.
A second aspect of the present invention provides a method for controlling a single chip microcomputer, where the method is applied to any one of the single chip microcomputers, and the method includes:
generating a target signal;
and sending the target signal to the singlechip to trigger the singlechip to acquire the target signal, acquiring a target operation to be executed based on the target signal, and executing the target operation.
A third aspect of the present invention provides a single chip microcomputer control apparatus, which is applied to any one of the single chip microcomputers described above, wherein the apparatus includes:
a target signal generation module for generating a target signal;
and the target signal sending module is used for sending the target signal to the singlechip so as to trigger the singlechip to acquire the target signal, acquire a target operation to be executed based on the target signal and execute the target operation.
A fourth aspect of the present invention provides an intelligent terminal, where the intelligent terminal includes a memory, a processor, and a single-chip microcomputer control program stored in the memory and operable on the processor, and the single-chip microcomputer control program implements the steps of the single-chip microcomputer control method when executed by the processor.
A fifth aspect of the present invention provides a computer-readable storage medium, where a single-chip microcomputer control program is stored on the computer-readable storage medium, and the single-chip microcomputer control program, when executed by a processor, implements the steps of the single-chip microcomputer control method.
The single chip microcomputer provided by the scheme of the invention comprises a target signal acquisition module, a target operation acquisition module and a target operation execution module; the target operation acquisition module is respectively in communication connection with the target signal acquisition module and the target operation execution module; the target signal acquisition module is used for acquiring a target signal; the target operation acquisition module is used for acquiring a target operation to be executed based on the target signal; the target operation execution module is used for executing the target operation. The single chip microcomputer provided by the scheme of the invention can acquire and execute the target operation to be executed through the target signal, thereby realizing the control of the corresponding single chip microcomputer directly through the target signal, being beneficial to reducing the complexity of the control of the single chip microcomputer and improving the stability and the reliability of the control.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
Fig. 1 is a schematic structural diagram of a single chip microcomputer provided in an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of another single chip microcomputer provided in the embodiment of the present invention;
fig. 3 is a schematic structural diagram of the target signal obtaining module 110 in fig. 2 according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of the target operation obtaining module 120 in fig. 2 according to an embodiment of the present invention;
fig. 5 is a schematic flow chart of a method for controlling a single chip microcomputer according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a single chip microcomputer control device provided in the embodiment of the present invention;
fig. 7 is a schematic diagram of a single chip microcomputer controlled by a target signal generator according to an embodiment of the present invention;
FIG. 8 is a schematic flow chart of a single chip microcomputer control provided in the embodiment of the present invention;
fig. 9 is a schematic block diagram of an internal structure of an intelligent terminal according to an embodiment of the present invention.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the specification of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be further understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.
As used in this specification and the appended claims, the term "if" may be interpreted contextually as "when …" or "upon" or "in response to a determination" or "in response to a detection". Similarly, the phrase "if it is determined" or "if a [ described condition or event ] is detected" may be interpreted depending on the context to mean "upon determining" or "in response to determining" or "upon detecting [ described condition or event ]" or "in response to detecting [ described condition or event ]".
The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the drawings of the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described and will be readily apparent to those of ordinary skill in the art without departing from the spirit of the present invention, and therefore the present invention is not limited to the specific embodiments disclosed below.
A Micro Control Unit (MCU), also called a Single-Chip Microcomputer (cpu), or a Single-Chip Microcomputer (MCU), which properly reduces the frequency and specification of a cpu, and integrates a memory, a counter, a USB, a/D conversion, UART, PLC, DMA, and other peripheral interfaces, even an LCD driving circuit, on a Single Chip to form a Chip-level computer, which performs different combination Control for different applications. In the prior art, in order to meet the use requirement, the single chip microcomputer generally has rich peripheral resources, but the more rich the peripheral resources, the higher the corresponding price is. Scheme end and terminal user will hope to develop high-quality, low-cost product based on the characteristic of singlechip, for example can get into certain special mode to realize the singlechip that a plurality of peripheral hardware resource multiplex as required. However, how to make the single chip microcomputer enter a certain special mode by a terminal user to realize the maximization of resource utilization is an urgent problem to be solved.
In the prior art, a single chip microcomputer is generally controlled in a register configuration mode, so that the single chip microcomputer enters a special mode, and therefore, the purpose of multiplexing external resources as required is achieved. However, the scheme for controlling the configuration register is complex to operate, and when the single chip microcomputer is required to be adjusted back to the default state after entering some common special modes, the kernel can be maintained by a method only after the single chip microcomputer is powered on or reset, and a new program is written in, so that the operation requirement is high, and the success rate is low. Therefore, the scheme for controlling the singlechip through the configuration register has complex operation and low stability and reliability. In another application scenario of the prior art, a delay is added before the configuration of the configuration special register, so that the user can update the program with the delay. However, in the scheme, after the single chip microcomputer is awakened from low power consumption, corresponding operation can be executed and functions can be realized only after waiting for delay, and the user waiting time is long, so that the user experience is influenced. Therefore, a better method for controlling the single chip microcomputer is needed.
In order to solve the problems in the prior art, an embodiment of the present invention provides a single chip microcomputer, where in the embodiment of the present invention, the single chip microcomputer includes a target signal obtaining module, a target operation obtaining module, and a target operation executing module; the target operation acquisition module is respectively in communication connection with the target signal acquisition module and the target operation execution module; the target signal acquisition module is used for acquiring a target signal; the target operation acquisition module is used for acquiring a target operation to be executed based on the target signal; the target operation execution module is used for executing the target operation. The single chip microcomputer provided by the scheme of the invention can acquire and execute the target operation to be executed through the target signal, thereby realizing the purpose of directly controlling the single chip microcomputer to execute the corresponding operation or enter the corresponding working mode through the target signal, being beneficial to reducing the complexity of the control of the single chip microcomputer and improving the stability and the reliability of the control.
As shown in fig. 1, an embodiment of the present invention provides a single chip microcomputer 100, and specifically, the single chip microcomputer 100 includes:
a target signal acquisition module 110, a target operation acquisition module 120 and a target operation execution module 130;
the target operation acquiring module 120 is in communication connection with the target signal acquiring module 110 and the target operation executing module 130 respectively;
the target signal acquiring module 110 is configured to acquire a target signal;
the target operation acquiring module 120 is configured to acquire a target operation to be performed based on the target signal;
the target operation executing module 130 is configured to execute the target operation.
The target signal is a preset signal used for indicating a special operation (or a special working mode) which needs to be executed by the singlechip, and the target operation is the special operation (or the special working mode) which needs to be executed by the singlechip. Specifically, a corresponding relationship is preset between the target signal and the target operation, and the target operation to be executed by the single chip microcomputer can be correspondingly acquired according to the target signal.
After the target signal obtaining module 110 obtains the target signal, the target signal may be transmitted to the target operation obtaining module 120. Further, the target operation obtaining module 120 obtains a corresponding target operation that the single chip microcomputer should execute according to a preset corresponding relationship between a target signal and the target operation, and then transmits the corresponding target operation to the target operation executing module 130, and the target operation executing module 130 executes the corresponding target operation, so as to adjust and control the single chip microcomputer, thereby enabling the single chip microcomputer 100 to enter a special working mode.
Specifically, in the embodiment of the present invention, only some modules (the target signal obtaining module 110, the target operation obtaining module 120, and the target operation executing module 130) of the single chip microcomputer 100 are disclosed, and other modules or units for implementing basic functions of the single chip microcomputer are not specifically disclosed, and in combination with the prior art, a person skilled in the art can understand according to actual situations that the single chip microcomputer 100 further has functional modules for implementing other specific functions, and can increase or decrease according to actual needs, which is not specifically limited herein.
Optionally, the target operation executing module 130 is further configured to: and after the target operation is successfully executed, feeding back success information so that the user can know the execution condition of the target operation and carry out the next operation.
As can be seen from the above, the single chip microcomputer 100 provided in the embodiment of the present invention includes a target signal obtaining module 110, a target operation obtaining module 120, and a target operation executing module 130; the target operation acquiring module 120 is in communication connection with the target signal acquiring module 110 and the target operation executing module 130 respectively; the target signal acquiring module 110 is configured to acquire a target signal; the target operation acquiring module 120 is configured to acquire a target operation to be performed based on the target signal; the target operation executing module 130 is configured to execute the target operation. The single chip microcomputer 100 provided by the scheme of the invention can acquire and execute the target operation to be executed through the target signal, thereby realizing the purpose of directly controlling the single chip microcomputer 100 to execute the corresponding operation or enter the corresponding working mode through the target signal, being beneficial to reducing the complexity of the control of the single chip microcomputer 100 and improving the stability and the reliability of the control.
Specifically, in this embodiment, as shown in fig. 2, the single chip microcomputer 100 further includes a target pin 140 communicatively connected to the target signal obtaining module 110, and as shown in fig. 3, the target signal obtaining module 110 includes:
a pin monitoring unit 111, configured to monitor the target pin 140 of the single chip microcomputer 100 in real time;
a target signal obtaining unit 112, configured to obtain the target signal based on the target pin 140.
In this embodiment, the target pins 140 include all non-power pins of the single chip microcomputer 100, and in an actual use process, one or more non-power pins of the single chip microcomputer 100 may also be designated as the target pins 140, so as to reduce the number of pins to be monitored, which is not specifically limited herein.
Optionally, the target signal includes: a predetermined target sequence signal and/or a predetermined target enable signal. The target sequence signal and the preset target enable signal are respectively a preset section of complex time sequence and a section of enable signal, the corresponding target signal can be preset according to the target operation set by actual needs, and the corresponding target operation can be executed when the single chip microcomputer 100 receives the target signal. Specifically, the target signal may be composed of a complex timing sequence and an enable signal, or may be a single complex timing sequence or an enable signal. Optionally, when the target signal may be formed by combining a complicated time sequence and an enable signal, the signal corresponding to the complicated time sequence may be further recognized only after the single chip microcomputer 100 recognizes the target enable signal. The enable signal may be a fixed timing sequence or a high-low level. The specific arrangement of the above signals depends on the actual requirements and is not limited in any way.
Specifically, all the non-power pins (target pins 140) of the single chip microcomputer 100 may receive an external special signal (i.e., a target signal), so as to obtain a corresponding special function (i.e., a target operation) according to the special signal, further implement the corresponding special function, and implement the control of the single chip microcomputer to switch the working mode or execute some special operations through the external special signal.
Specifically, in this embodiment, as shown in fig. 4, the target operation obtaining module 120 includes:
a target signal analyzing unit 121 configured to analyze the target signal to obtain an analysis result;
and a target operation matching unit 122, configured to match and acquire a corresponding target operation in a preset operation function library based on the analysis result.
The target signal analyzing unit 121 may be a decoder, and configured to perform decoding analysis on the target signal to obtain an analysis result, and send the analysis result to the target operation matching unit 122, so that the target operation matching unit 122 may match a corresponding target operation according to the analysis result.
In this embodiment, an operation function library is preset in the single chip microcomputer 100, and the operation function library stores all target operations that may need to be executed and corresponding analysis results thereof, and when the single chip microcomputer 100 receives a corresponding target signal and analyzes the target signal to obtain a corresponding analysis result, the corresponding target operations may be obtained according to the analysis result, so as to execute the target operations. Optionally, the analysis result and the target operation may be stored in the single chip microcomputer 100 in a table form, or other associated storage manners may also be provided, which is not specifically limited herein.
Optionally, the target operation matching unit 122 is further configured to: and when the operation is not matched with the corresponding target operation, feeding back error information so as to facilitate the adjustment and control of a user.
Optionally, the target operation includes: and restoring the burning interface multiplexed with the IO function into default configuration, restoring the reset pin multiplexed with the IO function into default configuration, and setting the power-on starting sequence of the single chip microcomputer. In actual use, the target operation may also include other operations, which are not specifically limited herein.
Optionally, the correspondence between the target signal and the target operation may be one-to-one or many-to-one, that is, one target signal may correspond to one target operation, or multiple target signals may correspond to the same target operation. In this embodiment, the target signals and the target operations are in a one-to-one relationship, and one target signal corresponds to one target operation.
In an application scenario, the corresponding relationship between the target signal and the target operation may also be directly stored in the single chip microcomputer 100, and the corresponding target operation is directly obtained according to the target signal without analysis after the target signal is received. For example, the operation function library is preset in the single chip microcomputer 100, and the corresponding relationship is stored in the operation function library: "enable signal 0101 … 1010(32bit) + complex timing 1010 … 1001(64 bit)", corresponding to: restoring the burning interface multiplexed as IO to default configuration; "enable signal 0101 … 1010(32bit) + complex timing 1010 … 1010(64 bit)", corresponding to: restoring a reset pin (NRST) multiplexed as an IO function to a default configuration; "enable signal 0101 … 1010(32bit) + complex timing 1010 … 1011(64 bit)" corresponds to: and setting the power-on starting sequence of the singlechip. The specific target signal, the specific target operation and the corresponding relationship thereof are only examples, and may be adjusted according to actual requirements in actual use.
In this embodiment, the target signal analyzing unit 121 may analyze the target signal into a preset code, as an analysis result, for example, "enable signal 0101 … 1010(32bit) + complex timing 1010 … 1001(64 bit)" is analyzed into code "0001", and the preset operation function library stores a corresponding relationship between each analysis result and the target operation, for example, "0001" corresponds "and restores the burning interface multiplexed as IO to the default configuration, so that the single chip microcomputer 100 executes the target operation" restore the burning interface multiplexed as IO to the default configuration "after receiving the target signal" enable signal 0101 … 1010(32bit) + complex timing 1010 … 1001(64bit) ".
Specifically, as shown in fig. 5, the present embodiment further provides a method for controlling a single chip microcomputer, which is applied to any one of the single chip microcomputers 100, where the method includes:
step S10, generating a target signal;
step S20, sending the target signal to the single chip to trigger the single chip to obtain the target signal, obtaining a target operation to be executed based on the target signal, and executing the target operation.
Optionally, the target operation executed by the single chip microcomputer 100 may be controlled as required, and the target signal generator generates the corresponding target signal. The target signal generator may be an online or offline recorder with a corresponding target signal generating function, or may be a dedicated signal generator, which is not limited herein.
The target signal includes a preset target sequence signal and/or a preset target enable signal, and the target operation includes: and restoring the burning interface multiplexed with the IO function into default configuration, restoring the reset pin multiplexed with the IO function into default configuration, and setting the power-on starting sequence of the single chip microcomputer. The specific target signal form and the corresponding relationship with the target operation are shown in the above embodiments, and are not described herein again.
Specifically, in step S20, a target signal is sent to the target pin 140 of the single chip microcomputer 100 to trigger the target signal obtaining module 110 of the single chip microcomputer 100 to obtain the target signal through the target pin 140. The target pin 140 includes all non-power pins of the single chip microcomputer 100. Further, the specific process of the single chip microcomputer 100 obtaining and executing the target operation based on the target signal is shown in the above embodiments, and is not described herein again.
Specifically, as shown in fig. 6, corresponding to the above-mentioned single chip microcomputer control method, this embodiment further provides a single chip microcomputer control device, which is applied to any one of the above-mentioned single chip microcomputers 100, and the above-mentioned device includes:
a target signal generation module 210 for generating a target signal;
and a target signal sending module 220, configured to send the target signal to the single chip to trigger the single chip to obtain the target signal, obtain a target operation to be executed based on the target signal, and execute the target operation.
Optionally, the target signal generating module 210 may control the target operation executed by the single chip microcomputer 100 to generate a corresponding target signal according to a requirement. The target signal generating module 210 may be an online or offline burner having a corresponding target signal generating function, or may be a dedicated signal generator, which is not limited herein.
The target signal includes a preset target sequence signal and/or a preset target enable signal, and the target operation includes: and restoring the burning interface multiplexed with the IO function into default configuration, restoring the reset pin multiplexed with the IO function into default configuration, and setting the power-on starting sequence of the single chip microcomputer. The specific target signal form and the corresponding relationship with the target operation are shown in the above embodiments, and are not described herein again.
Specifically, the target signal sending module 220 is specifically configured to: and sending a target signal to a target pin 140 of the single chip microcomputer 100 to trigger a target signal obtaining module 110 of the single chip microcomputer 100 to obtain the target signal through the target pin 140. The target pin 140 includes all non-power pins of the single chip microcomputer 100. Further, the specific process of the single chip microcomputer 100 obtaining and executing the target operation based on the target signal is shown in the above embodiments, and is not described herein again.
Optionally, the division of the modules and units of the single chip microcomputer 100 disclosed in this embodiment is not used to limit the protection scope of the present invention, and in practical application, the functions may be distributed by different functional units and modules according to needs, that is, the internal structure of the apparatus is divided into different functional units or modules to complete all or part of the functions described above. Fig. 7 is a schematic diagram of controlling a single chip microcomputer through a target signal generator according to an embodiment of the present invention, as shown in fig. 7, the target signal generator generates a target signal and sends the target signal to the single chip microcomputer, the single chip microcomputer includes a target signal logic analyzing module and a target operation executing module, and the target signal logic analyzing module includes a signal receiver for receiving the target signal and a decoder for analyzing the target signal and obtaining an analysis result; and the target operation execution module acquires the corresponding target operation from a preset operation function library according to the analysis result and executes the corresponding target operation through the target operation execution unit. Fig. 8 is a schematic flowchart of a control process of a single chip microcomputer according to an embodiment of the present invention, and as shown in fig. 8, after the single chip microcomputer starts to operate, if a target signal is received, the target signal is analyzed and a target operation is obtained by matching. When the target operation is matched, the corresponding target operation is executed, otherwise, error information can be fed back.
Specifically, the embodiment of the invention also discloses a plurality of examples of target operation executed by the singlechip in specific application scenes.
In an application scenario, a terminal user of an MCU (single chip microcomputer) reuses a burning interface of the MCU into IO ports, so that more IO ports of the MCU come out, and excellent products can be designed more flexibly and conveniently for the user. In this case, when the user needs to perform program burning again, since the burning interface is already multiplexed as the IO port, the MCU burning program does not work, and the burning interface that is already multiplexed as the IO port needs to be returned to the default setting. In the prior art, the reset key can be pressed, and after the IDCODE of the MCU is identified, the reset key is released, so that the MCU can be burnt. However, this method is unstable, and the user can burn the program once in a while, and needs to know the timing of releasing the reset button. Or, before configuring the MCU burning interface as the IO port, adding a delay of more than 100ms, and after the MCU is powered on again, during waiting for the delay, the function of the burning interface is not multiplexed as the IO port, so that a new program can be updated in the time, which is unacceptable for time-sensitive users. However, with the adoption of the scheme of the invention, after the program burning interface is configured as the IO port, the external target signal generator can generate a group of target signals (signals corresponding to target operation for recovering the default configuration of the burning interface) to any pins of the non-power supply signal of the MCU. And after the MCU feedback function is successfully executed, the burner can execute the normal burning process again.
In another application scenario, when the NRST reset pin is also configured as the IO port, the default configuration is to be restored again, which can only be solved by adding a delay of more than 100ms before configuring the MCU burning interface as the IO port based on the prior art. However, with the scheme of the present invention, after the program burning interface and the NRST reset pin are configured as IO ports, a set of target signals (signals corresponding to target operations for restoring the default configuration of the burning interface and the NRST reset pin) can be generated by the external target signal generator to any pin of the MCU that is not a power supply signal. And after the MCU feedback function is successfully executed, the burner can execute the normal burning process again. Further, after any other non-power class pin is multiplexed into other functions, the default configuration can be restored through the above scheme, which is not described herein again.
In another application scenario, an MCU designed and produced by a certain factory does not have a commonly used boot pin, so that a user can only determine the boot bit of the option byte by configuring the boot bit of the option byte when the MCU is powered on. Typical startup modes after the MCU is powered on include, but are not limited to: from SRAM boot, system info field boot, and FLASH boot. For example, after the MCU is powered on, the MCU is to be started from a system info area to enter a boot mode, and when the ISP is upgraded, the configuration method in the prior art needs to rewrite the address of the option byte through a burning interface via an external host (which may be an upper computer of a PC or other MCU), so that the operation is inconvenient. And the scheme of the invention is adopted: when the MCU needs to be upgraded by the ISP, an external target signal generator may generate a set of target signals (signals corresponding to target operations for setting the power-on start sequence of the MCU, for example, signals corresponding to target operations for setting the preferential start mode of the MCU to start from the system info area) to pins of any non-power signals of the MCU. And after the MCU feedback function is successfully executed, the burner can be upgraded by the ISP.
Based on the above embodiment, the present invention further provides an intelligent terminal, and a schematic block diagram thereof may be as shown in fig. 9. The intelligent terminal comprises a processor, a memory, a network interface and a display screen which are connected through a system bus. Wherein, the processor of the intelligent terminal is used for providing calculation and control capability. The memory of the intelligent terminal comprises a nonvolatile storage medium and an internal memory. The nonvolatile storage medium stores an operating system and a one-chip microcomputer control program. The internal memory provides an environment for the operating system and the running of the single chip microcomputer control program in the nonvolatile storage medium. The network interface of the intelligent terminal is used for being connected and communicated with an external terminal through a network. The steps of any one of the singlechip control methods are realized when the singlechip control program is executed by the processor. The display screen of the intelligent terminal can be a liquid crystal display screen or an electronic ink display screen.
It will be understood by those skilled in the art that the block diagram of fig. 9 is only a block diagram of a part of the structure related to the solution of the present invention, and does not constitute a limitation to the intelligent terminal to which the solution of the present invention is applied, and a specific intelligent terminal may include more or less components than those shown in the figure, or combine some components, or have different arrangements of components.
In one embodiment, an intelligent terminal is provided, where the intelligent terminal includes a memory, a processor, and a single-chip microcomputer control program stored in the memory and executable on the processor, and the single-chip microcomputer control program performs the following operation instructions when executed by the processor:
generating a target signal;
and sending the target signal to the singlechip to trigger the singlechip to acquire the target signal, acquiring a target operation to be executed based on the target signal, and executing the target operation.
The embodiment of the invention also provides a computer readable storage medium, wherein a singlechip control program is stored on the computer readable storage medium, and the steps of any one of the singlechip control methods provided by the embodiment of the invention are realized when the singlechip control program is executed by a processor.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional units and modules is illustrated, and in practical applications, the above-mentioned functions may be distributed as different functional units and modules according to needs, that is, the internal structure of the apparatus may be divided into different functional units or modules to implement all or part of the above-mentioned functions. Each functional unit and module in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one unit, and the integrated unit may be implemented in a form of hardware, or in a form of software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present invention. The specific working processes of the units and modules in the system may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.
Those of ordinary skill in the art would appreciate that the elements and algorithm steps of the examples described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
In the embodiments provided in the present invention, it should be understood that the disclosed apparatus/terminal device and method may be implemented in other ways. For example, the above-described embodiments of the apparatus/terminal device are merely illustrative, and for example, the division of the above modules or units is only one logical division, and the actual implementation may be implemented by another division, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed.
The integrated modules/units described above, if implemented in the form of software functional units and sold or used as separate products, may be stored in a computer readable storage medium. Based on such understanding, all or part of the flow of the method according to the embodiments of the present invention may also be implemented by a computer program, which may be stored in a computer-readable storage medium and can implement the steps of the embodiments of the method when the computer program is executed by a processor. The computer program includes computer program code, and the computer program code may be in a source code form, an object code form, an executable file or some intermediate form. The computer readable medium may include: any entity or device capable of carrying the above-mentioned computer program code, recording medium, usb disk, removable hard disk, magnetic disk, optical disk, computer Memory, Read-Only Memory (ROM), Random Access Memory (RAM), electrical carrier wave signal, telecommunication signal, software distribution medium, etc. It should be noted that the contents contained in the computer-readable storage medium can be increased or decreased as required by legislation and patent practice in the jurisdiction.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art; the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the embodiments of the present invention, and they should be construed as being included therein.
Claims (10)
1. A single chip microcomputer is characterized by comprising:
the system comprises a target signal acquisition module, a target operation acquisition module and a target operation execution module;
the target operation acquisition module is respectively in communication connection with the target signal acquisition module and the target operation execution module;
the target signal acquisition module is used for acquiring a target signal;
the target operation acquisition module is used for acquiring a target operation to be executed based on the target signal;
the target operation execution module is used for executing the target operation and feeding back success information after the target operation is successfully executed;
and the target operation comprises the step of restoring the burning interface multiplexed as the IO function to default configuration.
2. The single chip microcomputer according to claim 1, further comprising a target pin communicatively connected to the target signal obtaining module, wherein the target signal obtaining module comprises:
the pin monitoring unit is used for monitoring a target pin of the singlechip in real time;
and the target signal acquisition unit is used for receiving and acquiring the target signal based on the target pin.
3. The single-chip microcomputer according to claim 2, wherein the target pins include all non-power class pins of the single-chip microcomputer.
4. The single chip microcomputer according to claim 1, wherein the target signal includes: a predetermined target sequence signal and/or a predetermined target enable signal.
5. The single chip microcomputer according to any one of claims 1 to 4, wherein the target operation acquiring module includes:
the target signal analysis unit is used for analyzing the target signal to obtain an analysis result;
and the target operation matching unit is used for matching and acquiring corresponding target operation in a preset operation function library based on the analysis result.
6. The single-chip microcomputer according to claim 1, wherein the target operation further comprises: and restoring the reset pin multiplexed as the IO function to default configuration, and setting the power-on starting sequence of the single chip microcomputer.
7. A method for controlling a single chip microcomputer, wherein the method is applied to the single chip microcomputer according to any one of claims 1 to 6, and the method comprises the following steps:
generating a target signal;
sending the target signal to the single chip microcomputer to trigger the single chip microcomputer to acquire the target signal, acquiring target operation to be executed based on the target signal, executing the target operation, and feeding back success information after the target operation is executed successfully;
and the target operation comprises the step of restoring the burning interface multiplexed as the IO function to default configuration.
8. A single chip microcomputer control device, characterized in that the device is applied to the single chip microcomputer of any one of claims 1 to 6, and the device comprises:
a target signal generation module for generating a target signal;
the target signal sending module is used for sending the target signal to the single chip microcomputer so as to trigger the single chip microcomputer to acquire the target signal, acquiring target operation to be executed based on the target signal, executing the target operation and feeding back success information after the target operation is executed successfully;
and the target operation comprises the step of restoring the burning interface multiplexed as the IO function to default configuration.
9. An intelligent terminal, characterized in that the intelligent terminal comprises a memory, a processor and a single-chip microcomputer control program stored on the memory and capable of running on the processor, wherein the single-chip microcomputer control program realizes the steps of the single-chip microcomputer control method according to claim 7 when executed by the processor.
10. A computer-readable storage medium, wherein a single-chip microcomputer control program is stored on the computer-readable storage medium, and when executed by a processor, the single-chip microcomputer control program implements the steps of the single-chip microcomputer control method according to claim 7.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101127014A (en) * | 2006-08-15 | 2008-02-20 | 中兴通讯股份有限公司 | Device and method for initiating code chip on-board burning for processor system |
| US8453004B2 (en) * | 2006-06-21 | 2013-05-28 | Denso Corporation | Microcomputer with reset pin and electronic control unit with the same |
| CN105664221A (en) * | 2016-04-15 | 2016-06-15 | 镇江市高等专科学校 | Single-chip-microcomputer-based control system for wireless ultraviolet LED array |
| CN109324838A (en) * | 2018-08-31 | 2019-02-12 | 深圳市元征科技股份有限公司 | Execution method, executive device and the terminal of SCM program |
| US10571518B1 (en) * | 2018-09-26 | 2020-02-25 | Nxp B.V. | Limited pin test interface with analog test bus |
| CN111538488A (en) * | 2020-04-17 | 2020-08-14 | 荏原冷热系统（中国）有限公司 | Method and device for generating single-chip microcomputer driving program |
| CN111857304A (en) * | 2020-07-28 | 2020-10-30 | 山东云海国创云计算装备产业创新中心有限公司 | Chip reset control method, device, equipment and storage medium |
-
2021
- 2021-01-26 CN CN202110104643.0A patent/CN112882423B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8453004B2 (en) * | 2006-06-21 | 2013-05-28 | Denso Corporation | Microcomputer with reset pin and electronic control unit with the same |
| CN101127014A (en) * | 2006-08-15 | 2008-02-20 | 中兴通讯股份有限公司 | Device and method for initiating code chip on-board burning for processor system |
| CN105664221A (en) * | 2016-04-15 | 2016-06-15 | 镇江市高等专科学校 | Single-chip-microcomputer-based control system for wireless ultraviolet LED array |
| CN109324838A (en) * | 2018-08-31 | 2019-02-12 | 深圳市元征科技股份有限公司 | Execution method, executive device and the terminal of SCM program |
| US10571518B1 (en) * | 2018-09-26 | 2020-02-25 | Nxp B.V. | Limited pin test interface with analog test bus |
| CN110954808A (en) * | 2018-09-26 | 2020-04-03 | 恩智浦有限公司 | Limited pin test interface with analog test bus |
| CN111538488A (en) * | 2020-04-17 | 2020-08-14 | 荏原冷热系统（中国）有限公司 | Method and device for generating single-chip microcomputer driving program |
| CN111857304A (en) * | 2020-07-28 | 2020-10-30 | 山东云海国创云计算装备产业创新中心有限公司 | Chip reset control method, device, equipment and storage medium |
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