CN112864280A - High-reliability double-sided battery and preparation method thereof - Google Patents

High-reliability double-sided battery and preparation method thereof Download PDF

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CN112864280A
CN112864280A CN202110129157.4A CN202110129157A CN112864280A CN 112864280 A CN112864280 A CN 112864280A CN 202110129157 A CN202110129157 A CN 202110129157A CN 112864280 A CN112864280 A CN 112864280A
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silicon
layer
protective layer
silicon oxide
battery
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黄智�
张�林
张鹏
黄水华
胡耀霆
张世昌
徐涛
顾峰
翟绪锦
谢泰宏
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Tongwei Solar Hefei Co Ltd
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Abstract

The invention discloses a high-reliability double-sided battery and a preparation method thereof, and belongs to the technical field of solar batteries. According to the preparation method of the high-reliability double-sided battery, the silicon oxide protective layer is prepared on the back surface of the battery in an ALD or PEALD mode; the silicon-based precursor during the deposition of the silicon oxide protective layer is any one of hexachlorodisilane, disilane, trisilane and trisilylamine; the oxidant precursor is ozone or oxygen. By adopting the technical scheme of the invention, the back PID problem of the double-sided battery can be effectively improved, and the long-term stability of the battery piece is further improved.

Description

High-reliability double-sided battery and preparation method thereof
Technical Field
The invention belongs to the technical field of solar cells, and particularly relates to a high-reliability double-sided cell and a preparation method thereof.
Background
Potential Induced Degradation (PID) refers to a phenomenon that a solar cell module undergoes power degradation under a certain external voltage for a long time. This phenomenon was first discovered in 2005 by the company Sunpower. According to statistics of relevant authorities, the maximum attenuation of the power generation amount of the photovoltaic power station caused by PID can reach more than 30%, the attenuation becomes one of the main reasons of the attenuation of the output efficiency of the photovoltaic power station, and the attenuation becomes a major problem of component application.
With respect to the mechanism of PID failure, the following is widely studied and acknowledged in the industry: in grid power generation, a number of photovoltaic modules are connected in series to achieve the required voltage. In the design of the power station, for safety, the component frame is grounded, so that a large potential difference is formed between the battery piece and the glass and between the battery piece and the frame. Under the long-term working condition of the assembly in the high-voltage, humid and high-temperature ambient environment, water vapor enters the assembly through the edge sealing silica gel or the back plate, EVA (ethylene-vinyl acetate copolymer) in the packaging material of the assembly is hydrolyzed to generate acetic acid, and the acetic acid and alkali (Na) precipitated from the surface of glass2CO3) The reaction producing alkali metal ions, e.g. Na, which are free to move+Under the action of an electric field, Na+SiN moving to the surface of the battery and penetrating the surface of the battery piecexThe passivation anti-reflection layer migrates into the cell structure again, thereby destroying the performance of the semiconductor PN junction playing a key role in photoelectric conversion and even leading to the component delamination phenomenon under severe conditions. The above alkali metal ions generated from the package sealing materialUnder negative bias, the failure mechanism of performance attenuation such as leakage and the like caused by damaging the PN junction on the front side of the P-type battery piece is named by PID-S in the industry so as to be different from the failure (PID-P) of PID caused by polarization on the back side of a P-type double-sided battery or the front side of an N-type battery.
Aiming at the problem of slowing down PID-S attenuation, the main approach is to improve by a method for reducing or preventing alkali metal ions from migrating into the silicon wafer: firstly, the type and grounding mode of the component inverter and the optimization of the component array arrangement reduce or eliminate the negative bias on the surface of the battery plate; optimizing the packaging material of the component, such as improving the resistivity of the packaging material and reducing the water vapor transmittance by EVA modification or replacing EVA with POE (polyolefin elastomer), thereby reducing leakage current, reducing or even eliminating the generation of acetic acid, reducing the generation of alkali metal ions and slowing down the migration rate of the alkali metal ions; optimizing the battery process, for example, forming a layer of compact silicon oxide on the surface of the silicon wafer in the modes of thermal oxygen, ozone, PECVD and the like, and blocking alkali metal ions from entering the silicon wafer; the front antireflection film adopts a silicon nitride film structure with a high refractive index, so that the conductivity of silicon nitride is improved, and the accumulation of alkali metal ions on the silicon nitride and the silicon surface and the quantity of alkali metal ions migrating into the silicon wafer are reduced. There are many patents related to the above related measures or technologies, such as granted patent CN104538486B, which provides a method for improving the PID-S resistance of a cell by growing a layer of silicon oxide on the surface of a silicon wafer with laughing gas; granted patent CN104916710B provides a method for improving the PID-S resistance of a cell by overlapping an outer layer of a three-layer silicon nitride film with a silicon oxynitride composite anti-reflection film.
On the other hand, the double-sided PERC battery can be produced only by slightly changing the existing PERC battery and assembly production line, and the system power generation benefit can be increased by 5% -25% compared with a single-sided PERC battery assembly product, so that the double-sided PERC battery technology is gradually popularized and applied in a large scale. With the deep research and application of the double-sided PERC technology in the photovoltaic industry, the PID problem of the back side of the double-sided PERC battery is gradually highlighted. At present, under the standard test conditions of-1500V, 85% humidity and 85 ℃ (IEC61215 or UL1703 standard), the PID attenuation of the front side of the double-sided battery piece is about 3%, while the PID attenuation of the back side of the double-sided battery piece is as high as 5% -10%, even higher.
The PID failure mechanism of the back of the double-sided battery is widely researched in the industry, but the specific failure mechanism is not completely clear, and the possible failure causes have the following aspects: polarization by silicon nitride (PID-P): k-center in the back silicon nitride film layer under the action of electric field0，K-Conversion to K+Inherent and newly added K+The formed electric field weakens the field passivation effect caused by negative charges in the aluminum oxide passivation layer, accumulation is formed in the area of the aluminum oxide passivation layer, and the alkali metal ions with positive charges weaken the field passivation effect of the negative charges of the aluminum oxide. Polarization by alkali metal ion (PID-P): like PID-S, the back alkali metal ions penetrate the back silicon nitride film layer and form a pile in the area of the alumina passivation layer, and the positively charged alkali metal ions weaken the field passivation effect in the alumina passivation layer due to the negative charge. ③ corrosion by alkali metal ions or water vapor (PID-C): the back alkali metal ions penetrate through the back silicon nitride and aluminum oxide passivation layers to form aggregation on the back surface of the silicon wafer, electrochemical corrosion is locally formed under the action of potential and OH & lt- & gt in the aluminum oxide layer, and the generated silicon oxide destroys the passivation of the aluminum oxide passivation layers and causes surface recombination. The surface passivation caused by water vapor is reduced, and when a silicon nitride layer is not superposed on the aluminum oxide, the influence on the aluminum oxide passivation layer is serious. Fourthly, electrode area corrosion: under the conditions of high temperature and high humidity, the silver and aluminum electrodes are affected by metal ions generated by electrochemical corrosion. Aluminum paste corrosion: lateral erosion of the double-sided aluminum paste on the surface of the backside silicon nitride protective layer and at the laser openings may have an effect on the long-term stability of the backside passivation stack, especially on the silicon-rich silicon nitride layer.
Aiming at the problem of how to slow down PID attenuation of the back of the double-sided battery, the method is only in a starting research stage at present. The main measure is that the encapsulation mode of replacing ECV with dual-glass and POE is adopted to meet the basic performance of the double-sided PERC battery product, but the cost performance of the double-glass double-sided assembly is challenged along with the obvious problems of glass price, capacity gap and the like. Another scheme is a mode of stacking a transparent backplane with a POE, which has certain advantages in cost, but the reliability of the transparent backplane packaging mode still has risks, and needs to be further improved and evaluated. On the battery side, due to the requirement of the double-sided battery on double-sided rate, the thickness of the back silicon nitride film is generally 80-100nm, which further poses higher challenge to the reliability of the double-sided PERC battery, and related research is in progress.
For example, patent CN110444609A discloses a method for preparing a composite back structure of silicon nitride + silicon carbonitride on the back of a double-sided battery, and improving back PID; patent CN109509796A discloses a method for preparing a composite back structure of silicon nitride + silicon oxynitride on the back of a double-sided battery and improving back PID; patents CN109638110A, CN110943146A disclose a multilayer silicon nitride back structure and a method for improving back PID; patent CN111029436A discloses a method for preparing a silicon carbide back structure on the back of a double-sided battery and improving the LeTID. However, the above method is not ideal for improving the PID attenuation phenomenon on the back surface of the double-sided battery.
Therefore, how to further improve the improvement effect of the reliability problems such as the PID on the back surface of the double-sided battery becomes an important challenge limiting the popularization of the double-sided PERC product, and a solution is urgently needed.
Disclosure of Invention
1. Problems to be solved
Aiming at the defects that the back PID attenuation of the double-sided battery is serious and the problem is difficult to effectively improve by adopting the prior art, the double-sided battery with high reliability and the preparation method thereof are provided. According to the invention, a silicon oxide layer is deposited between the silicon substrate of the double-sided battery and the AlOx passivation layer on the back surface in an ALD or PEALD mode, so that the PID problem on the back surface of the double-sided battery can be effectively improved, and the long-term stability of the battery piece is further improved.
2. Technical scheme
In order to solve the problems, the technical scheme adopted by the invention is as follows:
according to the preparation method of the high-reliability double-sided battery, the silicon oxide protective layer is prepared on the back surface of the battery in an ALD (atomic layer deposition) or PEALD (chemical vapor deposition) mode.
Furthermore, the silicon oxide protective layer is positioned between the silicon wafer substrate and the aluminum oxide passivation layer on the back surface of the cell.
Furthermore, the thickness of the silicon oxide protective layer is 0.1-2 nm.
Furthermore, a silicon nitride passivation and protection layer is arranged on the bottom surface of the aluminum oxide passivation layer.
Furthermore, a silicon oxide protective layer is deposited between the aluminum oxide passivation layer and the silicon nitride passivation and protective layer by means of ALD or PEALD.
Furthermore, the specific process flow of the deposition preparation of the silicon oxide protective layer comprises the following steps:
step 1: in a vacuum environment, introducing any one precursor A of a gas-phase silicon-based precursor and an oxidant precursor into a reactor cavity, and keeping the precursor A on the back surface of a silicon wafer substrate through chemical adsorption;
step 2: introducing nitrogen or inert gas for removing by-products and redundant precursors;
step 3: introducing another precursor B in the silicon-based precursor and the oxidant precursor, and reacting with the precursor A adsorbed on the silicon wafer substrate to generate a silicon oxide protective film;
step 4: introducing nitrogen or inert gas again for cleaning;
step 5: repeating the above steps for different turns to grow the film layer by layer.
Furthermore, the silicon-based precursor during the deposition of the silicon oxide protective layer is any one of hexachlorodisilane, disilane, trisilane and trisilylamine; the oxidant precursor is ozone or oxygen.
Furthermore, the pressure in the reaction cavity is controlled to be 2-50mbar, the pulse time of the silicon-based precursor is 0.1-4s, and the flow is 1-500sccm when the silicon oxide protective layer is deposited; the pulse time of the oxidant is 1-10s, the flow rate is 1-2000sccm, and the cycle deposition times are 1-50.
Furthermore, the preparation method specifically comprises the working procedures of texturing, diffusion, laser SE, thermal oxidation, oxidation annealing, back side deposition of an aluminum oxide passivation film, back side deposition of a silicon oxide film, front side deposition of a silicon nitride film and back side deposition of a silicon nitride film, wherein the back side deposition of the aluminum oxide passivation film and the back side deposition of the silicon oxide film are carried out by adopting the same tube or different tubes.
The high-reliability double-sided battery comprises a silicon wafer substrate, wherein a silicon oxide protective layer, an aluminum oxide passivation layer and a silicon nitride passivation and protective layer are sequentially arranged on the back surface of the silicon wafer substrate from inside to outside, and the silicon oxide protective layer is formed by deposition in an ALD or PEALD mode.
Furthermore, a silicon oxide protective layer is deposited between the aluminum oxide passivation layer and the silicon nitride passivation and protective layer by means of ALD or PEALD.
3. Advantageous effects
Compared with the prior art, the invention has the beneficial effects that:
(1) according to the preparation method of the high-reliability double-sided battery, the silicon oxide protective layer is deposited on the back of the battery in an atomic layer film forming mode of ALD or PEALD, so that the thickness of the silicon oxide layer can be accurately controlled, the process repeatability and the stability are good, meanwhile, the compactness of the silicon oxide protective layer can be effectively improved, the uniform, compact and pinhole-free preparation of the silicon oxide is realized, and the PID (proportion integration differentiation) resistant effect of the back of the double-sided battery can be further ensured. Meanwhile, the addition of the silicon oxide protective layer also provides excellent surface passivation, and the passivation effect of the back passivation layer is further improved.
(2) According to the preparation method of the high-reliability double-sided battery, the silicon oxide protective layer is positioned between the silicon wafer substrate and the aluminum oxide passivation layer on the back of the battery, so that the electrochemical corrosion failure caused by the fact that alkali metal ions enter the surface of the silicon wafer can be effectively prevented on the basis of not influencing the passivation effect of the aluminum oxide passivation film, and the long-term stability of the battery piece is improved.
(3) According to the preparation method of the high-reliability double-sided battery, the bottom surface of the aluminum oxide passivation layer is provided with the silicon nitride passivation layer and the protective layer, and the inhibition effect on the PID (proportion integration differentiation) of the back surface of the double-sided battery and the back surface passivation effect can be effectively guaranteed through the combined action of the three-layer film structure consisting of the silicon oxide protective layer, the aluminum oxide passivation layer and the silicon nitride passivation layer. On one hand, the silicon oxide protective layer is deposited between the aluminum oxide passivation layer and the silicon nitride passivation and protection layer, so that alkali metal ions can be further prevented from entering the surface of the silicon wafer on the basis of not influencing the passivation effect of an aluminum oxide field, and polarization and corrosive PID failure caused by the alkali metal ions are further reduced; on the other hand, the polarization effect caused by K + center in silicon nitride can be effectively reduced, and PID failure caused by a silicon nitride layer is reduced.
(4) According to the preparation method of the high-reliability double-sided battery, the type of the silicon-based precursor is optimized, so that the deposition of the silicon oxide protective layer can be realized in an ALD or PEALD mode, a stable chemical adsorption layer can be quickly formed on the surface of the base material, and the quality of the deposited layer can be favorably ensured; meanwhile, by optimally designing various process parameters in the deposition process, such as pulse time, flow rate and the like of the silicon-based precursor and the oxidant, the compactness, thickness and component uniformity of the obtained silicon oxide layer can be further ensured.
(5) According to the preparation method of the high-reliability double-sided battery, the ALD or PEALD is adopted to prepare the silicon oxide layer, only one silicon-based precursor pipeline needs to be additionally added on the existing ALD or PEALD machine and process, and the aluminum oxide passivation layer and the silicon oxide protection layer on the outer side of the aluminum oxide passivation layer are directly prepared after the silicon oxide protection layer is prepared, so that the manufacturing process and equipment machine do not need to be additionally added.
(6) According to the high-reliability double-sided battery, the silicon oxide protective layer, the aluminum oxide passivation layer and the silicon nitride passivation and protection layer are sequentially arranged on the back surface of the silicon chip substrate from inside to outside, PID attenuation and failure of the back surface of the battery caused by electrochemical corrosion due to alkali metal ions entering the surface of the silicon chip can be effectively reduced through the arrangement of the silicon oxide protective layer, and meanwhile, the passivation effect of the back passivation layer can be effectively enhanced through the composite action of the silicon oxide protective layer, the aluminum oxide passivation layer and the silicon nitride passivation and protection layer. The silicon oxide protective layer is deposited by an ALD (atomic layer deposition) or PEALD (particle beam deposition) mode, so that the thickness of the silicon oxide layer can be accurately controlled, a uniform and compact silicon oxide film without pinholes can be obtained, and the influence on the passivation effect of an aluminum oxide passivation film is prevented.
Drawings
Fig. 1 is a schematic sectional view of a double-sided battery according to the present invention.
In the figure: 1. a silicon wafer substrate; 2. a front emitter; 2-1, shallow doped region; 2-2, a heavily doped region; 3. a front surface oxidation layer; 4. a silicon oxide protective layer; 5. an alumina passivation layer; 6. a silicon nitride passivation and protection layer; 7. a front surface silicon nitride passivation and antireflection layer; 8. laser grooving on the back; 9. a back side sub-gate electrode; 10. and a positive electrode.
Detailed Description
Aiming at the problem of serious PID attenuation of the back side of the existing double-sided battery, the silicon oxide protective layer 4 is deposited on the back side of the double-sided PERC battery by adopting an Atomic Layer Deposition (ALD) or Plasma Enhanced Atomic Layer Deposition (PEALD) mode, so that the silicon oxide dielectric film with accurate and controllable thickness, uniformity, compactness and no pin hole can be prepared, and the PID resistance of the back side of the battery is further improved. Meanwhile, the passivation effect of the back passivation layer can be further improved by adding the silicon oxide protection layer.
According to the invention, on the basis of the structure of the Si/AlOx/SiNx passivation layer on the back of the existing double-sided PERC battery, the silicon oxide protection layer 4 is deposited between the silicon wafer substrate 1 and the aluminum oxide passivation layer 5 on the back of the silicon wafer substrate, so that the thickness of the silicon oxide protection layer can be accurately controlled to be 0.1-2nm, and PID attenuation and failure of the back of the battery, which are caused by electrochemical corrosion due to the fact that alkali metal ions penetrate into the surface of the silicon wafer, can be effectively prevented.
Through retrieval, related researches disclose that a silicon oxide protective layer is prepared between the back surface of a cell matrix and an aluminum oxide passivation layer, for example, an application with the application number of 2018221198355 discloses a PID-resistant double-sided cell, an application with the application number of 201911366006X discloses a method for preparing a back surface fully-passivated contact solar cell by using tubular PECVD, and an application with the application number of 2019107631303, which is applied by an applicant in 2019, discloses a solar cell with a composite dielectric passivation layer structure and a preparation process thereof. However, the above applications are all by thermal annealing (dry thermal oxidation, ozone oxidation, N)2O oxidation) or PECVD method for growing a silicon oxide film between the back surface of a silicon wafer substrate and an aluminum oxide passivation layerThe main preparation method of silicon oxide film in the technology. However, ozone oxidation generally uses ozone to oxidize the silicon wafer in the transmission process in the etching blanking area, and the oxide layer formed by the method is loose and thin, the stability of the process is poor, and real-time monitoring cannot be realized. The oxidation layer of dry-oxygen thermal oxidation is compact, oxidation is mainly carried out in a quartz tube at present, in order to maximize the productivity, a single-groove double-insert mode is often adopted in a quartz boat, namely two silicon wafers are inserted into the same clamping groove in a back-to-back mode at back surfaces, the front surface is exposed, oxidation is basically carried out on the front surface during oxidation by the method, the oxidation layer is arranged on the edge of the silicon wafer at the back surface, and the central area is very thin or even not. Meanwhile, SiO prepared by thermal oxidation method2The silicon in the silicon chip is from the surface of the silicon chip, and when SiO with certain thickness is formed on the surface of the silicon chip2After the layer, the oxidizing agent must move in a diffuse manner to the Si-SiO2Interface, then react with silicon to form SiO2But with SiO2The growth rate of the thin film gradually decreases due to the thickening of the layer, so that it is difficult to control the oxidation rate, particularly to prepare an extremely thin oxide layer, and it is easy to cause transition metal contamination. Silicon oxide prepared by PECVD laughing gas is relatively loose, and when tubular preparation is adopted, the preparation of an oxide layer can be only carried out on one surface of the surface of a silicon wafer, the preparation of the oxide layer is mainly carried out on the front surface of the silicon wafer in the prior art, and if the oxide layer is prepared on the back surface, an additional equipment machine table is required to be additionally arranged for independent preparation. In addition, the above methods cannot accurately control the thickness of the back surface silicon oxide layer, and the excessively thick silicon oxide layer weakens the field passivation effect of aluminum oxide, thereby greatly reducing the conversion efficiency of the PERC cell, and therefore, the method also has a great challenge on the stability of the production line.
And the silicon oxide film is innovatively deposited between the back of the silicon substrate and the aluminum oxide passivation film in an ALD or PEALD mode, so that the thickness of the silicon oxide film can be controlled precisely, the compactness of the silicon oxide film can be effectively improved, and the thickness and component uniformity of the film are ensured, thereby effectively preventing alkali metal ions from entering the silicon substrate to cause electrochemical corrosion, greatly reducing PID attenuation at the back of the battery, and improving the reliability of the battery. In addition, a layer of silicon oxide film can be deposited between the aluminum oxide passivation film 5 on the back side of the cell and the silicon nitride passivation and protection layer 6 in an ALD or PEALD mode, and through the addition of the layer of silicon oxide film, alkali metal ions can be further prevented from entering the surface of the silicon wafer on the basis of not influencing the aluminum oxide field passivation effect (avoiding damaging the aluminum oxide passivation film), so that polarization and corrosive PID failure caused by the alkali metal ions are further reduced; meanwhile, the polarization effect caused by K + center in silicon nitride can be effectively reduced, so that PID failure caused by a silicon nitride layer is reduced. Therefore, the anti-PID effect of the back of the double-sided battery can be better improved through the combined action of the two silicon oxide protective layers.
Specifically, the preparation process of the silicon oxide protective layer of the invention is as follows:
(1) introducing a precursor A in a gas-phase silicon-based precursor and an oxidant precursor into a reactor cavity in a vacuum environment, and keeping the precursor A on the surface of a silicon wafer substrate through chemical adsorption; the silicon-based precursor is hexachlorodisilane (Si)2Cl6Abbreviated HCDS), bis (tert-butylamino) Silane (SiH)2[NHC(CH3)3]2BTBAS, bis (diethylamino) Silane (SiH)2[N(CH2CH3)2]2BDEAS), tris (dimethylamino) silane (SiH [ N (CH) ]3)2]33DMAS), trisilylamine ((SiH)3)3N, TSA); the oxidant adopts ozone (O)3) Oxygen (O2).
(2) Introducing nitrogen or inert gas for removing by-products and redundant precursors;
(3) introducing a silicon-based precursor and another precursor B in an oxidant precursor, and reacting with the precursor A adsorbed on the silicon wafer substrate to generate a silicon oxide film; wherein the temperature of the silicon wafer substrate is 150-400 ℃, and the pressure (vacuum degree) in the reaction chamber is 2-50 mbar; the purging time of nitrogen or inert gas is 0.5-20s, and the flow rate is 100-; the pulse time of the silicon-based precursor is 0.1-4s, and the flow is 1-500 sccm; the pulse time of the oxidant is 1-10s, and the flow rate is 1-2000 sccm. The cycle times are 10-500 times.
By optimizing the type of the silicon-based precursor and the specific reaction process parameters, the method can meet the requirement of atomic deposition and ensure the deposition growth of the silicon oxide film; on the other hand, the compactness, the thickness and the component uniformity of the obtained silicon oxide film can be effectively ensured, so that the PID resistance effect is favorably ensured.
(4) Introducing nitrogen or inert gas again for cleaning;
(5) the above steps are repeated for different turns (times) in a circulating way, and the thin film grows layer by layer.
The present invention will be further described with reference to specific examples, but it should be understood that the present invention is not limited thereto, and the types of silicon-based precursors and the values of the deposition process parameters of the silicon oxide protective layer are not limited to the following examples.
The invention is further described with reference to specific examples.
Example 1
As shown in fig. 1, the back cell of the present embodiment includes a silicon wafer substrate 1, a silicon oxide protection layer 4, an aluminum oxide passivation layer 5 and a silicon nitride passivation and protection layer 6 are sequentially disposed on the back surface of the silicon wafer substrate 1 from inside to outside, wherein the silicon oxide protection layer 4 is deposited by an ALD method, and the specific preparation process thereof is as follows: placing a silicon wafer into an atomic layer deposition cavity, heating the substrate temperature of the silicon wafer to 150 ℃, vacuumizing the reaction cavity until the pressure reaches 20mbar and below, and introducing tris (dimethylamino) silane (silicon-based precursor) with the flow rate of 150sccm for 4 s; then purging with nitrogen for 20 s; then ozone (oxidant precursor) with the flow rate of 20sccm is introduced for 10s, and then nitrogen is used for purging for 10 s; the steps are circulated for 20 times, and the silicon oxide protective film with the thickness of about 2nm is prepared.
Example 2
The back cell of the embodiment comprises a silicon wafer substrate 1, wherein the front surface of the silicon wafer substrate 1 is sequentially provided with a front emitter 2, a front oxide layer 3, a front silicon nitride passivation and antireflection layer 7 and a positive electrode 10 from bottom to top, and the back surface of the silicon wafer substrate is sequentially provided with a silicon oxide protective layer 4, an aluminum oxide passivation layer 5, a silicon nitride passivation and protection layer 6 and a back auxiliary gate electrode 9 from inside to outside.
The back side cell preparation process of the embodiment comprises the following steps:
1. texturing: a monocrystal P-type silicon wafer substrate 1 is adopted, and front and back texturing is carried out by alkali to form a textured structure.
2. Diffusion: and (3) reacting the silicon wafer after texturing with phosphorus oxychloride at high temperature to diffuse the front side to form a PN emitter junction (namely the front emitter 2). The diffusion is carried out by adopting the diffusion process, and the sheet resistance of the front surface thin layer after the diffusion is 150 omega/□.
3. Laser SE: and performing laser doping on the front surface of the diffused silicon wafer and the metalized area corresponding to the positive electrode grid line by using the diffused phosphorosilicate glass as a phosphorus source to form a heavily doped area 2-2, so that a structure (a shallow doped area 2-1 and a heavily doped area 2-2) for selecting an emitter is realized on the front surface of the silicon wafer. The laser doping is carried out by adopting the laser process, and the square resistance of the heavily doped region is 65 omega/□.
4. Thermal oxidation: and oxidizing the silicon wafer after the laser SE by introducing oxygen through the thermal oxidation process.
5. Removing PSG: and (4) removing the PSG on the back surface and the periphery of the silicon wafer after thermal oxidation by using HF.
6. Alkali polishing: and (3) carrying out back polishing on the silicon wafer with the PSG removed by adopting the alkali polishing process, removing the PSG on the front side and carrying out surface micro-etching.
7. Oxidizing and annealing: and (3) oxidizing and annealing the silicon wafer after alkali polishing, and preparing an oxide layer 3 on the front surface and the back surface of the silicon wafer simultaneously. The process is carried out in a quartz tube cavity, the temperature of a silicon wafer substrate is 700 ℃, the flow of oxygen is 2000sccm, and the oxidation is carried out for 10 min.
8. Back side deposition of silicon oxide layer: and preparing a silicon oxide protective layer 4 on the back of the annealed silicon wafer. Placing the silicon wafer after the step 7 into an atomic layer deposition cavity, heating the substrate of the silicon wafer to 190 ℃, vacuumizing the reaction cavity until the pressure reaches 20mbar and below, and introducing trisilylamine (silicon-based precursor) with the flow rate of 50sccm for 4 s; then purging with nitrogen for 8 s; then ozone (oxidant precursor) with the flow rate of 18sccm is introduced for 6s, and then nitrogen is used for purging for 8 s; the steps are circulated for 8 times, and the silicon oxide protective film with the thickness of about 0.5nm is prepared.
9. Depositing an aluminum oxide passivation film on the back: and (3) in the same cavity for depositing the silicon oxide protective layer, after the process of the step 8 is finished (the substrate temperature is 190 ℃, and the pressure in the reaction cavity is less than 20 mbar), purging by using nitrogen for 120s, and removing residues of silicon oxide reaction. Then TMA (aluminum-based precursor) with the flow rate of 20sccm is introduced for 2 s; then purging with nitrogen for 8 s; then ozone (oxidant precursor) with the flow rate of 18sccm is introduced for 6s, and then nitrogen is used for purging for 8 s; the steps are circulated for 25 times, and the aluminum oxide passive film 5 with the thickness of about 3nm is prepared.
10. Depositing a silicon nitride film on the back: preparing a three-layer silicon nitride passivation and protection film 6 on the back of the silicon wafer after the step 9, heating the cavity to 480 ℃ before depositing the silicon nitride, maintaining the constant temperature for 3min, introducing silane and ammonia plasma to carry out chemical vapor deposition on the silicon nitride film, wherein the total thickness of the silicon nitride film is 100nm, the thicknesses of the first layer and the second layer are respectively 30nm, the thickness of the third layer is 40nm, the refractive index is gradually reduced from inside to outside, and the overall refractive index is maintained at 2.06.
11. And (3) depositing a silicon nitride film: three layers of silicon nitride passivation and antireflection films 7 are prepared on the front surface, the total thickness of the film layers is 80nm, the refractive index is gradually reduced from inside to outside, and the overall refractive index is maintained to be more than 2.14.
12. Back laser: and (3) carrying out laser drilling on the silicon wafer with the passivation film prepared on the back surface to form a back surface laser groove 8.
13. Back electrode printing: and (4) screen printing is carried out on the silicon wafer with the front and the back surfaces subjected to laser hole opening to prepare a back electrode.
14. Back side sub-grid printing: the back side sub-gate electrode 9 is screen printed on the printed back electrode silicon wafer.
15. Positive electrode printing: and screen printing a front electrode on the front surface of the silicon wafer after the back electrode is printed, namely forming a positive electrode 10.
16. And (3) sintering: and (3) co-sintering the silicon chip with the front electrode printed, wherein the sintering peak temperature is 700 ℃.
17. Electric injection: and performing electro-injection treatment on the sintered battery piece.
18. And (3) finished product: and testing, sorting, packaging and warehousing the product battery pieces.
The double-sided PERC battery piece prepared by the technical route has the advantage that the back surface PID attenuation can be reduced by 0.5% under the standard test conditions (IEC61215 or UL1703 standard) of-1500V, 85% of humidity and 85 ℃.
Example 3
The structure of the back cell of this embodiment is the same as that of embodiment 2, and the method for manufacturing the back cell of this embodiment specifically includes the following process steps:
1. texturing: a monocrystal P-type silicon wafer is adopted, and front and back texturing is carried out by alkali to form a textured structure.
2. Diffusion: and (3) reacting the silicon wafer after texturing with phosphorus oxychloride at high temperature to diffuse the front side to form a PN emitter junction 2. The diffusion is carried out by adopting the diffusion process, and the sheet resistance of the front surface thin layer after the diffusion is 150 omega/□.
3. Laser SE: and performing laser doping on the front surface of the diffused silicon wafer and the metalized area corresponding to the positive electrode grid line by using the diffused phosphorosilicate glass as a phosphorus source to form a heavily doped area 2-2, so that the structure of selecting the emitter is realized on the front surface of the silicon wafer. The laser doping is carried out by adopting the laser process, and the square resistance of the heavily doped region is 65 omega/□.
4. Thermal oxidation: and oxidizing the silicon wafer after the laser SE by introducing oxygen through the thermal oxidation process.
5. Removing PSG: and (4) removing the PSG on the back surface and the periphery of the silicon wafer after thermal oxidation by using HF.
6. Alkali polishing: and (3) carrying out back polishing on the silicon wafer with the PSG removed by adopting the alkali polishing process, removing the PSG on the front side and carrying out surface micro-etching.
7. Oxidizing and annealing: and (3) oxidizing and annealing the silicon wafer after alkali polishing, and preparing an oxide layer 3 on the front surface and the back surface of the silicon wafer simultaneously. The process is carried out in a quartz tube cavity, the temperature of a silicon wafer substrate is 700 ℃, the flow of oxygen is 2000sccm, and the oxidation is carried out for 10 min.
8. Back side deposition of silicon oxide layer: and preparing a silicon oxide layer 4 on the back of the annealed silicon wafer. Placing the silicon wafer after the step 7 into an atomic layer deposition cavity, heating the substrate of the silicon wafer to 180 ℃, vacuumizing the reaction cavity until the pressure reaches 20mbar and below, and introducing hexachlorodisilane (silicon-based precursor) with the flow rate of 50sccm for 4 s; then purging with nitrogen for 8 s; then introducing plasma (oxidant precursor) subjected to radio frequency oxygen treatment for 3s, wherein the oxygen flow is 1000sccm, and then purging for 8s by using nitrogen; the steps are circulated for 10 times, and a silicon oxide protective film with the diameter of about 1nm is prepared, the radio frequency is 13.56MHZ, and the power is 8000W.
9. Depositing an aluminum oxide passivation film on the back: and (3) in the same cavity for depositing the silicon oxide layer, after the 8-step process is finished (the substrate temperature is 180 ℃, and the pressure in the reaction cavity is less than 20 mbar), purging with nitrogen for 120s, and removing the residue of the alumina reaction. Then TMA (aluminum-based precursor) is introduced for 3 s; then purging with nitrogen for 8 s; then introducing plasma (oxidant precursor) subjected to radio frequency oxygen treatment for 3s, wherein the oxygen flow is 1000sccm, and then purging for 8s by using nitrogen; the steps are circulated for 30 times, and the alumina passive film 5 with the thickness of about 3nm is prepared. Radio frequency 13.56MHZ, power 8000W.
10. Depositing a silicon nitride film on the back: preparing a three-layer silicon nitride passivation and protection film 6 on the back of the silicon wafer after the step 9, heating the cavity to 480 ℃ before depositing the silicon nitride, maintaining the constant temperature for 3min, introducing silane and ammonia plasma to carry out chemical vapor deposition on the silicon nitride film, wherein the total thickness of the silicon nitride film is 100nm, the thicknesses of the first layer and the second layer are respectively 30nm, the thickness of the third layer is 40nm, the refractive index is gradually reduced from inside to outside, and the overall refractive index is maintained at 2.06.
11. And (3) depositing a silicon nitride film: three layers of silicon nitride passivation and antireflection films 7 are prepared on the front surface, the total thickness of the layers is 80nm, the refractive index is gradually reduced from inside to outside, and the overall refractive index is maintained to be more than 2.14.
12. Back laser: and carrying out laser drilling on the silicon wafer with the passivation film prepared on the back surface.
13. Back electrode printing: and carrying out screen printing on the silicon wafer after laser hole opening on the front side and the back side to prepare a back electrode.
14. Back side sub-grid printing: the back side sub-gate electrode 9 is screen printed on the printed back electrode silicon wafer.
15. Positive electrode printing: after printing the back electrode, the silicon wafer is screen printed with a positive electrode 10 on its front side.
16. And (3) sintering: and (3) co-sintering the silicon chip with the front electrode printed, wherein the sintering peak temperature is 800 ℃.
17. Electric injection: and performing electro-injection treatment on the sintered battery piece.
18. And (3) finished product: and testing, sorting, packaging and warehousing the product battery pieces.
The double-sided PERC battery piece prepared by the technical route has the advantage that the back surface PID attenuation can be reduced by 0.7% under the standard test conditions (IEC61215 or UL1703 standard) of-1500V, 85% of humidity and 85 ℃.
Example 4
The structure of the back cell of this embodiment is the same as that of embodiment 2, and the method for manufacturing the back cell of this embodiment specifically includes the following process steps:
1. texturing: a monocrystal P-type silicon wafer substrate 1 is adopted, and front and back texturing is carried out by alkali to form a textured structure.
2. Diffusion: and (3) reacting the silicon wafer after texturing with phosphorus oxychloride at high temperature to diffuse the front side to form a PN emitter junction (namely the front emitter 2). The diffusion is carried out by adopting the diffusion process, and the square resistance of the front surface thin layer after the diffusion is between 100 omega/□.
3. Laser SE: and performing laser doping on the front surface of the diffused silicon wafer and the metalized area corresponding to the positive electrode grid line by using the diffused phosphorosilicate glass as a phosphorus source to form a heavily doped area 2-2, so that a structure (a shallow doped area and the heavily doped area 2-2) for selecting an emitter is realized on the front surface of the silicon wafer. The laser doping is carried out by adopting the laser process, and the square resistance of the heavily doped region is between 50 omega/□.
4. Thermal oxidation: and oxidizing the silicon wafer after the laser SE by introducing oxygen through the thermal oxidation process.
5. Removing PSG: and (4) removing the PSG on the back surface and the periphery of the silicon wafer after thermal oxidation by using HF.
6. Alkali polishing: and (3) carrying out back polishing on the silicon wafer with the PSG removed by adopting the alkali polishing process, removing the PSG on the front side and carrying out surface micro-etching.
7. Oxidizing and annealing: and (3) oxidizing and annealing the silicon wafer after alkali polishing, and preparing an oxide layer 3 on the front surface and the back surface of the silicon wafer simultaneously. The process is carried out in a quartz tube cavity, the temperature of a silicon wafer substrate is 680 ℃, the flow of oxygen is 1900sccm, and the oxidation is carried out for 8 min.
8. Back side deposition of silicon oxide layer: and preparing a silicon oxide layer 4 on the back of the annealed silicon wafer. Placing the silicon wafer after the step 7 into an atomic layer deposition cavity, heating the substrate of the silicon wafer to 250 ℃, vacuumizing the reaction cavity until the pressure reaches 20mbar and below, and introducing bis (diethylamino) silane (silicon-based precursor) with the flow rate of 50sccm for 3 s; then purging with nitrogen for 15 s; then introducing plasma (oxidant precursor) subjected to radio frequency oxygen treatment for 10s, wherein the oxygen flow is 1500sccm, and then purging for 17s by using nitrogen; the steps are circulated for 15 times, and the silicon oxide protective film with the diameter of about 1.5nm is prepared, the radio frequency is 13.56MHZ, and the power is 8000W.
9. Depositing an aluminum oxide passivation film on the back: and in the same cavity for depositing the silicon oxide layer, purging by using nitrogen for 100s after the process of the step 8 is completed, and removing residues of the aluminum oxide reaction. Then TMA (aluminum-based precursor) with the flow rate of 23sccm is introduced for 2 s; then purging with nitrogen for 6 s; then introducing plasma (oxidant precursor) subjected to radio frequency oxygen treatment for 5s, and then purging with nitrogen for 6 s; the steps are circulated for 32 times, and the aluminum oxide passive film with the thickness of about 3.5nm is prepared.
10. Depositing a silicon nitride film on the back: preparing a three-layer silicon nitride passivation and protection film 6 on the back of the silicon wafer after the step 9, heating the cavity to 480 ℃ before depositing the silicon nitride, maintaining the constant temperature for 3min, and then introducing silane and ammonia plasma to carry out chemical vapor deposition on a silicon nitride film, wherein the total thickness of the silicon nitride film is 100nm, the thicknesses of the first layer and the second layer are respectively 35nm, and the thickness of the third layer is 45 nm.
11. And (3) depositing a silicon nitride film: three layers of silicon nitride passivation and antireflection films 7 are prepared on the front surface, the total thickness of the film layers is 80nm, the refractive index is gradually reduced from inside to outside, and the overall refractive index is maintained to be more than 2.14.
12. Back laser: and (3) carrying out laser drilling on the silicon wafer with the passivation film prepared on the back surface to form a back surface laser groove 8.
13. Back electrode printing: and (4) screen printing is carried out on the silicon wafer with the front and the back surfaces subjected to laser hole opening to prepare a back electrode.
14. Back side sub-grid printing: the back side sub-gate electrode 9 is screen printed on the printed back electrode silicon wafer.
15. Positive electrode printing: and screen printing a front electrode on the front surface of the silicon wafer after the back electrode is printed, namely forming a positive electrode 10.
16. And (3) sintering: and (3) co-sintering the silicon chip with the front electrode printed, wherein the sintering peak temperature is 750 ℃.
17. Electric injection: and performing electro-injection treatment on the sintered battery piece.
18. And (3) finished product: and testing, sorting, packaging and warehousing the product battery pieces.
Under the standard test conditions of-1500V, 85% humidity and 85 ℃ (IEC61215 or UL1703 standard), the back PID attenuation of the double-sided PERC battery piece prepared by the embodiment can be reduced by 0.6%.
Example 5
The structure of the back cell of this embodiment is the same as that of embodiment 2, and the method for manufacturing the back cell of this embodiment specifically includes the following process steps:
1. texturing: a monocrystal P-type silicon wafer substrate 1 is adopted, and front and back texturing is carried out by alkali to form a textured structure.
2. Diffusion: and (3) reacting the silicon wafer after texturing with phosphorus oxychloride at high temperature to diffuse the front side to form a PN emitter junction (namely the front emitter 2). The diffusion is carried out by adopting the diffusion process, and the square resistance of the front surface thin layer after the diffusion is 180 omega/□.
3. Laser SE: and performing laser doping on the front surface of the diffused silicon wafer and the metalized area corresponding to the positive electrode grid line by using the diffused phosphorosilicate glass as a phosphorus source to form a heavily doped area 2-2, so that a structure (a shallow doped area and the heavily doped area 2-2) for selecting an emitter is realized on the front surface of the silicon wafer. The laser doping is carried out by adopting the laser process, and the square resistance of the heavily doped region is between 90 omega/□.
4. Thermal oxidation: and oxidizing the silicon wafer after the laser SE by introducing oxygen through the thermal oxidation process.
5. Removing PSG: and (4) removing the PSG on the back surface and the periphery of the silicon wafer after thermal oxidation by using HF.
6. Alkali polishing: and (3) carrying out back polishing on the silicon wafer with the PSG removed by adopting the alkali polishing process, removing the PSG on the front side and carrying out surface micro-etching.
7. Oxidizing and annealing: and (3) oxidizing and annealing the silicon wafer after alkali polishing, and preparing an oxide layer 3 on the front surface and the back surface of the silicon wafer simultaneously. The process is carried out in a quartz tube cavity, the temperature of a silicon wafer substrate is 730 ℃, the oxygen flow is 2050sccm, and the oxidation is carried out for 12 min.
8. Back side deposition of silicon oxide layer: and preparing a silicon oxide layer 4 on the back of the annealed silicon wafer. Placing the silicon wafer after the step 7 into an atomic layer deposition cavity, heating the substrate of the silicon wafer to 300 ℃, vacuumizing the reaction cavity until the pressure reaches 20mbar and below, and introducing bis (tert-butylamino) silane (silicon-based precursor) with the flow rate of 40sccm for 5 s; then purging with nitrogen for 14 s; then ozone (oxidant precursor) is introduced for 7s, the ozone flow is 200sccm, and then nitrogen is used for purging for 7 s; the steps are circulated for 20 times, and the silicon oxide protective film with the diameter of about 2nm is prepared, the radio frequency is 13.56MHZ, and the power is 8000W.
9. Depositing an aluminum oxide passivation film on the back: and in the same cavity for depositing the silicon oxide layer, after the 8 th step of process is finished, purging for 130s by using nitrogen, and removing residues of the aluminum oxide reaction. Then introducing TMA (aluminum-based precursor) with the flow rate of 30sccm for 3 s; then purging with nitrogen for 15 s; then ozone (oxidant precursor) is introduced for 10s, the ozone flow is 100sccm, and then nitrogen is used for purging for 4 s; the steps are circulated for 28 times, and the aluminum oxide passive film with the thickness of about 2.7nm is prepared.
10. Depositing a silicon nitride film on the back: preparing a three-layer silicon nitride passivation and protection film 6 on the back of the silicon wafer after the step 9, heating the cavity to 480 ℃ before depositing the silicon nitride, maintaining the constant temperature for 3min, introducing silane and ammonia plasma to carry out chemical vapor deposition on the silicon nitride film, wherein the total thickness of the silicon nitride film is 100nm, the thicknesses of the first layer and the second layer are respectively 30nm, the thickness of the third layer is 40nm, the refractive index is gradually reduced from inside to outside, and the overall refractive index is maintained at 2.06.
11. And (3) depositing a silicon nitride film: three layers of silicon nitride passivation and antireflection films 7 are prepared on the front surface, the total thickness of the film layers is 80nm, the refractive index is gradually reduced from inside to outside, and the overall refractive index is maintained to be more than 2.14.
12. Back laser: and (3) carrying out laser drilling on the silicon wafer with the passivation film prepared on the back surface to form a back surface laser groove 8.
13. Back electrode printing: and (4) screen printing is carried out on the silicon wafer with the front and the back surfaces subjected to laser hole opening to prepare a back electrode.
14. Back side sub-grid printing: the back side sub-gate electrode 9 is screen printed on the printed back electrode silicon wafer.
15. Positive electrode printing: and screen printing a front electrode on the front surface of the silicon wafer after the back electrode is printed, namely forming a positive electrode 10.
16. And (3) sintering: and (3) co-sintering the silicon chip with the front electrode printed, wherein the sintering peak temperature is 730 ℃.
17. Electric injection: and performing electro-injection treatment on the sintered battery piece.
18. And (3) finished product: and testing, sorting, packaging and warehousing the product battery pieces.
Under the standard test conditions of-1500V, 85% humidity and 85 ℃ (IEC61215 or UL1703 standard), the back PID attenuation of the double-sided PERC battery piece prepared by the embodiment can be reduced by 0.8%.
Example 6
The back cell of the embodiment comprises a silicon wafer substrate 1, wherein the front surface of the silicon wafer substrate 1 is sequentially provided with a front emitter 2, a front oxide layer 3, a front silicon nitride passivation and antireflection layer 7 and a positive electrode 10 from bottom to top, and the back surface thereof is sequentially provided with a silicon oxide protective layer 4, an aluminum oxide passivation layer 5, a silicon oxide protective layer 4, a silicon nitride passivation and protective layer 6 and a back auxiliary gate electrode 9 from inside to outside (the attached drawing is omitted).
In this embodiment, the two silicon oxide protective layers 4 are prepared by the same process as in embodiment 5, wherein the thickness of the silicon oxide protective layer 4 between the silicon wafer substrate 1 and the aluminum oxide passivation layer 5 is 1.2nm, and the thickness of the silicon oxide protective layer 4 between the aluminum oxide passivation layer 5 and the silicon nitride passivation and protection layer 6 is 3 nm.
Under the standard test conditions of-1500V, 85% humidity and 85 ℃ (IEC61215 or UL1703 standard), the back PID attenuation of the double-sided PERC battery piece prepared by the embodiment can be reduced by 4.0%.

Claims (11)

1. A preparation method of a high-reliability double-sided battery is characterized by comprising the following steps: and preparing a silicon oxide protective layer (4) on the back surface of the cell by means of ALD or PEALD.
2. The method for manufacturing a highly reliable bifacial battery as defined in claim 1, wherein: the silicon oxide protective layer (4) is positioned between the silicon wafer substrate (1) and the aluminum oxide passivation layer (5) on the back surface of the cell.
3. The method for manufacturing a highly reliable bifacial battery as defined in claim 2, wherein: the thickness of the silicon oxide protective layer (4) is 0.1-2 nm.
4. The method for manufacturing a highly reliable bifacial battery as defined in claim 2, wherein: and a silicon nitride passivation and protection layer (6) is arranged on the bottom surface of the aluminum oxide passivation layer (5).
5. The method for manufacturing a highly reliable bifacial battery as defined in claim 4, wherein: a silicon oxide protective layer (4) is also deposited between the aluminum oxide passivation layer (5) and the silicon nitride passivation and protective layer (6) by means of ALD or PEALD.
6. The preparation method of the double-sided battery with high reliability according to any one of claims 1 to 5, wherein the specific process flow for deposition preparation of the silicon oxide protective layer (4) is as follows:
step 1: in a vacuum environment, introducing any one precursor A of a gas-phase silicon-based precursor and an oxidant precursor into a reactor cavity, and keeping the precursor A on the back surface of a silicon wafer substrate (1) through chemical adsorption;
step 2: introducing nitrogen or inert gas for removing by-products and redundant precursors;
step 3: introducing another precursor B in the silicon-based precursor and the oxidant precursor, and reacting with the precursor A adsorbed on the silicon wafer substrate (1) to generate a silicon oxide protective film;
step 4: introducing nitrogen or inert gas again for cleaning;
step 5: repeating the above steps for different turns to grow the film layer by layer.
7. The high-reliability bifacial battery manufacturing method according to any one of claims 1-5, characterized in that: the silicon-based precursor when the silicon oxide protective layer (4) is deposited is any one of hexachlorodisilane, bis (tert-butylamino) silane, bis (diethylamino) silane, tris (dimethylamino) silane and trisilylamine; the oxidant precursor is ozone or oxygen.
8. The method for manufacturing a highly reliable bifacial battery as defined in claim 6, wherein: controlling the pressure in the reaction cavity to be 2-50mbar, the pulse time of the silicon-based precursor to be 0.1-4s and the flow rate to be 1-500sccm when the silicon oxide protective layer (4) is deposited; the pulse time of the oxidant is 1-10s, the flow rate is 1-2000sccm, and the cycle deposition times are 1-50.
9. The method for manufacturing a highly reliable bifacial battery as defined in claim 8, wherein: the preparation method specifically comprises the working procedures of texturing, diffusion, laser SE, thermal oxidation, oxidation annealing, back deposition of an aluminum oxide passivation film, back deposition of a silicon oxide film and front and back deposition of silicon nitride films, wherein the back deposition of the aluminum oxide passivation film and the back deposition of the silicon oxide film are carried out by adopting the same tube or different tubes.
10. A high-reliability double-sided battery comprises a silicon wafer substrate (1), and is characterized in that: the back of the silicon chip substrate (1) is sequentially provided with a silicon oxide protective layer (4), an aluminum oxide passivation layer (5) and a silicon nitride passivation and protective layer (6) from inside to outside, and the silicon oxide protective layer (4) is formed by deposition in an ALD or PEALD mode.
11. A high-reliability double-sided battery according to claim 10, characterized in that: a silicon oxide protective layer (4) is also deposited between the aluminum oxide passivation layer (5) and the silicon nitride passivation and protective layer (6) by means of ALD or PEALD.
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CN114447144A (en) * 2021-12-27 2022-05-06 张家港博佑光电科技有限公司 Before-after-alkali polishing protection process for PERC + SE battery
CN116995120A (en) * 2023-08-30 2023-11-03 南昌大学 Novel field passivation and high reliability photovoltaic module
CN118053919A (en) * 2024-04-15 2024-05-17 福建金石能源有限公司 Front-side specific passivated back contact solar cell, manufacturing method thereof and photovoltaic module

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