CN112864001A - Semiconductor structure, self-supporting gallium nitride layer and preparation method thereof - Google Patents

Semiconductor structure, self-supporting gallium nitride layer and preparation method thereof Download PDF

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CN112864001A
CN112864001A CN202011637943.7A CN202011637943A CN112864001A CN 112864001 A CN112864001 A CN 112864001A CN 202011637943 A CN202011637943 A CN 202011637943A CN 112864001 A CN112864001 A CN 112864001A
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layer
gallium nitride
nitride layer
gallium
patterned mask
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刘仁锁
特洛伊·乔纳森·贝克
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Jiate Semiconductor Technology Shanghai Co ltd
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Jiate Semiconductor Technology Shanghai Co ltd
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Abstract

The application particularly relates to a semiconductor structure, a self-supporting gallium nitride layer and a preparation method thereof, wherein the preparation method comprises the following steps: providing a substrate; forming a first gallium nitride layer on a substrate; forming a graphical mask layer on the first gallium nitride layer, wherein the graphical mask layer is internally provided with a plurality of openings; forming a silicon carbide layer or a graphene layer on the upper surface of the patterned mask layer and/or the upper surface of the opening exposed out of the first gallium nitride layer; and forming a second gallium nitride layer in the opening and on the upper surface of the silicon carbide layer or the upper surface of the graphene layer. In the method for manufacturing the semiconductor structure in the above embodiment, the silicon carbide layer or the graphene layer is formed on the upper surface of the patterned mask layer, and then the second gallium nitride layer is formed, so that dislocations and defects can be reduced, the crystal quality can be improved, and the second gallium nitride layer can be more easily peeled from the patterned mask layer.

Description

Semiconductor structure, self-supporting gallium nitride layer and preparation method thereof
Technical Field
The application belongs to the technical field of semiconductors, and particularly relates to a semiconductor structure, a self-supporting gallium nitride layer and a preparation method thereof.
Background
Compared with the traditional substrate material, the gallium nitride has the superior characteristics of large forbidden band width, high breakdown voltage, large heat conductivity, high electron saturation drift velocity, strong radiation resistance, good chemical stability and the like, and is a material system with the highest photoelectric and photoelectric conversion efficiency theoretically up to now.
Because of the lack of homogeneous substrates, semiconductors such as gallium nitride, aluminum nitride and the like grow on heterogeneous substrates such as sapphire, silicon carbide, silicon, gallium arsenide and the like for a long time, and the semiconductors such as gallium nitride, aluminum nitride and the like and the heterogeneous substrates have larger lattice mismatch and mismatch of thermal expansion coefficients, a large amount of dislocation and microcracks are generated on epitaxial crystals, the quality of the crystals is seriously influenced, and the performance of semiconductor-based devices such as gallium nitride, aluminum nitride and the like is further influenced, so the acquisition of the homogeneous substrates of the semiconductors such as gallium nitride, aluminum nitride and the like becomes an effective way for solving the quality of the crystals and improving the performance of the devices.
The HVPE method (Hydride Vapor Phase Epitaxy) is a preferred method for mass production of nitride substrates at high growth rates and low equipment costs, and nitride having a thickness of over 200 μm is grown on a foreign substrate by the HVPE method, and the foreign substrate is removed to obtain a free-standing nitride substrate. However, the nitride layer still grows on the foreign substrate, and doping is introduced in the growth process of part of products, so that the quality is poor, and the product performance is difficult to meet the requirements.
Disclosure of Invention
In view of the above, it is necessary to provide a semiconductor structure, a self-supporting gallium nitride layer and a method for manufacturing the same, which can solve the above problems.
One aspect of the present application provides a method for fabricating a semiconductor structure, including:
providing a substrate;
forming a first gallium nitride layer on the substrate;
forming a patterned mask layer on the first gallium nitride layer, wherein the patterned mask layer is internally provided with a plurality of openings, and the openings expose the first gallium nitride layer;
forming a silicon carbide layer or a graphene layer on the upper surface of the patterned mask layer and/or the upper surface of the first gallium nitride layer exposed by the opening;
and forming a second gallium nitride layer in the opening and on the upper surface of the silicon carbide layer or the upper surface of the graphene layer.
In the preparation method of the semiconductor structure in the embodiment, the silicon carbide layer or the graphene layer is formed on the upper surface of the patterned mask layer and/or the upper surface of the first gallium nitride layer exposed by the opening, and then the second gallium nitride layer is formed, compared with silicon dioxide or other non-gallium nitride materials (such as sapphire, silicon and the like), the silicon carbide has smaller lattice mismatch and thermal mismatch with gallium nitride, the lattice mismatch rate is only 3.4%, and meanwhile, the silicon carbide also has good electrical conductivity and thermal conductivity, and a silicon carbide thin film is formed between the patterned mask layer and the second gallium nitride layer, so that dislocation and defects generated on contact interfaces of the patterned mask layer and the gallium nitride thin film are reduced, the crystal quality is improved, and the second gallium nitride layer is easier to strip from the patterned mask layer; graphene layer can reduce second gallium nitride layer and graphical mask layer surface or opening bottom contact interface stress, is favorable to second gallium nitride layer nucleation, reduces the defect that adjacent gallium nitride closed the in-process production on graphical mask layer surface, and then improves crystal quality, helps second gallium nitride layer to peel off simultaneously.
In one embodiment, before forming the first gallium nitride layer on the substrate, a step of forming a buffer layer on an upper surface of the substrate is further included, and the first gallium nitride layer is formed on an upper surface of the buffer layer.
In one embodiment, the patterned mask layer comprises a silicon oxide layer, and the silicon oxide layer is the top of the patterned mask layer; and carbonizing the patterned mask layer to form a silicon carbide layer on the upper surface of the patterned mask layer.
In one embodiment, the second gallium nitride layer is formed as a graphene-doped gallium nitride layer.
In the above embodiment, the second gallium nitride layer is doped with graphene, that is, the three-dimensional material is filled or substituted with the two-dimensional material, so that the quality of the obtained second gallium nitride layer is significantly higher than that of the undoped second gallium nitride layer, and the dislocation and defect densities are kept at lower levels, which is beneficial to improving the carrier mobility.
In one embodiment, the step of forming the second gallium nitride layer in the opening and on the upper surface of the silicon carbide layer or the upper surface of the graphene layer includes the steps of:
placing the structure obtained after the patterned mask layer is formed in hydride vapor phase epitaxy equipment, wherein the hydride vapor phase epitaxy equipment comprises a gallium boat area and a substrate area, the structure obtained after the patterned mask layer is formed is located in the substrate area, and liquid metal gallium is placed in the gallium boat area;
introducing hydrogen chloride into the gallium boat area, and reacting the hydrogen chloride with the liquid metal gallium to generate gallium chloride; introducing ammonia gas into the substrate area, wherein the ammonia gas and the gallium chloride react in the opening to form the nucleating layer;
introducing hydrogen chloride and a carbon source into the gallium boat area, wherein the hydrogen chloride reacts with the liquid metal gallium to generate gallium chloride, and the carbon source is contacted with the liquid metal gallium to generate graphene; introducing ammonia gas into the substrate region; the gallium chloride drives the graphene to the substrate area, the ammonia gas and the gallium chloride react to form a gallium nitride layer on the upper surface of the nucleation layer and the upper surface of the silicon carbide layer or the upper surface of the graphene layer, and the gallium nitride layer and the nucleation layer jointly form the second gallium nitride layer.
The present application further provides a semiconductor structure comprising:
a substrate;
a first gallium nitride layer on the substrate;
the patterned mask layer is positioned on the upper surface of the first gallium nitride layer, a plurality of openings are formed in the patterned mask layer, and the first gallium nitride layer is exposed out of the openings;
the silicon carbide layer or the graphene layer is positioned on the upper surface of the graphical mask layer and/or the opening exposes out of the upper surface of the first gallium nitride layer;
and the second gallium nitride layer is positioned in the opening and on the upper surface of the silicon carbide layer or the upper surface of the graphene layer.
In the semiconductor structure in the above embodiment, a silicon carbide layer or a graphene layer is formed on the upper surface of the patterned mask layer and/or the upper surface of the first gallium nitride layer exposed by the opening, and compared with silicon dioxide or other non-gallium nitride materials (such as sapphire, silicon and the like), silicon carbide has smaller lattice mismatch and thermal mismatch with gallium nitride, the lattice mismatch rate is only 3.4%, and meanwhile, silicon carbide also has good electrical conductivity and thermal conductivity, and a silicon carbide thin film is formed between the patterned mask layer and the second gallium nitride layer, so that dislocation and defects generated at a contact interface between the patterned mask layer and the second gallium nitride layer are reduced, the crystal quality is improved, and the second gallium nitride layer is easier to be peeled from the patterned mask layer; graphene layer can reduce second gallium nitride layer and graphical mask layer surface or opening bottom contact interface stress, is favorable to second gallium nitride layer nucleation, reduces the defect that adjacent gallium nitride closed the in-process production on graphical mask layer surface, and then improves crystal quality, helps second gallium nitride layer to peel off simultaneously.
In one embodiment, the device further comprises a buffer layer, wherein the buffer layer is located on the upper surface of the substrate, and the first gallium nitride layer is located on the upper surface of the buffer layer.
In one embodiment, when a silicon carbide layer is formed on the upper surface of the patterned mask layer, the top layer of the patterned mask layer is a silicon oxide layer, and the silicon carbide layer is located on the upper surface of the silicon oxide layer.
In one embodiment, the second gallium nitride layer is a graphene-doped gallium nitride layer.
The application also provides a preparation method of the self-supporting gallium nitride layer, which comprises the following steps:
preparing the semiconductor structure by adopting the preparation method of the semiconductor structure in any scheme;
and cooling the semiconductor structure to enable the second gallium nitride layer to be automatically stripped so as to obtain the self-supporting gallium nitride layer.
The application also provides a self-supporting gallium nitride layer, which is prepared by the preparation method.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain drawings of other embodiments based on these drawings without any creative effort.
FIG. 1 is a flow chart of a method of fabricating a semiconductor structure provided in an embodiment of the present application;
fig. 2 is a schematic cross-sectional structure diagram of a structure obtained in step S10 in the method for manufacturing a semiconductor structure provided in an embodiment of the present application;
fig. 3 is a schematic cross-sectional structure diagram of the structure obtained in step S20 in the method for manufacturing a semiconductor structure provided in an embodiment of the present application;
fig. 4 is a schematic cross-sectional structure diagram of the structure obtained in step S30 in the method for manufacturing a semiconductor structure provided in an embodiment of the present application;
fig. 5 to 10 are schematic cross-sectional views illustrating the structure obtained in step S40 in the method for fabricating a semiconductor structure provided in an embodiment of the present application;
fig. 11 to 16 are schematic cross-sectional views illustrating the structure obtained in step S50 in the method for fabricating a semiconductor structure provided in an embodiment of the present application; fig. 11 to 16 are schematic cross-sectional views of a semiconductor structure provided in another embodiment of the present application;
fig. 17 is a schematic cross-sectional structure view of a self-supporting gallium nitride layer obtained in a method for preparing a self-supporting gallium nitride layer provided in yet another embodiment of the present application; fig. 17 is a schematic cross-sectional structure view of a self-supporting gallium nitride layer provided in another embodiment of the present application.
Description of reference numerals: 10. a substrate; 11. a first gallium nitride layer; 12. patterning the mask layer; 121. an opening; 13. a graphene layer; 14. a silicon carbide layer; 15. a second gallium nitride layer; 151. a nucleation layer; 152. a gallium nitride layer; 16. a self-supporting gallium nitride layer.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are illustrated in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
Where the terms "comprising," "having," and "including" are used herein, another element may be added unless an explicit limitation is used, such as "only," "consisting of … …," etc. Unless mentioned to the contrary, terms in the singular may include the plural and are not to be construed as being one in number.
In one embodiment, referring to fig. 1, the present application provides a method for manufacturing a memory cell structure, including the following steps:
s10: providing a substrate;
s20: forming a first gallium nitride layer on a substrate;
s30: forming a graphical mask layer on the first gallium nitride layer, wherein the graphical mask layer is internally provided with a plurality of openings which expose the first gallium nitride layer;
s40: forming a silicon carbide layer or a graphene layer on the upper surface of the patterned mask layer and/or the upper surface of the first gallium nitride layer exposed by the opening;
s50: and forming a second gallium nitride layer in the opening and on the upper surface of the silicon carbide layer or the upper surface of the graphene layer.
In the preparation method of the semiconductor structure in the embodiment, the silicon carbide layer or the graphene layer is formed on the upper surface of the patterned mask layer, and then the second gallium nitride layer is formed, compared with silicon dioxide or other non-gallium nitride materials (such as sapphire, silicon and the like), the silicon carbide has smaller lattice mismatch and thermal mismatch with gallium nitride, the lattice mismatch rate is only 3.4%, and meanwhile, the silicon carbide also has good electrical conductivity and thermal conductivity, and a silicon carbide thin film is formed between the patterned mask layer and the second gallium nitride layer, so that dislocation and defects generated on contact interfaces of the patterned mask layer and the second gallium nitride layer are reduced, the crystal quality is improved, and the second gallium nitride layer is easier to strip from the patterned mask layer; graphene layer can reduce second gallium nitride layer and graphical mask layer surface or opening bottom contact interface stress, is favorable to second gallium nitride layer nucleation, reduces the defect that adjacent gallium nitride closed the in-process production on graphical mask layer surface, and then improves crystal quality, helps second gallium nitride layer to peel off simultaneously.
In step S10, please refer to step S10 in fig. 1 and fig. 2, the substrate 10 is provided.
In one example, the substrate 10 may be any one of a silicon substrate, a sapphire substrate, a silicon carbide substrate, a gallium arsenide substrate, or an aluminum nitride substrate.
In one example, after providing the substrate and before forming the first gallium nitride layer 11 on the substrate 10, a step of forming a buffer layer (not shown) on the upper surface of the substrate 10 may be further included. Specifically, the buffer layer may be formed using, but not limited to, an MOCVD (metal organic chemical vapor deposition) process, an HVPE (metal source chemical vapor deposition) process, an MBE (molecular beam epitaxy) process, or the like. The buffer layer serves to provide a lattice mismatch that exists when the material of the substrate 10 is different from that of the first gallium nitride layer 11 that is subsequently grown.
In one example, the growth process conditions of the buffer layer may be: the growth pressure is 200Torr to 600 Torr; the growth temperature is 400-800 ℃; the carrier gas comprises nitrogen and hydrogen, the gas flow of the nitrogen is 20slm (standard liters per minute) to 80slm, and the gas flow of the hydrogen is 10slm to 60 slm; the reaction gas is ammonia gas, and the gas flow of the ammonia gas is 20 slm-70 slm; the gallium source has a gas flow rate of 10sccm (standard milliliters per minute) to 100 sccm. Specifically, in the growth process conditions of the buffer layer, the growth pressure may be 200Torr, 300Torr, 400Torr, 500Torr, 600Torr, or the like; the growth temperature can be 400 ℃, 500 ℃, 600 ℃, 700 ℃ or 800 ℃ and the like; the gas flow rate of nitrogen may be 20slm, 50slm, or 80slm, etc.; the gas flow rate of the hydrogen is 10slm, 30slm or 60slm, etc.; the gallium source has a gas flow rate of 10sccm, 40sccm, 60sccm, 100sccm, or the like.
In one example, the thickness of the buffer layer may be set according to actual needs, and specifically, the thickness of the buffer layer may be 10nm to 50 nm; more specifically, the thickness of the buffer layer may be 10nm, 20nm, 30nm, 40nm, 50nm, or the like.
In step S20, please refer to step S20 in fig. 1 and fig. 3, a first gallium nitride layer 11 is formed on the substrate 10.
In one example, the first gallium nitride layer 11 may be formed using, but not limited to, an MOCVD (metal organic chemical vapor deposition) process, an HVPE (metal source chemical vapor deposition) process, an MBE (molecular beam epitaxy) process, or the like.
In one example, the growth process conditions of the first gallium nitride layer 11 may be: the growth pressure is 100 Torr-500 Torr; the growth temperature is 800-1200 ℃; the carrier gas comprises nitrogen and ammonia, the gas flow of the nitrogen is 20 slm-80 slm, and the gas flow of the hydrogen is 10 slm-60 slm; the reaction gas is ammonia gas, and the gas flow of the ammonia gas is 20 slm-70 slm; the gas flow of the gallium source is 10sccm to 100 sccm. Specifically, in the growth process conditions of the first gallium nitride layer 11, the growth pressure may be 100Torr, 300Torr, 400Torr, 500Torr, or the like; the growth temperature can be 800 ℃, 900 ℃, 1000 ℃, 1100 ℃, 1200 ℃ or the like; the gas flow rate of nitrogen may be 20slm, 50slm, or 80slm, etc.; the gas flow rate of the hydrogen is 10slm, 30slm or 60slm, etc.; the gallium source has a gas flow rate of 10sccm, 40sccm, 60sccm, 100sccm, or the like.
In an example, the thickness of the first gallium nitride layer 11 may be set according to actual needs, and specifically, the thickness of the first gallium nitride layer 11 may be 1 μm to 6 μm; more specifically, the thickness of the first gallium nitride layer 11 may be 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, or 6 μm, or the like.
In step S30, please refer to step S30 in fig. 1 and fig. 4, a patterned mask layer 12 is formed on the first gallium nitride layer 11, the patterned mask layer 12 has a plurality of openings 121 therein, and the openings 121 expose the first gallium nitride layer 11.
In one example, the patterned mask layer 12 may be a single layer structure, and in this case, the patterned mask layer 12 may be a metal mask layer, a metal alloy mask layer, a silicon-based oxide mask layer, a silicon-based nitride mask layer, a metal oxide mask layer, or a metal nitride mask layer. The thickness of the patterned mask layer 12 may be set according to actual needs, and specifically, the thickness of the patterned mask layer 12 may be, but is not limited to, 1nm to 1000 nm; more specifically, it may be 50nm to 700 nm; in the present embodiment, the thickness of the patterned mask layer 12 may be 70nm to 300nm, such as 70nm, 100nm, 200nm, or 300 nm.
In another example, the patterned mask layer 12 may be a multi-layer structure, in which case each patterned mask layer may be a metal mask layer, a metal alloy mask layer, a silicon-based oxide mask layer, a silicon-based nitride mask layer, a metal oxide mask layer, or a metal nitride mask layer. The thickness of each patterned mask layer can be set according to actual needs, and specifically, the thickness of each patterned mask layer can be, but is not limited to, 1 nm-1000 nm; more specifically, it may be 50nm to 700 nm; in the present embodiment, the thickness of each patterned mask layer may be 70nm to 300nm, such as 70nm, 100nm, 200nm, or 300 nm.
It should be noted that, if the patterned mask layer 12 includes a multi-layer structure, the patterns of the layers in the patterned mask layer 12 are in principle consistent, and even if the patterned mask layer is manufactured by using a mask with the same pattern, the amount of deformation between the patterns of the layers and the patterns of the used mask is not more than 20% acceptable according to the process.
In one example, the shape of the opening 121 may be set according to actual needs, and the shape of the opening 121 may be a circle, an ellipse, or an equilateral shape with a variable greater than 3.
In one example, the patterned mask layer 12 may include a plurality of openings 121 therein, and the plurality of openings 121 may be arranged regularly, for example, in a matrix arrangement, a hexagonal array arrangement, or the like. In one example, the distances between centers of adjacent openings 121 may be equal, and specifically may be 1 μm to 100 μm, and more specifically may be 1 μm, 20 μm, 50 μm, 80 μm, 100 μm, or the like; in another example, the transverse distance between the centers of the adjacent openings 121 may be the same, and the longitudinal distance between the centers of the adjacent openings 121 may be the same, but the transverse distance and the longitudinal distance may be different; in yet another example, the shape of the opening 121 may be a stripe-shaped opening, the width of the stripe-shaped opening may be 1 μm to 10 μm, and specifically may be 1 μm, 5 μm, or 10 μm, and the pitch between adjacent openings 121 may be 1 μm to 10 μm, and specifically may be 1 μm, 5 μm, or 10 μm.
In one example, the area of the opening 121 in the patterned mask layer 12 accounts for 30% to 90% of the total area of the patterned mask layer 12, and in this embodiment, the area of the opening 121 accounts for 40% to 80% of the total area of the patterned mask layer 12, and may be 40%, 50%, or 60%.
In one example, step S30 may include the steps of:
s301: forming a mask layer (not shown) on the first gallium nitride layer 11; specifically, the mask layer may be formed by, but not limited to, evaporation or sputtering;
s302: the mask layer is photolithographically etched to obtain a patterned mask layer 12.
In one example, as shown in fig. 5, patterned masking layer 12 includes a silicon oxide layer (not shown), i.e., the top layer of patterned masking layer 12 is a silicon oxide layer.
In step S40, please refer to step S40 in fig. 1 and fig. 5 to 10, a silicon carbide layer 14 or a graphene layer 13 is formed on the upper surface of the patterned mask layer 12 and/or the upper surface of the opening 121 exposing the first gallium nitride layer 11.
In one embodiment, a silicon carbide layer is formed on the upper surface of patterned masking layer 12, as shown in fig. 8; at this time, the top of the patterned mask layer 12 is a silicon oxide layer, and the silicon carbide layer 14 may be formed on the upper surface of the patterned mask layer 12 by carbonizing the patterned mask layer 12. The thickness of the silicon oxide layer may be 100nm to 2000nm, and specifically may be 100nm, 500nm, 1000nm, 1500nm, or 2000 nm.
In one example, the temperature of the carbonization treatment may be 1000 ℃ to 1500 ℃, specifically, the temperature of the carbonization treatment may be 1000 ℃, 1100 ℃, 1200 ℃, 1300 ℃, 1400 ℃, 1500 ℃, or the like; the carbonization time may be 5min to 20min, and specifically, the carbonization time may be 5min, 10min, 20min, or the like.
In one example, patterned mask layer 12 may be carbonized by passing a carbon source through patterned mask layer 12. The carbon source may include at least one of methane, ethane, acetylene, and propane.
In another example, a silicon carbide layer 14 is formed on the upper surface of the first gallium nitride layer 11 exposed by the opening 121, as shown in fig. 9. Specifically, the silicon carbide layer 14 may be formed by introducing a carbon source and silane to the upper surface of the first gallium nitride layer 11 exposed by the opening 121, and reacting the carbon source with the silane.
In yet another example, a silicon carbide layer 14 may be formed on both the upper surface of the patterned mask layer 12 and the upper surface of the opening 121 exposing the first gallium nitride layer 11, as shown in fig. 10.
In yet another embodiment, a graphene layer 13 is formed on the upper surface of the patterned mask layer 12, as shown in fig. 5; specifically, the method can comprise the following steps:
placing the structure obtained after the patterned mask layer 12 is formed in hydride vapor phase epitaxy equipment (not shown), wherein the hydride vapor phase epitaxy equipment comprises a gallium boat area and a substrate area, the structure obtained after the patterned mask layer 12 is formed is located in the substrate area, and liquid metal gallium is placed in the gallium boat area;
introducing a carbon source into the gallium boat area, and reacting the carbon source with the liquid metal gallium to generate graphene; the graphene is driven by the carrier gas to the substrate region, so that a graphene layer 13 is formed on the upper surface of the patterned mask layer 12.
In yet another example, a graphene layer 13 may also be formed on the upper surface of the first gallium nitride layer 11 exposed at the opening 121, as shown in fig. 6.
In yet another example, the graphene layer 13 may be further formed on both the upper surface of the patterned mask layer 12 and the upper surface of the opening 121 exposing the first gallium nitride layer 11, as shown in fig. 7.
In step S50, please refer to step S50 in fig. 1 and fig. 11 to fig. 16, a second gallium nitride layer 15 is formed in the opening 121 and on the upper surface of the silicon carbide layer 14 or the upper surface of the graphene layer 13.
In one example, forming the second gallium nitride layer 15 in the opening 121 and on the upper surface of the silicon carbide layer 14 or the upper surface of the graphene layer 13 may include the following steps:
s501: placing the structure obtained after the patterned mask layer 12 is formed in hydride vapor phase epitaxy equipment; it should be noted that the hydride vapor phase epitaxy apparatus in this step is the same as the hydride vapor phase epitaxy apparatus in step S40; if the graphene layer 13 is formed on the upper surface of the patterned mask layer 12 in the hydride vapor phase epitaxy apparatus in step S40, step S501 may be omitted and step S502 may be directly performed;
s502: introducing hydrogen chloride into the gallium boat area, and reacting the hydrogen chloride with liquid metal gallium to generate gallium chloride; introducing ammonia gas into the substrate region, wherein the ammonia gas reacts with the gallium chloride to form a nucleation layer 151 in the opening 121;
s503: introducing hydrogen chloride and a carbon source into the gallium boat area, reacting the hydrogen chloride with liquid metal gallium to generate gallium chloride, and contacting the carbon source with the liquid metal gallium to generate graphene; introducing ammonia gas into the substrate region; since gan has a large specific surface area, as the airflow gan drives the graphene to the substrate region, the ammonia gas reacts with gan to form a gan layer 152 on the upper surface of the nucleation layer 151 and the upper surface of the silicon nitride layer 13 or the upper surface of the graphene layer 14, and the gan layer 152 and the nucleation layer 151 together form the second gan layer 15.
In one example, the flow ratio of the carbon source to the hydrogen chloride in step S503 may be 1:1 to 10:1, such as 1:1, 5:1, or 10: 1.
In one example, the flow rate of the carbon source can be 10sccm to 5000sccm, and specifically, the flow rate of the carbon source can be 10sccm, 100sccm, 200sccm, 500sccm, 1000sccm, 2000sccm, 2500sccm, 5000sccm, or the like.
Specifically, the flow rate of hydrogen sulfide can be set according to the flow rate ratio of the carbon source to hydrogen chloride and the flow rate of the carbon source, for example, when the flow rate ratio of the carbon source to hydrogen chloride is 1:1, the flow rate of the carbon source can be 10sccm and the flow rate of hydrogen chloride can be 10sccm, the flow rate of the carbon source can be 100sccm and the flow rate of hydrogen chloride can be 100sccm, the flow rate of the carbon source can be 200sccm and the flow rate of hydrogen chloride can be 200sccm, the flow rate of the carbon source can be 500sccm and the flow rate of hydrogen chloride can be 500 sccm; when the flow ratio of the carbon source to the hydrogen chloride is 5:1, the flow rate of the carbon source can be 50sccm and the flow rate of the hydrogen chloride can be 10sccm, the flow rate of the carbon source can be 500sccm and the flow rate of the hydrogen chloride can be 100sccm, the flow rate of the carbon source can be 1000sccm and the flow rate of the hydrogen chloride can be 200sccm, the flow rate of the carbon source can be 2500sccm and the flow rate of the hydrogen chloride can be 500 sccm; when the flow ratio of the carbon source to the hydrogen chloride is 10:1, the flow rate of the carbon source may be 100sccm and the flow rate of the hydrogen chloride may be 10sccm, the flow rate of the carbon source may be 1000sccm and the flow rate of the hydrogen chloride may be 100sccm, the flow rate of the carbon source may be 2000sccm and the flow rate of the hydrogen chloride may be 200sccm, and the flow rate of the carbon source may be 5000sccm and the flow rate of the hydrogen chloride may be 500 sccm.
In one example, the carbon source may include at least one of methane, ethane, acetylene, and propane.
In one example, the growth process conditions for forming the gallium nitride layer 152 in step S503 may be: the growth pressure is 500 Torr-1000 Torr; the growth temperature is 1000-1500 ℃; the growth atmosphere can comprise carrier gas and reaction gas, the carrier gas comprises nitrogen and ammonia, the gas flow of the nitrogen is 5 slm-30 slm, and the gas flow of the hydrogen is 0 slm-20 slm; the reaction gas is ammonia gas, a carbon source, hydrogen chloride and metal gallium, and the gas flow of the ammonia gas is 1 slm-15 slm; the gas flow of the carbon source is 10sccm to 5000 sccm; the gas flow rate of the hydrogen chloride is 10sccm to 500 sccm. Specifically, in the growth process conditions of the gallium nitride layer 152, the growth pressure may be 500Torr, 600Torr, 700Torr, 800Torr, 900Torr, 1000Torr, or the like; the growth temperature can be 1000 ℃, 1100 ℃, 1200 ℃, 1300 ℃, 1400 ℃ or 1500 ℃ and the like; the gas flow rate of nitrogen may be 5slm, 10slm, 20slm, or 30slm, etc.; the gas flow rate of the hydrogen is 0slm, 10slm or 20slm, etc.; the gas flow rate of the ammonia gas is 1sccm, 5sccm, 10sccm or 15sccm, etc.; the gas flow rate of the carbon source is 10slm, 500slm, 1000slm, 2000slm, 3000slm, 4000slm, 5000slm, or the like; the gas flow rate of hydrogen chloride is 10sccm, 100sccm, 200sccm, 300sccm, 400sccm, or 500sccm, etc.
In one example, the thickness of the gallium nitride layer 152 may be set according to actual needs, and the thickness of the gallium nitride layer 152 may be 200 μm to 2000 μm, and specifically may be 200 μm, 500 μm, 1000 μm, 1500 μm, or 2000 μm.
In one example, in step S503, the temperature of the hydrogen chloride and the carbon source contacting the surface of the liquid metal gallium may be 700 ℃ to 1200 ℃, specifically 700 ℃, 800 ℃, 900 ℃, 1000 ℃, 1100 ℃ or 1200 ℃.
In one example, the second gallium nitride layer 15 may be formed using, but not limited to, MOCVD, HVPE, or MBE; in the present embodiment, the second gallium nitride layer 15 is formed by an HVPE process.
In one example, no carbon source is introduced during the formation of the nucleation layer 151 in step S502, since the nucleation layer 151 needs to be formed by first forming a seed, which needs to be performed at a slow growth rate, and if the carbon source is introduced at this time, the formation of the seed is destroyed, thereby affecting the crystal quality of the gallium nitride layer 152 formed subsequently.
In one example, the thickness of nucleation layer 151 is equal to or less than the thickness of patterned mask layer 12, and in this embodiment, the thickness of nucleation layer 151 is equal to the thickness of patterned mask layer 12.
In one example, a carbon source is introduced during the process of forming the gallium nitride layer 152 in step S503, and the formed gallium nitride layer 152 is a gallium nitride layer doped with graphene. The graphene layer 13 is formed before the second gallium nitride layer 152 is formed, and a carbon source is introduced in step S503, because when the gallium nitride layer 152 is formed in step S503, the seed crystal in the opening 121 starts to be laterally merged, which easily generates a large amount of dislocations and defects in the lateral merging process, and because the graphene layer 13 is formed on the upper surface of the patterned mask layer 12 before the gallium nitride layer 152 is formed, the lateral merging is performed on the graphene surface, the dislocations and defects are significantly reduced, and simultaneously, the subsequent peeling of the second gallium nitride layer 15 from the patterned mask layer 12 is facilitated.
With continued reference to fig. 11 to 16, the present application further provides a semiconductor structure, including: a substrate 10; a first gallium nitride layer 11, the first gallium nitride layer 11 being located on the substrate 10; the patterning mask layer 12 is located on the upper surface of the first gallium nitride layer 11, the patterning mask layer 12 is provided with a plurality of openings 121, and the openings 121 expose the first gallium nitride layer 11; a silicon carbide layer 14 or a graphene layer 13, wherein the silicon carbide layer 14 or the graphene layer 13 is positioned on the upper surface of the patterned mask layer 12 and/or the first gallium nitride layer 11 exposed by the opening 121; and a second gallium nitride layer 15, wherein the second gallium nitride layer 15 is positioned in the opening 121 and on the upper surface of the silicon carbide layer 14 or the upper surface of the graphene layer 15.
In the semiconductor structure in the above embodiment, the silicon carbide layer 14 or the graphene layer 13 is disposed between the patterned mask layer 12 and the second gallium nitride layer 15, and compared with silicon dioxide or other non-gallium nitride materials (such as sapphire, silicon, etc.), silicon carbide has smaller lattice mismatch and thermal mismatch with gallium nitride, and the lattice mismatch rate is only 3.4%, and meanwhile, silicon carbide also has very good electrical conductivity and thermal conductivity, and a silicon carbide thin film is formed between the patterned mask layer 12 and the second gallium nitride layer 15, which is beneficial to reducing dislocations and defects generated at a contact interface between the patterned mask layer 12 and the second gallium nitride layer 15, and improves crystal quality, so that the second gallium nitride layer 15 is easier to be peeled off from the patterned mask layer 12; graphene layer 13 can reduce second gallium nitride layer 15 and graphical mask layer 12 surface or opening 121 bottom contact interface stress, is favorable to second gallium nitride layer 15 nucleation, reduces the defect that adjacent gallium nitride closed the in-process production on graphical mask layer 12 surface, and then improves crystal quality, helps second gallium nitride layer 15 to peel off simultaneously.
In one example, the substrate 10 may be any one of a silicon substrate, a sapphire substrate, a silicon carbide substrate, a gallium arsenide substrate, or an aluminum nitride substrate.
In one example, a buffer layer (not shown) is further included, the buffer layer is located on the upper surface of the substrate 10, and the first gallium nitride layer 11 is located on the upper surface of the buffer layer.
In one example, the thickness of the buffer layer may be set according to actual needs, and specifically, the thickness of the buffer layer may be 10nm to 50 nm; more specifically, the thickness of the buffer layer may be 10nm, 20nm, 30nm, 40nm, 50nm, or the like.
In an example, the thickness of the first gallium nitride layer 11 may be set according to actual needs, and specifically, the thickness of the first gallium nitride layer 11 may be 1 μm to 6 μm; more specifically, the thickness of the first gallium nitride layer 11 may be 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, or 6 μm, or the like.
In one example, the patterned mask layer 12 may be a single layer structure, and in this case, the patterned mask layer 12 may be a metal mask layer, a metal alloy mask layer, a silicon-based oxide mask layer, a silicon-based nitride mask layer, a metal oxide mask layer, or a metal nitride mask layer. The thickness of the patterned mask layer 12 may be set according to actual needs, and specifically, the thickness of the patterned mask layer 12 may be, but is not limited to, 1nm to 1000 nm; more specifically, it may be 50nm to 700 nm; in the present embodiment, the thickness of the patterned mask layer 12 may be 70nm to 300nm, such as 70nm, 100nm, 200nm, or 300 nm.
In another example, the patterned mask layer 12 may be a multi-layer structure, in which case each patterned mask layer may be a metal mask layer, a metal alloy mask layer, a silicon-based oxide mask layer, a silicon-based nitride mask layer, a metal oxide mask layer, or a metal nitride mask layer. The thickness of each patterned mask layer can be set according to actual needs, and specifically, the thickness of each patterned mask layer can be, but is not limited to, 1 nm-1000 nm; more specifically, it may be 50nm to 700 nm; in the present embodiment, the thickness of each patterned mask layer may be 70nm to 300nm, such as 70nm, 100nm, 200nm, or 300 nm.
It should be noted that, if the patterned mask layer 12 includes a multi-layer structure, the patterns of the layers in the patterned mask layer 12 are in principle consistent, and even if the patterned mask layer is manufactured by using a mask with the same pattern, the amount of deformation between the patterns of the layers and the patterns of the used mask is not more than 20% acceptable according to the process.
In one example, the shape of the opening 121 may be set according to actual needs, and the shape of the opening 121 may be a circle, an ellipse, or an equilateral shape with a variable greater than 3.
In one example, the patterned mask layer 12 may include a plurality of openings 121 therein, and the plurality of openings 121 may be arranged regularly, for example, in a matrix arrangement, a hexagonal array arrangement, or the like. In one example, the distances between centers of adjacent openings 121 may be equal, and specifically may be 1 μm to 100 μm, and more specifically may be 1 μm, 20 μm, 50 μm, 80 μm, 100 μm, or the like; in another example, the transverse distance between the centers of the adjacent openings 121 may be the same, and the longitudinal distance between the centers of the adjacent openings 121 may be the same, but the transverse distance and the longitudinal distance may be different; in yet another example, the shape of the opening 121 may be a stripe-shaped opening, the width of the stripe-shaped opening may be 1 μm to 10 μm, and specifically may be 1 μm, 5 μm, or 10 μm, and the pitch between adjacent openings 121 may be 1 μm to 10 μm, and specifically may be 1 μm, 5 μm, or 10 μm.
In one example, the area of the opening 121 in the patterned mask layer 12 accounts for 30% to 90% of the total area of the patterned mask layer 12, and in this embodiment, the area of the opening 121 accounts for 40% to 80% of the total area of the patterned mask layer 12, and may be 40%, 50%, or 60%.
In one example, the second gallium nitride layer 15 may include a nucleation layer 151 and a gallium nitride layer 152; nucleation layer 151 is disposed within opening 121 and gallium nitride layer 152 is disposed on patterned mask layer 12 and on the upper surface of nucleation layer 151.
In one example, the thickness of nucleation layer 151 is equal to or less than the thickness of patterned mask layer 12, and in this embodiment, the thickness of nucleation layer 151 is equal to the thickness of patterned mask layer 12.
In one example, the thickness of the gallium nitride layer 152 may be set according to actual needs, and the thickness of the gallium nitride layer 152 may be 200 μm to 2000 μm, and specifically may be 200 μm, 500 μm, 1000 μm, 1500 μm, or 2000 μm.
In one example, gallium nitride layer 152 is a graphene-doped gallium nitride layer.
In another embodiment, referring to fig. 17 in conjunction with fig. 1 to 16, the present application further provides a method for preparing a self-supporting gallium nitride layer, including:
preparing the semiconductor structure by using the method for preparing a semiconductor structure according to any scheme; with reference to the foregoing embodiments, specific methods for fabricating semiconductor structures will not be described again;
the semiconductor structure is subjected to a temperature reduction treatment so that the second gallium nitride layer 15 is automatically peeled off to obtain a self-supporting gallium nitride layer 16, as shown in fig. 17.
In one example, the semiconductor structure may be naturally cooled to room temperature, and during the cooling process, the second gallium nitride layer 15 is automatically peeled off to obtain the self-supporting gallium nitride layer 16.
In one example, the semiconductor structure may be cooled to room temperature at a cooling rate of 5 ℃/min to 30 ℃/min, and during the cooling process, the second gallium nitride layer 15 is automatically peeled off to obtain the self-supporting gallium nitride layer 16. Specifically, the cooling rate can be 5 ℃/min, 10 ℃/min, 15 ℃/min, 20 ℃/min, 25 ℃/min or 30 ℃/min.
In one example, after the self-supporting gallium nitride layer 16 is obtained, the self-supporting gallium nitride layer 16 may be further subjected to a grinding and polishing process.
In yet another embodiment, with continued reference to fig. 17, the present application further provides a self-supporting gan layer 16, wherein the self-supporting gan layer 16 is prepared by the above-mentioned method.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (11)

1. A method for fabricating a semiconductor structure, comprising:
providing a substrate;
forming a first gallium nitride layer on the substrate;
forming a patterned mask layer on the first gallium nitride layer, wherein the patterned mask layer is internally provided with a plurality of openings, and the openings expose the first gallium nitride layer;
forming a silicon carbide layer or a graphene layer on the upper surface of the patterned mask layer and/or the upper surface of the first gallium nitride layer exposed by the opening;
and forming a second gallium nitride layer in the opening and on the upper surface of the silicon carbide layer or the upper surface of the graphene layer.
2. The method according to claim 1, further comprising a step of forming a buffer layer on an upper surface of the substrate before forming the first gallium nitride layer on the substrate, wherein the first gallium nitride layer is formed on an upper surface of the buffer layer.
3. The method of claim 1, wherein the patterned mask layer comprises a silicon oxide layer, the silicon oxide layer being a top portion of the patterned mask layer; and carbonizing the patterned mask layer to form a silicon carbide layer on the upper surface of the patterned mask layer.
4. The method according to any one of claims 1 to 3, wherein the second gallium nitride layer is formed as a graphene-doped gallium nitride layer.
5. The method of claim 4, wherein forming the second gallium nitride layer within the opening and on the top surface of the silicon carbide layer or the top surface of the graphene layer comprises:
placing the structure obtained after the patterned mask layer is formed in hydride vapor phase epitaxy equipment, wherein the hydride vapor phase epitaxy equipment comprises a gallium boat area and a substrate area, the structure obtained after the patterned mask layer is formed is located in the substrate area, and liquid metal gallium is placed in the gallium boat area;
introducing hydrogen chloride into the gallium boat area, and reacting the hydrogen chloride with the liquid metal gallium to generate gallium chloride; introducing ammonia gas into the substrate area, wherein the ammonia gas and the gallium chloride react in the opening to form the nucleating layer;
introducing hydrogen chloride and a carbon source into the gallium boat area, wherein the hydrogen chloride reacts with the liquid metal gallium to generate gallium chloride, and the carbon source is contacted with the liquid metal gallium to generate graphene; introducing ammonia gas into the substrate region; the gallium chloride drives the graphene to the substrate area, the ammonia gas and the gallium chloride react to form a gallium nitride layer on the upper surface of the nucleation layer and the upper surface of the silicon carbide layer or the upper surface of the graphene layer, and the gallium nitride layer and the nucleation layer jointly form the second gallium nitride layer.
6. A semiconductor structure, comprising:
a substrate;
a first gallium nitride layer on the substrate;
the patterned mask layer is positioned on the upper surface of the first gallium nitride layer, a plurality of openings are formed in the patterned mask layer, and the first gallium nitride layer is exposed out of the openings;
the silicon carbide layer or the graphene layer is positioned on the upper surface of the graphical mask layer and/or the opening exposes out of the upper surface of the first gallium nitride layer;
and the second gallium nitride layer is positioned in the opening and on the upper surface of the silicon carbide layer or the upper surface of the graphene layer.
7. The semiconductor structure of claim 6, further comprising a buffer layer on an upper surface of the substrate, the first gallium nitride layer on an upper surface of the buffer layer.
8. The semiconductor structure of claim 6, wherein when a silicon carbide layer is formed on the upper surface of the patterned mask layer, the top layer of the patterned mask layer is a silicon oxide layer, and the silicon carbide layer is located on the upper surface of the silicon oxide layer.
9. The semiconductor structure of any of claims 6 to 8, wherein the second gallium nitride layer is a graphene-doped gallium nitride layer.
10. A method for preparing a self-supporting gallium nitride layer is characterized by comprising the following steps:
preparing the semiconductor structure by using the method for preparing a semiconductor structure according to any one of claims 1 to 5;
and cooling the semiconductor structure to enable the second gallium nitride layer to be automatically stripped so as to obtain the self-supporting gallium nitride layer.
11. A self-supporting gallium nitride layer, characterized in that it is prepared by the preparation method according to claim 10.
CN202011637943.7A 2020-12-31 2020-12-31 Semiconductor structure, self-supporting gallium nitride layer and preparation method thereof Pending CN112864001A (en)

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