CN112861457B - Model order reduction method, device and medium of delay circuit system - Google Patents
Model order reduction method, device and medium of delay circuit system Download PDFInfo
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Abstract
The invention discloses a model order reduction method of a delay circuit system, which comprises the following steps: establishing a corresponding delay circuit model based on the circuit structure and the circuit parameters of the delay circuit; carrying out Laplace transformation on the delay circuit model to obtain a first transfer function; acquiring a delay term based on the first transfer function; obtaining a delay function and a transformation factor based on the hermite polynomial and the delay term; acquiring a transformation function based on the delay function and the transformation factor, and setting a recurrence relation based on the transformation function; orthogonalization processing is carried out based on an orthometric algorithm and a recurrence relation to obtain a projection matrix; performing projective transformation on the delay circuit model based on the projective matrix to obtain a reduced order model of the delay circuit; the invention can utilize the Hermite polynomial to carry out order reduction processing on the model of the high-speed interconnection circuit system, meets the order reduction standard of the high-speed interconnection circuit system, ensures the passivity and the structural property of the circuit system before order reduction, and further improves the stability of the circuit system after order reduction.
Description
Technical Field
The present invention relates to the field of integrated circuit design technologies, and in particular, to a method, an apparatus, and a medium for model order reduction of a delay circuit system.
Background
When designing an integrated circuit, designing an interconnection line, and considering delay when designing the interconnection line, so that modeling analysis is performed on an interconnected delay circuit system to obtain a corresponding differential equation model containing delay terms; the existing interconnection delay circuit has large scale, so that the differential equation model needs to be subjected to reduced order processing;
the existing order reduction methods have two kinds: the first is to process the delay term after Taylor expansion in the differential equation model by utilizing the model reduction of the linear system; the second is to use Gramia (gram matrix ) matrix to perform reduced order processing on the differential equation model; in the order reduction process, the passivity and the structural property of the circuit system before order reduction cannot be ensured, so that the circuit system after order reduction is unstable and the physical meaning of the circuit system before order reduction cannot be reflected.
Disclosure of Invention
The invention mainly solves the problem that the passivity and the structural performance of the interconnected delay circuit system cannot be ensured before the model is reduced.
In order to solve the technical problems, the invention adopts a technical scheme that: there is provided a model reduction method of a delay circuit system, applied to a delay circuit model, the method comprising the steps of:
establishing a corresponding delay circuit model based on the circuit structure and the circuit parameters of the delay circuit;
carrying out Laplace transformation on the delay circuit model to obtain a first transfer function;
obtaining a delay term based on the first transfer function;
obtaining a delay function and a transformation factor based on the hermite polynomial and the delay term;
acquiring a transformation function based on the delay function and the transformation factor, and setting a recurrence relation based on the transformation function;
orthogonalizing based on an orthometric algorithm and the recurrence relation to obtain a projection matrix;
and performing projective transformation on the delay circuit model based on the projective matrix to obtain a reduced order model of the delay circuit.
As an improvement, the step of obtaining a delay term based on the first transfer function includes:
performing taylor expansion on the first transfer function to obtain a first taylor expansion;
the delay term is determined in the first taylor expansion.
As an improvement, the step of obtaining the delay function and the transform factor based on the hermite polynomial and the delay term further includes:
approximating the delay term by adopting a Hermite polynomial to obtain the delay function;
setting a transformation polynomial;
and obtaining a delay factor of the delay function, modifying the delay factor according to the transformation polynomial, and defining the modified delay factor as the transformation factor.
As an improvement, the step of obtaining a transformation function based on the delay function and the transformation factor, and setting a recurrence relation based on the transformation function further includes:
substituting the transformation factor into the delay function to obtain a transformation function;
and determining a first order of the transformation function, and setting the recurrence relation according to the first order and the transformation function.
As an improved solution, the step of orthogonalizing based on the orthogonal algorithm and the recurrence relation to obtain a projection matrix further includes:
creating a gram Lei Luofu subspace based on the recurrence relation;
and carrying out orthogonalization processing on the gram Lei Luofu subspace by adopting the orthogonalization algorithm to obtain the projection matrix.
As an improvement, the step of creating a gram Lei Luofu subspace based on the recurrence relation further includes:
substituting the transformation factor and the transformation function into the first transfer function to obtain a second transfer function;
performing taylor expansion on the second transfer function to obtain a second taylor expansion;
calculating a first moment value according to the recurrence relation and the second taylor expansion; the gram Lei Luofu subspace is created from the first moment.
As an improvement, the step of orthogonalizing the gram Lei Luofu subspace by using the orthogonalization algorithm to obtain the projection matrix further includes:
setting the circulation times;
carrying out orthogonalization processing on the gram Lei Luofu subspace according to the cycle times and the orthogonalization algorithm to obtain a plurality of matrix vectors;
and integrating the matrix vectors to obtain the projection matrix.
As an improvement, the projective transformation includes:
acquiring each state variable and each coefficient matrix of the delay circuit model;
substituting the state variables and the coefficient matrixes into the projection matrix to obtain transformed state variables and coefficient matrixes;
and respectively replacing each state variable and each coefficient matrix in the delay circuit model with each transformed state variable and each coefficient matrix to obtain the reduced order model.
The invention also provides a model order reduction device of the delay circuit system, which is applied to a delay circuit model and comprises:
a first processor, a second processor, and a third processor;
the first processor is used for establishing a corresponding delay circuit model according to the circuit structure and the circuit parameters of the delay circuit, and carrying out Laplace transformation on the delay circuit model to obtain a first transfer function; the first processor obtains a delay term through the first transfer function; the first processor obtains a delay function and a transformation factor through a Hermite polynomial and the delay term;
the second processor is used for obtaining a transformation function according to the delay function and the transformation factor, and setting a recurrence relation according to the transformation function;
the third processor is used for carrying out orthogonalization processing according to an orthogonalization algorithm and the recurrence relation to obtain a projection matrix, and carrying out projection transformation on the delay circuit model according to the projection matrix to obtain a reduced order model of the delay circuit.
The present invention also provides a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the model reduction method of delay circuitry.
The beneficial effects of the invention are as follows:
1. the model order reduction method of the delay circuit system can realize order reduction processing on the model of the high-speed interconnection circuit system by utilizing the Hermite matrix, thereby not only meeting the order reduction standard of the high-speed interconnection circuit system, but also ensuring the passivity and the structural property of the circuit system before order reduction, further improving the stability of the circuit system after order reduction and enabling the circuit system after order reduction to show the physical significance of the circuit system before order reduction.
2. The model order reduction device of the delay circuit system can realize order reduction processing on the model of the high-speed interconnection circuit system by the mutual coordination of the first processor, the second processor and the third processor, thereby meeting order reduction standards of the high-speed interconnection circuit system, ensuring the passivity and the structural property of the circuit system before order reduction, further improving the stability of the circuit system after order reduction, and enabling the circuit system after order reduction to show the physical significance of the circuit system before order reduction.
3. The computer readable storage medium can realize the coordination of the first processor, the second processor and the third processor, further realize the order reduction processing of the model of the high-speed interconnection circuit system by utilizing the Hermite matrix, not only meet the order reduction standard of the high-speed interconnection circuit system, but also ensure the passivity and the structural property of the circuit system before order reduction, further improve the stability of the circuit system after order reduction, enable the circuit system after order reduction to embody the physical meaning of the circuit system before order reduction, and effectively increase the operability of the model order reduction method of the delay circuit system.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a model reduction method of a delay circuit system according to embodiment 1 of the present invention;
FIG. 2 is a schematic diagram of a model reduction method of a delay circuit system according to embodiment 1 of the present invention;
FIG. 3 is a schematic diagram of the output response of the pre-order reduction system and the post-order reduction system according to embodiment 1 of the present invention;
FIG. 4 is a schematic diagram of the relative errors of the system before and after the step down according to embodiment 1 of the present invention;
fig. 5 is a schematic diagram of a model reduction device of delay circuit system according to embodiment 2 of the present invention.
Detailed Description
The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby making clear and defining the scope of the present invention.
In the description of the present invention, it should be noted that the described embodiments of the present invention are some, but not all embodiments of the present invention; all other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the description of the present invention, it should be noted that Krylov is an iterative algorithm, arnoldi is a polynomial fitting algorithm, and the RLC circuit is a circuit composed of a resistor, an inductor, and a capacitor.
In the description of the present invention, it should be noted that the terms "first," "second," "third," and "fourth" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, unless explicitly specified and defined otherwise, the terms "delay circuit model", "delay function", "transformation factor", "recurrence relation", "projection matrix", "state variable", "coefficient matrix", "reduced order model", "transfer function", "orthometric algorithm", "subspace", "first moment value", "orthometric process" are to be understood in a broad sense. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
Example 1
The embodiment provides a model order reduction method of a delay circuit system, as shown in fig. 1 to 4, comprising the following steps:
s100, carrying out mathematical modeling on the interconnection circuit system to obtain a corresponding delay circuit mathematical model (namely a delay circuit model);
the step S100 specifically includes:
modeling a transmission line part of the interconnection circuit system by adopting a telegraph equation to obtain a first circuit model; modeling the lumped parameter part of the interconnection circuit system by adopting an improved node voltage method to obtain a second circuit model; combining the first circuit model and the second circuit model to obtain the delay circuit mathematical model;
the mathematical model of the delay circuit is as follows:
the delay circuit mathematical model comprises the following state variables and coefficient matrixes:
the value of matrix E consists of inductance L and inductance C, and E ε R n×n The method comprises the steps of carrying out a first treatment on the surface of the The matrix A consists of the association relation of resistance value, conductance value and each device in the circuit system, and A is E R n×n The method comprises the steps of carrying out a first treatment on the surface of the Matrix A i Is a coefficient matrix of a delay structure in a circuit system, and A i ∈R n×n The method comprises the steps of carrying out a first treatment on the surface of the B is an input matrix, where u (t) is the input value and B ε R n×1 ；B T Is an output matrix, and B T ∈R 1×n The method comprises the steps of carrying out a first treatment on the surface of the x (t) belongs to an unknown variable and represents node voltage or branch current in the circuit system; n is the first order of the mathematical model of the delay circuit, which represents the number of unknowns in the whole mathematical model; r is the specification size of each matrix; τ is the delay; t\T is a time variable; m is the interconnection in the circuit systemThe number of lines, i, is a random variable relative to m.
S200, executing a first calculation step on the delay circuit mathematical model to obtain a delay function and a transformation factor;
the step S200 specifically includes:
the first calculation step is as follows:
s201, carrying out Laplace transformation on the mathematical model of the delay circuit to obtain a first transfer function of the mathematical model of the delay circuit; the first transfer function represents the expression form of the circuit system before the reduction in the frequency domain, and the expression form comprises all information of the whole circuit system before the reduction;
the first transfer function is:
where s is a complex frequency variable, which is defined as a "delay factor" in the following steps, and is used for descriptive purposes only.
S202, performing taylor expansion on the transfer function at s=0, to obtain a first taylor expansion of the first transfer function:
wherein a key moment "Mi" in the first taylor expansion represents important information of the pre-reduction circuitry.
S203, determining a key moment Mi and a delay term in the first Taylor expansion
/>
In the prior art, when Mi is calculated, taylor expansion is needed to be carried out on a delay term, approximation values of the previous terms are taken, new variables are needed to be introduced in the calculation process, corresponding calculation amount is increased, and the structural property of the system before the reduction cannot be maintained in the finally obtained reduction system; the present embodiment efficiently processes the delay term by the following method.
S204, performing approximate treatment on the delay term by adopting a Hermite polynomial to obtain a delay function of the Hermite polynomial;
wherein H is n (x) Is the hermite expansion coefficient; although the delay function is generated, the delay function cannot be directly used for approximate expansion of the delay term, so the next step is performed:
s205, obtaining a delay factor S in the delay function, and performing higher-order transformation on the delay factor S (namely setting a polynomial u) 2 -2u and modifying the delay factor to the polynomial) to obtain a transform factor u 2 -2u；
For example: after this higher order transformation, the delay term is:
alpha in the above formulae i And τ i Meaning is the same, i.e. alpha i ＝τ i ；
S300, executing a second calculation step based on the delay function and the transformation factor to obtain a recurrence relation;
the step S300 specifically includes:
s301, substituting the transformation factor into the delay function to obtain a transformation function;
s302, substituting the transformation factor and the transformation function into the first transfer function together to obtain a second transfer function;
s303, carrying out Taylor expansion on the second transfer function to obtain a second Taylor expansion:
the solution of the key moment "Mi" according to the second taylor expansion is relatively complex, so that the calculation of Mi is performed by setting a recurrence relation.
S303, confirming a first order n in the transformation function; setting a recurrence relation of Mi according to the first order:
for example: if n=3, then there is the following recurrence relation;
in the recurrence relation, the following relation exists:
in the above formulae, +.;
s400, calculating a projection matrix based on the recurrence relation;
the step S400 specifically includes:
s401, calculating the key moment according to the recursive relation and the second Taylor expansion, and creating a p-order Krylov subspace (namely a gram Lei Luofu subspace) according to the key moment; wherein (p) is set to be greater than or equal to 2); when p of the p-order Krylov subspace is selected, p=n is selected, and the recursion relation obtained according to n before verification accords with the p-order Krylov subspace;
for example: when n=3, the 3-order Krylov subspace is:
s402, configuring an orthogonal algorithm, and carrying out orthogonalization processing on the Krylov subspace by adopting the orthogonal algorithm to obtain a projection matrix V, wherein a projection order r is configured in the projection matrix V, and r is far smaller than n; in this embodiment, the selected orthogonal algorithm is Arnoldi algorithm, which is relatively stable compared to other orthogonal algorithms, but the orthogonal algorithm is not limited;
for example: in this embodiment, the steps of the Arnoldi algorithm are as follows:
the following relationship is satisfied when proceeding to the calculation for the intermediate matrix U according to the usual arnold algorithm: type of ≡ 0 U=b; QR decomposition is carried out on the intermediate matrix U to obtain v 0 V, i.e 0 ＝qr(U)；
Setting a first cycle number i, and calculating a submatrix according to the i cycle
Setting a second cycle number j, and calculating according to the cycles of i and j
Here H represents the intermediate matrix in the same sense as U, i.e. without other physical meaning, as expressed only;
after the cycle is completed, according to H to v i Statistics is performed, i.e
Integrating said v i Obtaining the projection matrix V= [ V ] 0 ,v 1 ,…,v r ]The method comprises the steps of carrying out a first treatment on the surface of the After the projection matrix is obtained, the following steps can be executed according to the projection matrix, so that the order reduction effect achieved by the method described in the embodiment is achieved;
the method comprises the following steps: because the set projection order r is far smaller than n, in the process of circuit simulation analysis, a great amount of calculation amount is reduced; in addition, the order reduction system keeps the passivity of the interconnection circuit system before order reduction, and can still embody the physical meaning of the interconnection circuit system before order reduction;
the method comprises the following steps:
s500, reducing the order of the delay circuit mathematical model according to a projection matrix;
the step S500 specifically includes:
acquiring a state variable and a coefficient matrix of the delay circuit mathematical model, projecting the state variable and the coefficient matrix into the projection matrix V to obtain a plurality of reduced elements (namely a second state variable and a second coefficient matrix), and correspondingly replacing the original state variable and coefficient matrix by the reduced elements to obtain a reduced system;
the order-reducing elements are as follows: x is x r ＝V T x，E r ＝V T EV∈R r×r ，A r ＝V T AV∈R r×r ，A ir ＝V T A i V∈R r×r ，B r ＝V T B∈R r×1 ，
The reduced elements respectively correspond to state variables and coefficient matrixes in the delay circuit mathematical model;
the order reduction system is as follows:
in this embodiment, an effect test is performed on the reduced order system obtained by the method, where the tested interconnection circuit system is composed of an RLC circuit containing lumped parameters and three interconnection lines containing distributed parameters;
performing mathematical modeling on the RLC circuit network by adopting an improved node voltage method to obtain a 432-order mathematical mode; the order of the reduced system obtained according to the method is 18;
through simulation test, the input of the system before the order reduction and the system after the order reduction are sin (pi is 2*t) +1/3 sin (3 pi is 2 t), the comparison of the output responses of the system before the order reduction and the system after the order reduction is shown in fig. 3, and the output relative errors of the system before the order reduction and the system after the order reduction are shown in fig. 4;
the analysis of the image shows that the method has good order reduction effect, and ensures the passivity and the structural property of the system before order reduction.
Example 2
The present embodiment provides a model order reduction device of a delay circuit system, as shown in fig. 5, including:
a first processor, a second processor, and a third processor;
before the device executes operation, a first circuit model is obtained by modeling a transmission line part of an interconnection circuit system in advance by adopting a telegraph equation; modeling the lumped parameter part of the interconnection circuit system by adopting an improved node voltage method to obtain a second circuit model; combining the first circuit model and the second circuit model to obtain a delay circuit mathematical model;
the first processor is used for executing a first calculation step on the delay circuit mathematical model to obtain a delay function and a transformation factor;
when the first processor executes the first calculation step, the method specifically includes:
the first processor performs Laplace transformation on the mathematical model of the delay circuit to obtain a first transfer function of the mathematical model of the delay circuit;
the first processor performs Taylor expansion on the transfer function to obtain a first Taylor expansion of the first transfer function;
a first processor determines key moments and delay terms in the first taylor expansion;
the first processor approximates the delay term by adopting a Hermite polynomial to obtain a delay function of the Hermite polynomial;
the first processor acquires a delay factor in the delay function, and carries out high-order transformation on the delay factor to obtain a transformation factor;
after the first processor obtains a delay function and a transformation factor, the first processor sends a first processing signal to the second processor; after the second processor receives the first processing signal, executing a second calculation step:
the second processor executing the second calculating step specifically includes:
substituting the transformation factor into the delay function by the second processor to obtain a transformation function;
substituting the transformation factor and the transformation function into the first transfer function by the second processor to obtain a second transfer function;
the second processor performs taylor expansion on the second transfer function to obtain a second taylor expansion;
the second processor acknowledges the first order in the transform function; setting a recurrence relation of key moment according to the first order:
when the second processor obtains the recurrence relation, a second processing signal is sent to a third processor, and after the third processor receives the first processing signal, a corresponding step is executed;
the third processor calculates a projection matrix through the recurrence relation;
when the third processor executes the operation, the method specifically includes:
a third processor calculates the key moment according to the recursive relation and the second Taylor expansion, and creates a multi-order Krylov subspace according to the key moment;
the third processor configures an orthogonal algorithm, the third processor adopts the orthogonal algorithm to orthogonalize the Krylov subspace to obtain the projection matrix, the projection order is set for the projection matrix, and the projection order is far smaller than the first order; in this embodiment, the selected orthogonal algorithm is Arnoldi algorithm, which is relatively stable compared to other orthogonal algorithms, but the orthogonal algorithm is not limited;
after the third processor obtains the projection matrix, the third processor reduces the delay circuit mathematical model through the projection matrix;
when the third processor executes the operation, the method specifically further comprises:
and the third processor acquires a state variable and a coefficient matrix of the delay circuit mathematical model, projects the state variable and the coefficient matrix into the projection matrix to obtain a plurality of reduced elements (namely a second state variable and a second coefficient matrix), and correspondingly replaces the original state variable and coefficient matrix by the reduced elements to obtain the reduced system.
Because the set projection order is far smaller than the first order, the calculation amount is reduced in the process of circuit simulation analysis; in addition, the order reduction system maintains the passivity of the interconnection circuit system before order reduction, and can still embody the physical meaning of the interconnection circuit system before order reduction.
Based on the same inventive concept as the model reduction method of the delay circuit system in the foregoing embodiments, the present disclosure further provides a computer-readable storage medium, on which a computer program is stored, which when executed by a processor, implements the steps of the model reduction method of the delay circuit system.
Compared with the prior art, the model order reduction method, device and medium for the delay circuit system can realize order reduction processing on the model of the high-speed interconnection circuit system by utilizing the Hermite matrix, not only meets the order reduction standard of the high-speed interconnection circuit system, but also ensures the passivity and the structural property of the circuit system before order reduction, and provides technical support for the method through the first processor, the second processor and the third processor, so that the method is realized, the stability of the circuit system after order reduction is improved, and the circuit system after order reduction can embody the physical significance of the circuit system before order reduction.
The foregoing embodiment of the present invention has been disclosed with reference to the number of embodiments for the purpose of description only, and does not represent the advantages or disadvantages of the embodiments.
It will be appreciated by those of ordinary skill in the art that all or part of the steps of implementing the above embodiments may be implemented by hardware, or a program implemented by a program to instruct related hardware may be stored in a computer readable storage medium, where the storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
The foregoing description is only illustrative of the present invention and is not intended to limit the scope of the invention, and all equivalent structures or equivalent processes or direct or indirect application in other related technical fields are included in the scope of the present invention.
Claims (7)
1. A method for model reduction of delay circuitry, comprising the steps of:
establishing a corresponding delay circuit model based on the circuit structure and the circuit parameters of the delay circuit; the delay circuit model is as follows:
wherein: matrix E consists of the inductance and the inductance of the delay circuit, and +.>
The method comprises the steps of carrying out a first treatment on the surface of the Matrix A is composed of the resistance value, conductance value and the relation of devices in the delay circuit, and +.>
；A i Is a coefficient matrix of a delay structure in a delay circuit, and +.>
The method comprises the steps of carrying out a first treatment on the surface of the B is the input matrix, u (t) is the input value, and +.>
；B T Is an output matrix, and->
The method comprises the steps of carrying out a first treatment on the surface of the x (t) is an unknown variable, represents node voltage or branch current in a delay circuit, n is a first order of the delay circuit model, represents the number of unknowns in the delay circuit model, and R is the specification of each matrix; />
Is the i-th delay; t is a time variable; m is the number of interconnect lines in the delay circuit, i is a random variable relative to m, i=1, 2,..m;
and carrying out Laplace transformation on the delay circuit model to obtain a first transfer function, wherein the first transfer function is as follows:
wherein s is a complex frequency variable;
acquiring a delay term based on the first transfer function, wherein the delay term is
；
Obtaining a delay function and a transformation factor based on the hermite polynomial and the delay term;
acquiring a transformation function based on the delay function and the transformation factor, and setting a recurrence relation based on the transformation function;
orthogonalizing based on an orthometric algorithm and the recurrence relation to obtain a projection matrix;
performing projective transformation on the delay circuit model based on the projective matrix to obtain a reduced order model of the delay circuit, wherein the reduced order model is
Wherein, the method comprises the steps of, wherein,
，/>
，/>
，/>
，
，/>
；
the step of obtaining a delay function and a transformation factor based on the hermite polynomial and the delay term further comprises: approximating the delay term by adopting a Hermite polynomial to obtain the delay function; the delay function is
Wherein->
Is the hermite expansion coefficient; setting a transformation polynomial, wherein the transformation polynomial is u 2 -2u; obtaining a delay factor of the delay function, wherein the delay factor is s, modifying the delay factor according to the transformation polynomial, defining the modified delay factor as the transformation factor, and the transformation factor is u 2 -2u；
The step of obtaining a transformation function based on the delay function and the transformation factor, and setting a recurrence relation based on the transformation function further includes: substituting the transformation factor into the delay function to obtain a transformation function, wherein the transformation function is as follows:
wherein->
And τ i Meaning the same; determining a first order of the transform function, the first order comprising 3; setting the recurrence relation according to the first order and the transformation function; the recurrence relation includes: />
；
；
；
；
Wherein: m is M i Represents a key moment;
B；/>
B；
B；/>
B；
the step of obtaining a projection matrix further comprises the steps of: creating a gram Lei Luofu subspace based on the recurrence relation, the gram Lei Luofu subspace comprising:
the method comprises the steps of carrying out a first treatment on the surface of the Carrying out orthogonalization processing on the gram Lei Luofu subspace by adopting the orthogonalization algorithm to obtain the projection matrix, wherein the projection matrix is +.>
Wherein->
，j=1,2,...,r。
2. The model reduction method of delay circuitry of claim 1, wherein: the step of obtaining a delay term based on the first transfer function includes:
performing taylor expansion on the first transfer function to obtain a first taylor expansion, wherein the first taylor expansion is as follows:
；
the delay term is determined in the first taylor expansion.
3. The model reduction method of delay circuitry of claim 2, wherein: the step of creating a gram Lei Luofu subspace based on the recurrence relation further comprises:
substituting the transformation factor and the transformation function into the first transfer function to obtain a second transfer function, wherein the second transfer function is as follows:
performing taylor expansion on the second transfer function to obtain a second taylor expansion, wherein the second taylor expansion is as follows:
calculating a first moment value according to the recursive relation and the second Taylor expansion, wherein the first moment value is the key moment M i The method comprises the steps of carrying out a first treatment on the surface of the The gram Lei Luofu space is created from the first moment value.
4. A method of model reduction of delay circuitry according to claim 2 or 3, wherein: the step of orthogonalizing the gram Lei Luofu subspace by using the orthogonalization algorithm to obtain the projection matrix further comprises:
setting the circulation times;
carrying out orthogonalization processing on the gram Lei Luofu subspace according to the cycle times and the orthogonalization algorithm to obtain a plurality of matrix vectors, wherein the matrix vectors are the
；
And integrating the matrix vectors to obtain the projection matrix.
5. The model reduction method of delay circuitry of claim 1, wherein: the projective transformation includes:
acquiring each state variable and each coefficient matrix of the delay circuit model, wherein each state variable and each coefficient matrix comprises: in the delay circuit model
、/>
、/>
、/>
And->
；
Substituting the state variables and the coefficient matrixes into the projection matrix to obtain transformed state variables and coefficient matrixes, wherein the transformed state variables and coefficient matrixes comprise: in the reduced order model
、/>
、/>
、
、/>
And->
；
And respectively replacing each state variable and each coefficient matrix in the delay circuit model with each transformed state variable and each coefficient matrix to obtain the reduced order model.
6. A model reducing apparatus of a delay circuit system based on a model reducing method of a delay circuit system according to claim 1, applied to a delay circuit model, characterized in that the apparatus comprises: a first processor, a second processor, and a third processor;
the first processor is used for establishing a corresponding delay circuit model according to the circuit structure and the circuit parameters of the delay circuit, and carrying out Laplace transformation on the delay circuit model to obtain a first transfer function; the first processor obtains a delay term through the first transfer function; the first processor obtains a delay function and a transformation factor through a Hermite polynomial and the delay term; the first processor is further configured to perform approximation processing on the delay term by using a hermite polynomial to obtain the delay function; the first processor sets a transform polynomial; the first processor obtains a delay factor of the delay function and modifies the delay factor according to the transformation polynomial, and the first processor defines the modified delay factor as the transformation factor;
the second processor is used for obtaining a transformation function according to the delay function and the transformation factor, and setting a recurrence relation according to the transformation function; the second processor is further configured to substitute the transformation factor into the delay function to obtain a transformation function; the second processor determines a first order of the transformation function and sets the recurrence relation according to the first order and the transformation function;
the third processor is used for carrying out orthogonalization processing according to an orthogonalization algorithm and the recurrence relation to obtain a projection matrix, and carrying out projection transformation on the delay circuit model according to the projection matrix to obtain a reduced order model of the delay circuit; the third processor creates a gram Lei Luofu subspace based on the recurrence relation; and the third processor adopts the orthogonalization algorithm to conduct orthogonalization processing on the gram Lei Luofu subspace to obtain the projection matrix.
7. A computer readable storage medium, wherein a computer program is stored on the computer readable storage medium, and the computer program when executed by a processor implements the steps of the model reduction method of the delay circuit system of any one of claims 1 to 5.
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