CN114117999B - Method and device for reducing order of interconnection line mathematical model, electronic equipment and storage medium - Google Patents
Method and device for reducing order of interconnection line mathematical model, electronic equipment and storage medium Download PDFInfo
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Abstract
The application discloses a method and device for reducing order of an interconnection line mathematical model, electronic equipment and a storage medium. The method comprises the following steps: detecting parasitic parameters of an interconnection line in the target chip, and obtaining an interconnection line mathematical model by using kirchhoff's law; establishing an error value between a transfer function of an original interconnection line mathematical model and a transfer function of a target reduced interconnection line system; determining a local optimal solution of the error value based on a relaxation Newton interpolation iterative algorithm, and establishing a target projection matrix corresponding to the interconnection line mathematical model by utilizing interpolation points at the optimal solution; and reducing the order of the mathematical model of the internal interconnection line of the original target chip based on the target projection matrix, and performing simulation calculation to obtain a simulation result. The method solves the problem that the target projection matrix corresponding to the interconnection line mathematical model is established, and the interconnection line mathematical model is compressed to the greatest extent under the conditions of the input and output precision and the passivity of the interconnection line, so that the analysis simulation time of the interconnection line mathematical model is greatly saved.
Description
Technical Field
The present disclosure relates to the field of circuit simulation technologies, and in particular, to a method and apparatus for reducing an order of an interconnection line mathematical model, an electronic device, and a storage medium.
Background
Along with the rapid development of integrated circuit technology, the integration level of chips is higher and higher, the scale of internal interconnection lines is larger and larger, the working frequency is also increased continuously, and the analysis and verification of circuits are required to process mathematical problems with large scale. In the prior art, a model order reduction method aiming at an interconnection line mathematical model mainly comprises a model order reduction method based on a Krylov subspace and a balance cut model order reduction method, but the passivity of an order reduction system obtained by the method is sometimes not ensured, so that the effect of simulating a circuit by the finally obtained interconnection line mathematical model is poor.
Disclosure of Invention
In order to solve the technical problems or at least partially solve the technical problems, the application provides a method, a device, electronic equipment and a storage medium for reducing an interconnection line mathematical model.
According to an aspect of the embodiments of the present application, there is provided a method for reducing an interconnection line mathematical model, including:
detecting parasitic parameters of an interconnection line in the target chip, and obtaining an interconnection line mathematical model by using kirchhoff's law;
establishing an error value between a transfer function of an original interconnection line mathematical model and a transfer function of a target reduced interconnection line system;
determining a local optimal solution of the error value based on a relaxation Newton interpolation iterative algorithm, and establishing a target projection matrix corresponding to the interconnection line mathematical model by utilizing interpolation points at the optimal solution;
and reducing the order of the mathematical model of the internal interconnection line of the original target chip based on the target projection matrix, and performing simulation calculation to obtain a simulation result.
Further, the detecting the parasitic parameter of the interconnect line inside the target chip to obtain the mathematical model of the interconnect line includes:
determining a plurality of interconnect line branches included in the target chip internal interconnect line;
detecting parasitic parameters within each interconnect line branch, wherein the parasitic parameters include: inductance, resistance, capacitance;
constructing the interconnection line mathematical model according to the parasitic parameters, wherein the interconnection line mathematical model is as follows:
where i (τ) is the branch current, M is the matrix of inductance values, D is the matrix of resistance values, K is the matrix of inverse capacitance values, B is the input matrix, and C is the output matrix.
Further, the establishing the error value between the transfer function of the original interconnection line mathematical model and the transfer function of the target reduced interconnection line system includes:
determining a target transfer function corresponding to the interconnection line mathematical model and an initial target system transfer function, wherein the initial target system transfer function is a transfer function obtained according to a preset reduced-order matrix;
establishing an error value between a transfer function of an original interconnection line mathematical model and a transfer function of a target reduced interconnection line system according to the initial target system transfer function and the initial target system transfer function, wherein the error value is expressed as follows:
wherein G(s) is the transfer function of the original interconnection line mathematical model, G r (s) a target transfer function,to initiate the target system transfer function, H 2 Is the error value.
Further, the determining a locally optimal solution of the error value based on the relaxation newton interpolation iterative algorithm includes:
performing iterative decomposition on the target projection matrix to obtain a characteristic value set of the target projection matrix in a current iterative period;
arranging the characteristic values in the characteristic value set in sequence from large to small, selecting target characteristic values with the same number as the target order from the arranged characteristics, and determining a first extreme point in the target characteristic values;
obtaining a second extreme point, wherein the second extreme point is obtained in the last iteration period of the target projection matrix;
and determining a difference value between the first extreme point and the second extreme point, and constructing the target reduced order matrix according to the target characteristic value under the condition that the difference value is smaller than the target error.
Further, the establishing the target projection matrix corresponding to the interconnection line mathematical model by using the interpolation point at the optimal solution includes:
determining the current reduced target order of the interconnection line mathematical model, and randomly selecting the same number of target interpolation points according to the target order;
and constructing a target projection matrix based on the target interpolation points and the interconnection line mathematical model.
Further, the target projection matrix is:
in the formula, { sigma } 1 、σ r 、....、σ 2r All are target interpolation points, V r 、W r Is a target projection matrix.
Furthermore, the step of reducing the mathematical model of the internal interconnection line of the original target chip based on the target projection matrix is performed to obtain a simulation result, and the step of performing simulation calculation comprises the following steps:
acquiring test data for testing the internal interconnection line of the target chip;
inputting the test data into the target reduced order matrix to obtain a simulation result of the interconnection line under the test data.
According to another aspect of the embodiments of the present application, there is also provided a device for reducing the order of a mathematical model of an interconnection line, including:
the detection module is used for detecting parasitic parameters of the internal interconnection line of the target chip and obtaining an interconnection line mathematical model by using kirchhoff's law;
the construction module is used for establishing an error value between a transfer function of the original interconnection line mathematical model and a transfer function of the target reduced interconnection line system;
the determining module is used for determining a local optimal solution of the error value based on a relaxation Newton interpolation iterative algorithm and establishing a target projection matrix corresponding to the interconnection line mathematical model by utilizing interpolation points at the optimal solution;
and the calculation module is used for reducing the order of the mathematical model of the internal interconnection line of the original target chip based on the target projection matrix, and carrying out simulation calculation to obtain a simulation result.
According to another aspect of the embodiments of the present application, there is also provided a storage medium including a stored program that performs the steps described above when running.
According to another aspect of the embodiments of the present application, there is provided an electronic device including a processor, a communication interface, a memory, and a communication bus, where the processor, the communication interface, and the memory complete communication with each other through the communication bus; wherein: a memory for storing a computer program; and a processor for executing the steps of the method by running a program stored on the memory.
Embodiments of the present application also provide a computer program product comprising instructions which, when run on a computer, cause the computer to perform the steps of the above method.
Compared with the prior art, the technical scheme provided by the embodiment of the application has the following advantages: the method solves the problems that a mode of establishing a target projection matrix corresponding to the interconnection line mathematical model and carrying out iterative decomposition on the target projection matrix is adopted, the interconnection line mathematical model is compressed to the greatest extent under the conditions of input and output precision and passivity of the interconnection line, and the simulation time of the interconnection line mathematical model is greatly saved.
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The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the description of the embodiments or the prior art will be briefly described below, and it will be obvious to those skilled in the art that other drawings can be obtained from these drawings without inventive effort.
FIG. 1 is a flowchart of a method for reducing the order of a mathematical model of an interconnect line according to an embodiment of the present disclosure;
FIG. 2 is a flow chart of a method for reducing the order of a mathematical model of an interconnect line according to another embodiment of the present application;
FIG. 3 is a schematic diagram of an interconnect line in a chip according to an embodiment of the present disclosure;
FIG. 4 is a flow chart of a method for reducing the order of a mathematical model of an interconnect line according to another embodiment of the present application;
FIG. 5 is a block diagram of a device for reducing the order of a mathematical model of an interconnect line according to an embodiment of the present application;
fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments, the exemplary embodiments of the present application and the descriptions thereof are used to explain the present application and do not constitute undue limitations of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present application based on the embodiments herein.
It should be noted that in this document, relational terms such as "first" and "second" and the like are used solely to distinguish one entity or action from another similar entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The embodiment of the application provides a method and device for reducing an interconnection line mathematical model, electronic equipment and a storage medium. The method provided by the embodiment of the invention can be applied to any needed electronic equipment, for example, the electronic equipment can be a server, a terminal and the like, is not particularly limited, and is convenient to describe and is called as the electronic equipment for short hereinafter.
According to an aspect of the embodiments of the present application, a method embodiment for reducing an interconnection line mathematical model is provided. Fig. 1 is a flowchart of a method for reducing an interconnection line mathematical model according to an embodiment of the present application, as shown in fig. 1, where the method includes:
and S11, detecting parasitic parameters of the internal interconnection line of the target chip to obtain an interconnection line mathematical model.
In the embodiment of the application, the parasitic parameters of the interconnect line inside the target chip are detected to obtain the mathematical model of the interconnect line, as shown in fig. 2, including the following steps A1-A3:
and step A1, determining a plurality of interconnection line branches included in the interconnection line inside the target chip.
Step A2, detecting parasitic parameters in each interconnection line branch, wherein the parasitic parameters comprise: inductance, resistance, capacitance.
In this embodiment of the present application, the interconnect is divided into a plurality of interconnect segments with lumped parameters, and the interconnect can be equivalent by RLC circuit with reference to fig. 3, and parasitic parameters in each interconnect branch, such as capacitance, inductance, and resistance in fig. 3, are detected and detected.
And step A3, constructing an interconnection line mathematical model according to the parasitic parameters.
In the embodiment of the application, after parasitic parameters are obtained, a matrix corresponding to each parasitic parameter is constructed, and finally, an initial interconnection line mathematical model is built according to the matrix corresponding to each parasitic parameter and kirchhoff's law, and in order to facilitate the reduction, the initial interconnection line mathematical model is converted to obtain a final interconnection line mathematical model, wherein the interconnection line mathematical model is as follows:
in the above equation, i (τ) is a branch current, M is a matrix of inductance values, D is a matrix of resistance values, K is a matrix of inverse capacitance values, B is an input matrix, and C is an output matrix.
In the formula, M is E R N×N ，D∈R N×N ，K∈R N×N ，B∈R N×N ，C∈R N×N 。
It should be noted that, because the scale of the formula is huge, most of the matrixes in the formula are sparse matrixes, the calculation amount for directly solving the mathematical model of the interconnection line is huge, in order to solve the simulation analysis problem of the interconnection line, the model needs to be reduced by a model reduction method, and the obtained smaller system can keep the input-output relation, the passivity and other important circuit properties of the original system. The existing model order-reducing algorithm has higher calculation complexity, and the passivity of the obtained order-reducing system cannot be ensured. Based on the above, the embodiment of the application adopts a target projection matrix mode to perform order reduction.
And step S12, establishing an error value between the transfer function of the original interconnection line mathematical model and the transfer function of the target reduced interconnection line system.
In the embodiment of the present application, step S12, establishing an error value between a transfer function of an original interconnect line mathematical model and a transfer function of a target reduced interconnect line system, includes the following steps B1-B2:
step B1, determining a target transfer function corresponding to an interconnection line mathematical model and an initial target system transfer function, wherein the initial target system transfer function is a transfer function obtained according to a preset reduced-order matrix;
in the embodiment of the application, the order reduction requirement uploaded by the user is acquired, and the order reduction requirement carries a target order number which needs to reduce the order of the interconnection line. Then randomly selecting the same number of r target interpolation points { sigma } according to the target orders 1 ，σ 1 ，...,σ r }。
And step B2, establishing an error value between the transfer function of the original interconnection line mathematical model and the transfer function of the target reduced interconnection line system according to the initial target system transfer function and the initial target system transfer function.
In the embodiment of the application, first, laplace transformation is performed on an interconnection line mathematical model to obtain a transfer function of the interconnection line mathematical model, as follows:
G(s)＝C(s 2 M+sD+K) -1 and B, wherein s is a variable in the frequency domain.
The error value is formulated as follows:
wherein G(s) is the transfer function of the original interconnection line mathematical model, G r (s) target transfer function, < >>To initiate the target system transfer function, H 2 Is the error value.
Since the purpose of the embodiments of the present application is to obtain a stable mathematical model of the interconnect line, it is assumed that the initial target system transfer function of the mathematical model of the interconnect line is G(s).
The model reduction is converted into an optimization problem in the form of solving the above formula. According to the residue theory, canThe conversion is as follows:
in the above formula, phi,The original system transfer function G(s) and the final target system transfer function G, respectively r (s) interpolation at target sigma i 、/>The remainder of the process. The formula shows H between the mathematical model of the interconnection line and the preset reduced order matrix 2 Errors are mainly due to mismatch between transfer functions at the negative value points of the system. Based on the above, the embodiment of the application adopts a method of carrying out iterative decomposition on the projection matrix to find a reduced-order matrix, so that the transfer function of the reduced-order matrix can be matched with the transfer function of the interconnection line mathematical model at the negative value point.
And S13, determining a local optimal solution of the error value based on a relaxation Newton interpolation iterative algorithm, and establishing a target projection matrix corresponding to the interconnection line mathematical model by utilizing interpolation points at the optimal solution.
In the embodiment of the present application, step S13, determining a locally optimal solution of the error value based on the relaxed newton interpolation iterative algorithm, as shown in fig. 4, includes the following steps C1-C4:
and step C1, carrying out iterative decomposition on the target projection matrix to obtain a characteristic value set of the target projection matrix in the current iterative period.
And C2, arranging the characteristic values in the characteristic value set according to the sequence from large to small, selecting the target characteristic values with the same number as the target order from the arranged characteristics, and determining a first extreme value in the target characteristic values.
And C3, acquiring a second extreme point, wherein the second extreme point is obtained in the last iteration period of the target projection matrix.
And C4, determining a difference value between the first extreme point and the second extreme point, and constructing a target reduced-order matrix according to the target characteristic value under the condition that the difference value is smaller than the target error.
In the implementation of the present application, in the process of calculating the reduced order matrix according to the projection matrix, first, the coefficient matrix corresponding to the coefficient of the original system in each projection matrix is converted to obtain the reduced order matrix corresponding to each coefficient matrix, which is specifically as follows:
after obtaining the reduced order matrix corresponding to each coefficient matrix, establishing an integral reduced order system (namely a target reduced order system) according to the reduced order matrix corresponding to each coefficient matrix, wherein the reduced order system is as follows:
the extreme point of the order reduction system is calculated by adopting an iterative decomposition mode, and the calculation process is as follows: first, determining parameters of reduced order matrix of each coefficient matrix, lambda 2 M r +λD r +K r =0. Wherein lambda is a preset parameter, lambda i =1, 2,..2 r. Assigning-lambda to sigma i I.e. sigma i ＝-λ i Sigma is calculated as i Inputting the target projection matrix to obtain a matrix V 2r Sum matrix W 2r Then the characteristic values are arranged from big to small to obtain the first R characteristic values, namely [ V, R ]]＝eig(V 2r )，[W,R]＝eig(W 2r )。
And then determining a first extreme point from the previous r characteristic values, and acquiring a second extreme point corresponding to the target projection matrix in the previous iteration period. Comparing the first extreme point with the second extreme point machine, if the difference between the first extreme point and the second extreme point is smaller than the target error, determining the current iteration period as the final iteration period, and outputting the current obtained reduced order matrixes V and W.
As an example, it is determined whether an iteration stop condition is satisfied, that is, an error between an extreme point of a reduced matrix obtained by the current iteration and an extreme point of a reduced matrix obtained by the previous iteration is less than 0.0001. If the iteration stop condition is not satisfied, the iteration decomposition operation is continued.
In the embodiment of the present application, step S13, a target projection matrix corresponding to the mathematical model of the interconnection line is established by using interpolation points at the optimal solution, including the following steps D1-D2:
step D1, determining the current reduced target order of the interconnecting line mathematical model, and randomly selecting the same number of target interpolation points according to the target order;
and D2, constructing a target projection matrix based on the target interpolation points and the interconnection line mathematical model.
In the embodiment of the present application, the target projection matrix is:
in the formula, { sigma } 1 、σ r 、....、σ 2r All are target interpolation points, V r 、W r Is a target projection matrix.
The method for carrying out iterative decomposition on the target projection matrix in the embodiment of the application finds a reduced-order matrix, and the specific process of enabling the transfer function of the reduced-order matrix to be matched with the transfer function of the interconnection line mathematical model at the negative value point is as follows:
first, a group of interpolation points { sigma } is selected 1 ,σ 2 ,....,σ i And the constructed reduced order matrix is matched with the original interconnection line mathematical model at interpolation points. On the one hand, the extreme points of the reduced order matrix are set asFrom this extreme point construction function g (σ) =λ (σ) +σ, the order of the difference points is ignored, and the relationship between the extreme point and the interpolation point can be obtained. Thus, the root of g (σ) =0 can be determined using the following formula k+1 ＝σ k -(I-J) -1 (σ k λ(σ k ) Where I is an identity matrix and J is sigma k Jacobian matrix at σ. The root of g (σ) =0 can be found by an iterative process to the above formula, and a reduced order matrix can be constructed. In most cases, the Jacobian matrix values are very small, j=0 can be taken, resulting in a relaxed iterative strategy, i.e., σ i+1 ←λ i (σ i )。
And (3) taking the interpolation point in the step (i+1) as the negative value point of the reduced system obtained in the step (i) iteration in the iteration process. The reduced order system constructed for each iteration is obtained according to the projection method. The projection matrix construction strategy is:
the target reduced order matrix may be determined based on the above formula.
And then calculating the extreme points of the target reduced order matrix, and taking the obtained extreme points as interpolation points of the next iterative decomposition. The order of the target reduced matrix is r, r extreme points can be obtained in the iterative decomposition process, the r extreme points are used as interpolation points of the next iteration, the two projection matrices are doubled, the iteration is gradually carried out, and the obtained reduced matrix is larger and larger in scale, so that the matrix is decomposed by using the eigenvalue decomposition method in order to control the scale of the reduced matrix.
Then selecting the feature vector corresponding to the larger feature value in V and W as the projection matrix V of the next iteration r And W is equal to r The problem of controlling the scale of the reduced order system is solved, and in the iteration process, when the difference between extreme points of the reduced order matrix obtained in two iterations is smaller than the target error, the extreme points are set as iteration stop conditions, and the final target reduced order matrix can be obtained and is madeThe input-output relation, the passivity and other important properties of the original system are reserved.
And S14, reducing the order of the mathematical model of the internal interconnection line of the original target chip based on the target projection matrix, and performing simulation calculation to obtain a simulation result.
In the embodiment of the application, the simulation calculation is performed on the internal interconnection line of the target chip based on the target reduced order matrix to obtain a simulation result, and the method comprises the following steps of E1-E2:
step E1, obtaining test data for testing an internal interconnection line of a target chip;
and E1, inputting the test data into a target reduced order matrix to obtain a simulation result of the interconnection line under the test data.
The method solves the problems that a target projection matrix corresponding to the interconnection line mathematical model is established, a final target reduced-order interconnection line system is obtained through the target projection matrix, the interconnection line mathematical model is compressed to the greatest extent under the condition that the input and output precision and the passivity of the interconnection line are maintained, and the simulation time of the interconnection line mathematical model is greatly saved.
Fig. 5 is a block diagram of a device for reducing the order of a mathematical model of an interconnection line according to an embodiment of the present application, where the device may be implemented as part or all of an electronic device by software, hardware, or a combination of both. As shown in fig. 5, the apparatus includes:
the detection module 51 is configured to detect parasitic parameters of an interconnect line inside the target chip, and obtain an interconnect line mathematical model using kirchhoff's law;
a building module 52, configured to build an error value between a transfer function of the original interconnect mathematical model and a transfer function of the target reduced interconnect system;
the determining module 53 is configured to determine a locally optimal solution of the error value based on a loose newton interpolation iterative algorithm, and establish a target projection matrix corresponding to the interconnection line mathematical model by using interpolation points at the optimal solution;
the calculation module 54 is configured to reduce the order of the mathematical model of the internal interconnection line of the original target chip based on the target projection matrix, and perform a simulation calculation to obtain a simulation result.
In the embodiment of the present application, the detection module 51 is configured to determine a plurality of interconnect line branches including the interconnect line inside the target chip; detecting parasitic parameters within each interconnect line branch, wherein the parasitic parameters include: inductance, resistance, capacitance; constructing an interconnection line mathematical model according to the parasitic parameters, wherein the interconnection line mathematical model is as follows:
where i (τ) is the branch current, M is the matrix of inductance values, D is the matrix of resistance values, K is the matrix of inverse capacitance values, B is the input matrix, and C is the output matrix.
In the embodiment of the present application, the construction module 52 is configured to determine a target transfer function corresponding to the interconnection line mathematical model, and an initial target system transfer function, where the initial target system transfer function is a transfer function obtained according to a preset reduced order matrix; according to the error value between the initial target system transfer function and the original system transfer function, the formula of the error value is as follows:
wherein G(s) is the original system transfer function, G r (s) a final target system transfer function,to initiate the target system transfer function, H 2 Is the error value.
In this embodiment of the present application, the determining module 53 is configured to perform iterative decomposition on the target projection matrix to obtain a set of eigenvalues of the target projection matrix in a current iteration period; arranging the characteristic values in the characteristic value set according to the sequence from big to small, selecting target characteristic values with the same number as the target order from the arranged characteristics, and determining a first extreme point in the target characteristic values; obtaining a second extreme point, wherein the second extreme point is obtained in the last iteration cycle of the target projection matrix; and determining a difference value between the first extreme point and the second extreme point, and constructing a target reduced order matrix according to the target characteristic value under the condition that the difference value is smaller than the target error.
In this embodiment of the present application, the determining module 53 is configured to determine a target order of a current reduced order of the interconnection line mathematical model, and randomly select the same number of target interpolation points according to the target order; and constructing a target projection matrix based on the target interpolation points and the interconnection line mathematical model.
In the embodiment of the present application, the target projection matrix is:
in the formula, { sigma } 1 、σ r 、....、σ 2r All are target interpolation points, V r 、W r Is a target projection matrix.
In the embodiment of the present application, the calculation module 54 is configured to obtain test data for testing the internal interconnection line of the target chip; inputting the test data into the target reduced order matrix to obtain the simulation result of the interconnection line under the test data.
The embodiment of the application further provides an electronic device, as shown in fig. 6, the electronic device may include: the device comprises a processor 1501, a communication interface 1502, a memory 1503 and a communication bus 1504, wherein the processor 1501, the communication interface 1502 and the memory 1503 are in communication with each other through the communication bus 1504.
A memory 1503 for storing a computer program;
the processor 1501, when executing the computer program stored in the memory 1503, implements the steps of the above embodiments.
The communication bus mentioned by the above terminal may be a peripheral component interconnect standard (Peripheral Component Interconnect, abbreviated as PCI) bus or an extended industry standard architecture (Extended Industry Standard Architecture, abbreviated as EISA) bus, etc. The communication bus may be classified as an address bus, a data bus, a control bus, or the like. For ease of illustration, the figures are shown with only one bold line, but not with only one bus or one type of bus.
The communication interface is used for communication between the terminal and other devices.
The memory may include random access memory (Random Access Memory, RAM) or non-volatile memory (non-volatile memory), such as at least one disk memory. Optionally, the memory may also be at least one memory device located remotely from the aforementioned processor.
The processor may be a general-purpose processor, including a central processing unit (Central Processing Unit, CPU for short), a network processor (Network Processor, NP for short), etc.; but also digital signal processors (Digital Signal Processing, DSP for short), application specific integrated circuits (Application Specific Integrated Circuit, ASIC for short), field-programmable gate arrays (Field-Programmable Gate Array, FPGA for short) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.
In yet another embodiment provided herein, a computer readable storage medium having instructions stored therein that when run on a computer cause the computer to perform the method of reducing the mathematical model of an interconnect line as described in any of the above embodiments.
In yet another embodiment provided herein, there is also provided a computer program product containing instructions that, when run on a computer, cause the computer to perform the method of reducing the mathematical model of an interconnect line as described in any of the above embodiments.
In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, produces a flow or function in accordance with embodiments of the present application, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line), or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid State Disk), etc.
The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the scope of the present application. Any modifications, equivalent substitutions, improvements, etc. that are within the spirit and principles of the present application are intended to be included within the scope of the present application.
The foregoing is merely a specific embodiment of the application to enable one skilled in the art to understand or practice the application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (5)
1. A method for reducing the order of a mathematical model of an interconnect line, comprising:
detecting parasitic parameters of an interconnection line in the target chip, and obtaining an interconnection line mathematical model by using kirchhoff's law;
establishing an error value between a transfer function of an original interconnection line mathematical model and a transfer function of a target reduced interconnection line system;
determining a local optimal solution of the error value based on a relaxation Newton interpolation iterative algorithm, and establishing a target projection matrix corresponding to the interconnection line mathematical model by utilizing interpolation points at the optimal solution;
reducing the order of an original internal interconnection line mathematical model of the target chip based on the target projection matrix, and performing simulation calculation to obtain a simulation result;
and detecting parasitic parameters of the internal interconnection line of the target chip to obtain an interconnection line mathematical model, wherein the method comprises the following steps of:
determining a plurality of interconnect line branches included in the target chip internal interconnect line;
detecting parasitic parameters within each interconnect line branch, wherein the parasitic parameters include: inductance, resistance, capacitance;
constructing the interconnection line mathematical model according to the parasitic parameters, wherein the interconnection line mathematical model is as follows:
wherein i (τ) is a branch current, M is a matrix composed of inductance values, D is a matrix composed of resistance values, K is a matrix composed of inverse capacitance values, B is an input matrix, and C is an output matrix;
the establishing the error value between the transfer function of the original interconnection line mathematical model and the transfer function of the target reduced interconnection line system comprises the following steps:
determining a target transfer function corresponding to the interconnection line mathematical model and an initial target system transfer function, wherein the initial target system transfer function is a transfer function obtained according to a preset reduced-order matrix;
establishing an error value between a transfer function of an original interconnection line mathematical model and a transfer function of a target reduced interconnection line system according to the initial target system transfer function and the initial target system transfer function, wherein the error value is expressed as follows:
wherein G(s) is the transfer function of the original interconnection line mathematical model, G r (s) a target transfer function,to initiate the target system transfer function, H 2 Is an error value;
the method for determining the local optimal solution of the error value based on the relaxation Newton interpolation iterative algorithm comprises the following steps:
performing iterative decomposition on the target projection matrix to obtain a characteristic value set of the target projection matrix in a current iterative period;
arranging the characteristic values in the characteristic value set in sequence from large to small, selecting target characteristic values with the same number as the target order from the arranged characteristics, and determining a first extreme point in the target characteristic values;
obtaining a second extreme point, wherein the second extreme point is obtained in the last iteration period of the target projection matrix;
determining a difference value between the first extreme point and the second extreme point, and constructing a target reduced-order matrix according to the target characteristic value under the condition that the difference value is smaller than a target error;
the establishing a target projection matrix corresponding to the interconnection line mathematical model by using interpolation points at the optimal solution comprises the following steps:
determining the current reduced target order of the interconnection line mathematical model, and randomly selecting the same number of target interpolation points according to the target order;
constructing a target projection matrix based on the target interpolation points and the interconnection line mathematical model;
the target projection matrix is as follows:
in the formula, { sigma } 1 、σ r 、....、σ 2r All are target interpolation points, V r 、W r Is a target projection matrix.
2. The method of claim 1, wherein the performing a simulation calculation to reduce the order of the mathematical model of the interconnect line inside the original target chip based on the target projection matrix to obtain a simulation result comprises:
acquiring test data for testing the internal interconnection line of the target chip;
inputting the test data into the target reduced order matrix to obtain a simulation result of the interconnection line under the test data.
3. A device for reducing the order of a mathematical model of an interconnect line, comprising:
the detection module is used for detecting parasitic parameters of the internal interconnection line of the target chip and obtaining an interconnection line mathematical model by using kirchhoff's law;
the construction module is used for establishing an error value between a transfer function of the original interconnection line mathematical model and a transfer function of the target reduced interconnection line system;
the determining module is used for determining a local optimal solution of the error value based on a relaxation Newton interpolation iterative algorithm and establishing a target projection matrix corresponding to the interconnection line mathematical model by utilizing interpolation points at the optimal solution;
the calculation module is used for reducing the order of the mathematical model of the internal interconnection line of the original target chip based on the target projection matrix, and performing simulation calculation to obtain a simulation result;
a detection module, configured to determine a plurality of interconnect branches included in the interconnect inside the target chip; detecting parasitic parameters within each interconnect line branch, wherein the parasitic parameters include: inductance, resistance, capacitance; constructing an interconnection line mathematical model according to the parasitic parameters, wherein the interconnection line mathematical model is as follows:
wherein i (τ) is a branch current, M is a matrix composed of inductance values, D is a matrix composed of resistance values, K is a matrix composed of inverse capacitance values, B is an input matrix, and C is an output matrix;
the construction module is used for determining a target transfer function corresponding to the interconnection line mathematical model and an initial target system transfer function, wherein the initial target system transfer function is a transfer function obtained according to a preset reduced-order matrix; establishing an error value between a transfer function of an original interconnection line mathematical model and a transfer function of a target reduced interconnection line system according to the initial target system transfer function and the initial target system transfer function, wherein the error value is expressed as follows:
wherein G(s) is the transfer function of the original interconnection line mathematical model, G r (s) a target transfer function,to initiate the target system transfer function, H 2 Is an error value;
the determining module is used for carrying out iterative decomposition on the target projection matrix to obtain a characteristic value set of the target projection matrix in the current iterative period; arranging the characteristic values in the characteristic value set according to the sequence from big to small, selecting target characteristic values with the same number as the target order from the arranged characteristics, and determining a first extreme point in the target characteristic values; obtaining a second extreme point, wherein the second extreme point is obtained in the last iteration cycle of the target projection matrix; determining a difference value between the first extreme point and the second extreme point, and constructing a target reduced-order matrix according to the target characteristic value under the condition that the difference value is smaller than the target error;
the determining module is used for determining the current reduced target order of the interconnection line mathematical model and randomly selecting the same number of target interpolation points according to the target order; constructing a target projection matrix based on the target interpolation points and the interconnection line mathematical model;
the target projection matrix is:
in the formula, { sigma } 1 、σ r 、....、σ 2r All are target interpolation points, V r 、W r Is a target projection matrix.
4. A storage medium comprising a stored program, wherein the program when run performs the method steps of any of the preceding claims 1 to 2.
5. The electronic equipment is characterized by comprising a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory are communicated with each other through the communication bus; wherein:
a memory for storing a computer program;
a processor for performing the method steps of any of claims 1-2 by running a program stored on a memory.
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| CN111859835A (en) * | 2020-06-29 | 2020-10-30 | 浪潮电子信息产业股份有限公司 | Order reduction method, order reduction device and order reduction equipment of circuit interconnection network model |
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| CN111859835A (en) * | 2020-06-29 | 2020-10-30 | 浪潮电子信息产业股份有限公司 | Order reduction method, order reduction device and order reduction equipment of circuit interconnection network model |
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