CN112860044B - Control circuit and control device - Google Patents
Control circuit and control device Download PDFInfo
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- CN112860044B CN112860044B CN202110095312.5A CN202110095312A CN112860044B CN 112860044 B CN112860044 B CN 112860044B CN 202110095312 A CN202110095312 A CN 202110095312A CN 112860044 B CN112860044 B CN 112860044B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
Abstract
The invention discloses a control circuit and control equipment, which are used for solving the problem that the performance of an OPS computer in an interactive all-in-one machine in the prior art is influenced due to illegal power failure. In the embodiment of the invention, the comparison circuit generates a first level signal representing external power failure and a second level signal representing the duration of the continuous output port control signal of the signal integration circuit, the shutdown judgment circuit generates a fourth level signal triggering the signal integration circuit to work, and the signal integration circuit generates a control signal for controlling shutdown of the controlled equipment according to the first level signal, the second level signal and the fourth level signal.
Description
Technical Field
The invention relates to the technical field of power supply, in particular to a control circuit and control equipment.
Background
In recent years, the interactive all-in-one machine integrates functions of a projector, an electronic whiteboard, a computer, a television, a sound device, a power amplifier and the like by means of advanced intelligent hardware technology, integrates technologies such as high-definition display, writing, annotation, drawing, man-machine interaction, multimedia entertainment and the like, and is widely applied to markets such as school education, enterprise conferences, large-scale exhibitions and the like.
The wide use of the interactive all-in-one machine expands the application of the OPS (Open plug capable Specification) in the industries of education, conference and the like, and the OPS computer is powered by a power panel of the interactive all-in-one machine, so that the OPS computer is easily subjected to illegal power failure caused by abnormal power failure of the interactive all-in-one machine, and the system breakdown or hardware damage of the OPS computer can be caused by long-term illegal power failure to influence the computer performance.
Disclosure of Invention
The invention provides a control circuit and control equipment, which are used for solving the problem that the performance of an OPS computer in an interactive all-in-one machine in the prior art is influenced due to illegal power failure.
In a first aspect, an embodiment of the present invention provides a control circuit, including: the circuit comprises a comparison circuit, a delay circuit, a shutdown judgment circuit and a signal integration circuit; wherein the content of the first and second substances,
the comparison circuit is used for generating a first level signal for representing external power failure according to the input voltage value of the external power supply end and the input voltage value of the internal power supply end, generating a second level signal for representing the duration of the continuous output control signal of the signal integration circuit according to the voltage value of the output voltage output by the delay circuit and the voltage value of the internal power supply end, inputting the first level signal to the delay circuit and the signal integration circuit respectively, and inputting the second level signal to the signal integration circuit;
the delay circuit is used for generating the output voltage according to the first level signal and a voltage value of a endurance power supply, wherein the endurance power supply is a power supply for supplying power to the controlled equipment after external power failure;
the shutdown judgment circuit is used for generating a fourth level signal for triggering the signal integration circuit to work according to an input third level signal for representing the standby state of the controlled equipment;
the signal integration circuit is configured to generate the control signal for controlling the controlled device to shut down according to the fourth level signal, the first level signal, and the second level signal, and output the control signal to the controlled device.
In one possible implementation, the comparison circuit includes a first comparator, a second comparator, a first resistor, a second resistor, a third resistor, and a fourth resistor, where:
one end of the first resistor is connected with the external power supply end, and the other end of the first resistor is respectively connected with one end of the second resistor and the negative input end of the first comparator;
the other end of the second resistor is grounded;
one end of the third resistor is connected with the internal power supply end, and the other end of the third resistor is respectively connected with the positive input end of the first comparator, the positive input end of the second comparator and one end of the fourth resistor;
the other end of the fourth resistor is grounded;
a power supply end of the first comparator is connected with the internal power supply end, and an output end of the first comparator outputs the first level signal;
and a power supply end of the second comparator is connected with the internal power supply end, a negative input end of the second comparator is connected with an output end of the delay circuit, the output voltage is input, and an output end of the second comparator outputs the second level signal.
In a possible implementation manner, the comparison circuit further includes a voltage stabilizing diode, an anode of the voltage stabilizing diode is grounded, a cathode of the voltage stabilizing diode is connected with the internal power supply terminal, and a common terminal of the voltage stabilizing diode is connected with the other terminal of the first resistor and a cathode input terminal of the first comparator respectively.
In one possible implementation manner, the delay circuit includes a first switch tube, a second switch tube, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a resistor component, and a capacitor component, where:
one end of the fifth resistor is connected with the output end of the first comparator and one end of the sixth resistor respectively, and the other end of the fifth resistor is connected with the internal power supply end;
the control end of the first switching tube is respectively connected with the other end of the sixth resistor and one end of the ninth resistor, the first power end of the first switching tube is connected with one end of the eighth resistor, and the second power end of the first switching tube is grounded;
the control end of the second switching tube is respectively connected with the other end of the eighth resistor and one end of the seventh resistor, the first power end of the second switching tube is respectively connected with one end of the tenth resistor and one end of the resistor assembly, and the second power end of the second switching tube is respectively connected with the other end of the seventh resistor and the endurance power supply;
the other end of the resistor assembly is connected with one end of the capacitor assembly and the negative electrode input end of the second comparator respectively;
the other end of the capacitor assembly, the other end of the ninth resistor and the other end of the tenth resistor are respectively grounded.
In one possible implementation, the delay circuit further comprises a diode, wherein,
the anode of the diode is connected with the other end of the resistor assembly, and the cathode of the diode is connected with one end of the resistor assembly.
In one possible implementation, the resistor component includes one resistor, or at least two resistors connected in parallel; and/or
The capacitor assembly comprises one capacitor or at least two capacitors connected in parallel.
In a possible implementation manner, the shutdown determination circuit includes a third switching tube, a first capacitor, and a second capacitor, where:
the control end of the third switching tube is connected with the controlled device, and a third level signal used for representing the starting state of the controlled device is input, the first power end of the third switching tube is respectively connected with one end of the second capacitor and the shutdown signal integration circuit, and the second power end of the third switching tube is respectively connected with one end of the first capacitor and the internal power supply end;
the other end of the first capacitor and the other end of the second capacitor are respectively grounded.
In one possible implementation manner, the signal integration circuit includes an and circuit, a switch circuit, an eleventh resistor, a twelfth resistor, and a thirteenth resistor, where:
one end of the eleventh resistor is connected with the internal power supply end, and the other end of the eleventh resistor is respectively connected with one end of the thirteenth resistor and the output end of the second comparator;
one end of the twelfth resistor is connected with the output end of the first comparator, and the other end of the twelfth resistor is connected with the first input end of the AND circuit;
the second input end of the AND-gate circuit is connected with the other end of the thirteenth resistor, the output end of the AND-gate circuit is connected with the input end of the switch circuit, the power supply end of the AND-gate circuit is connected with the first power end of the third switch tube, and the grounding end of the AND-gate circuit is connected with the ground;
and the output end of the switching circuit outputs the control signal.
In a possible implementation manner, the switching circuit includes a fourth switching tube, a fifth switching tube, a sixth switching tube, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, and a nineteenth resistor, where:
one end of the fourteenth resistor is connected with the output end of the AND circuit;
a control end of the fourth switching tube is connected with the other end of the fourteenth resistor and one end of the fifteenth resistor respectively, a first power end of the fourth switching tube is connected with the other end of the fifteenth resistor and the ground respectively, and a second power end of the fourth switching tube is connected with one end of the sixteenth resistor and one end of the seventeenth resistor respectively;
the other end of the sixteenth resistor is connected with the internal power supply end;
a control end of the fifth switching tube is connected with the other end of the seventeenth resistor and one end of the eighteenth resistor respectively, a first power end of the fifth switching tube is connected with one end of the nineteenth resistor and the control end of the sixth switching tube respectively, and a second power end of the fifth switching tube is grounded;
the other end of the eighteenth resistor and the other end of the nineteenth resistor are connected with the internal power supply end;
the first power end of the sixth switching tube outputs the control signal, and the second power end of the sixth switching tube is grounded.
In a second aspect, an embodiment of the present invention further provides a control device, including any one of the control circuits described in the first aspect.
In the embodiment of the invention, the comparison circuit generates a first level signal representing external power failure and a second level signal representing the duration of the continuous output port control signal of the signal integration circuit, the shutdown judgment circuit generates a fourth level signal triggering the signal integration circuit to work, and the signal integration circuit generates a control signal for controlling shutdown of the controlled equipment according to the first level signal, the second level signal and the fourth level signal.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
Fig. 1 is a schematic structural diagram of a control circuit according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a comparison circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of another comparison circuit according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a delay circuit according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a shutdown determination circuit according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a signal integration circuit according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of another signal integration circuit according to an embodiment of the present invention;
fig. 8 is a flowchart illustrating a control method according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the present invention will be described in further detail with reference to the accompanying drawings, and it is apparent that the described embodiments are only a part of the embodiments of the present invention, not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
At present, all OPS computers in the used interactive all-in-one machines are powered by the interactive all-in-one machines, if the interactive all-in-one machines are powered off abnormally, the OPS computers can be powered off illegally, and the performance of the OPS computers can be influenced by long-term illegal power off.
Based on the above problem, an embodiment of the present invention provides a control circuit, which is applied to an electronic device, as shown in fig. 1, and includes a comparing circuit 10, a delay circuit 20, a shutdown judging circuit 30, and a signal integrating circuit 40, where:
the comparison circuit 10 is connected to the delay circuit 20 and the signal integration circuit 40, and configured to generate a first level signal for representing external power failure according to the input voltage value of the external power supply terminal and the input voltage value of the internal power supply terminal, generate a second level signal for representing a duration of the signal integration circuit 40 continuously outputting the control signal according to the voltage value of the output voltage output by the delay circuit 20 and the voltage value of the internal power supply terminal, input the first level signal to the delay protection circuit 20 and the signal integration circuit 40, and input the second level signal to the signal integration circuit 40;
the delay circuit 20 is configured to generate an output voltage according to the first level signal and a voltage value of a cruising power supply, where the cruising power supply is a power supply that supplies power to the controlled device after external power failure;
the shutdown judging circuit 30 is connected with the controlled device and the integrating circuit, and is used for generating a fourth level signal for triggering the working of the signal integrating circuit 40 according to an input third level signal for representing the startup state of the controlled device;
and the signal integration circuit 40 is connected with the controlled device, and is used for generating a control signal for controlling the controlled device to shut down according to the fourth level signal, the first level signal and the second level signal, and outputting the control signal to the controlled device.
In the embodiment of the invention, the comparison circuit generates a first level signal representing external power failure and a second level signal representing the duration of the continuous output port control signal of the signal integration circuit, the shutdown judgment circuit generates a fourth level signal triggering the signal integration circuit to work, and the signal integration circuit generates a control signal for controlling shutdown of the controlled equipment according to the first level signal, the second level signal and the fourth level signal.
The controlled device in the embodiment of the invention can be an OPS computer in an interactive all-in-one machine, and can also be other devices which can be controlled to be shut down by a control signal.
In the embodiment of the present invention, the voltage of the internal power supply terminal is 3.3V, the voltage of the external power supply terminal is 19V, and the voltage of the cruising power supply is 16V.
In an implementation, as shown in fig. 2, the comparison circuit 10 may include a first comparator 101, a second comparator 102, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4, wherein:
one end of the first resistor R1 is connected with an external power supply end, and the other end of the first resistor R1 is respectively connected with one end of the second resistor R2 and the negative phase input end of the first comparator 101;
the other end of the second resistor R2 is grounded;
one end of the third resistor R3 is connected to the internal power supply terminal, and the other end of the third resistor R3 is connected to the positive input terminal of the first comparator 101 and the positive input terminal of the second comparator 102, respectively;
a power supply end of the first comparator 101 is connected with an internal power supply end, and an output end of the first comparator 101 outputs a first level signal;
the power supply terminal of the second comparator 102 is connected to the internal power supply terminal, the negative input terminal of the second comparator 102 is connected to the output terminal of the delay circuit 20, the output voltage is input, and the output terminal of the second comparator 102 outputs the second level signal.
The voltage at the internal power supply end is divided by the resistors R3 and R4, the obtained divided voltage is input to the positive input end of the first comparator 101, the voltage at the external power supply end is divided by the resistors R1 and R2 and then input to the negative input end of the first comparator 101, that is, the divided voltage value at the external power supply end is compared with the divided voltage value at the internal power supply end, the divided voltage value at the internal power supply end is used as a reference voltage value, if a low-level signal is output, the external power supply is determined to be powered down, and if a high-level signal is output, the external power supply is determined to be powered normally.
In the embodiment of the present invention, as shown in fig. 3, the comparison circuit 10 may include a zener diode ZD, an anode of the zener diode ZD is grounded, a cathode of the zener diode ZD is connected to the internal power supply terminal, and a common terminal of the zener diode ZD is connected to the other end of the first resistor R1 and the cathode input terminal of the first comparator 101, respectively.
And the voltage stabilizing diode ZD is used for stabilizing the voltage division ratio of the external power supply voltage of the external power supply end.
In the embodiment of the present invention, a first level signal, i.e., a low level signal, is input to the delay circuit 20, and the delay circuit outputs an output voltage.
In an implementation, as shown in fig. 4, the delay circuit may include a first switch Q1, a second switch Q2, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a resistor component 201, and a capacitor component 202, where:
one end of the fifth resistor R5 is connected with the output end of the first comparator 101 and one end of the sixth resistor R6 respectively, and the other end of the fifth resistor R5 is connected with the internal power supply end;
a control end of the first switching tube Q1 is connected with the other end of the sixth resistor R6 and one end of the ninth resistor R9 respectively, a first power end of the first switching tube Q1 is connected with one end of the eighth resistor R8, and a second power end of the first switching tube Q1 is grounded;
a control end of the second switching tube Q2 is connected with the other end of the eighth resistor R8 and one end of the seventh resistor R7 respectively, a first power end of the second switching tube Q2 is connected with one end of the tenth resistor R10 and one end of the resistor component 201 respectively, and a second power end of the second switching tube Q2 is connected with the other end of the seventh resistor R7 and the cruising power supply respectively;
the other end of the resistor component 201 is respectively connected with one end of the capacitor component 202 and the negative input end of the second comparator 102;
the other end of the capacitor element 202, the other end of the ninth resistor R9 and the other end of the tenth resistor R10 are grounded, respectively.
In a specific implementation, the delay circuit may further include a diode D1, as shown in fig. 4, an anode of the diode D1 is connected to the other end of the resistor element 201, and a cathode of the diode D1 is connected to one end of the resistor element 201.
The diode D1 is used to prevent the output voltage from flowing backward to the second switch tube Q2.
The resistor component 201 and the capacitor component 202 form an RC (resistor-capacitor) charging circuit, and the charging duration can be determined according to the connection mode of the resistors in the resistor component 201, the number of the resistors, the resistance value of the resistors, the connection mode of the capacitors in the capacitor component 202, the number of the capacitors, and the capacitance value of the capacitors.
Specifically, the resistor assembly 201 may include one resistor, or may include at least two resistors connected in parallel, or of course, may also include at least two resistors connected in parallel and in series; the capacitor assembly 202 may include one capacitor, at least two capacitors connected in parallel, and at least two capacitors connected in parallel and in series.
As shown in fig. 4, the resistance assembly 201 includes two resistors, R20 and R21, connected in parallel; the capacitor assembly 202 includes 4 capacitors, C3, C4, C5, and C6, connected in parallel.
In the embodiment of the present disclosure, the input end of the delay circuit 20 is a first level signal, that is, a low level, the voltage of the internal power supply end is 3.3V, the first switch tube Q1 is turned off, the voltage of the endurance power supply is 16V, the second switch tube Q2 is turned off, the capacitor in the capacitor module 202 starts to be charged, the output voltage of the output end of the delay circuit 20 increases, and after a period of time T, the charging of the capacitor in the capacitor module 202 is finished, and the output voltage reaches a maximum value.
The delay circuit 20 inputs the output voltage to the negative phase input end of the second comparator, the positive input end of the second comparator inputs the divided internal power supply voltage, before and during the charging of the charging circuit in the delay circuit 20, the output voltage is lower than the divided internal power supply voltage, the second comparator outputs a high level, and after the charging of the charging circuit is completed, the output voltage is higher than the divided internal power supply voltage, the second comparator outputs a low level, so that the duration time of the high level is the charging time T of the charging circuit.
The first level signal and the second level signal output from the comparator circuit are explained above, and the fourth level signal is explained below.
As shown in fig. 5, the shutdown determination circuit 30 in the embodiment of the present invention includes a third switching tube Q3, a first capacitor C1, and a second capacitor C2, where:
the control end of the third switching tube Q3 is connected with the controlled device, and inputs a third level signal for representing the power-on state of the controlled device, the first power end of the third switching tube Q3 is connected with one end of the second capacitor C2 and the shutdown signal integration circuit 40, and the second power end of the third switching tube Q3 is connected with one end of the first capacitor C1 and the internal power supply end;
the other end of the first capacitor C1 and the other end of the second capacitor C2 are respectively grounded.
In the embodiment of the invention, when the controlled equipment is in a power-off state, the high level is output, and when the controlled equipment is in a power-on state, the low level is output. The third level signal is used for representing the power-on state of the controlled device, so that the third level signal is at a low level.
As can be seen from fig. 5, the third level signal is low, the voltage of the internal power supply terminal is 3.3V, the third switching tube Q3 is turned on, and the fourth level signal is high.
The signal integration circuit 40 in the embodiment of the present disclosure is explained below.
As shown in fig. 6, the signal integration circuit 40 in the embodiment of the present disclosure may include an and circuit 401, a switch circuit 402, an eleventh resistor R11, a twelfth resistor R12, and a thirteenth resistor R13, wherein:
one end of an eleventh resistor R11 is connected with the internal power supply end, and the other end of the eleventh resistor R11 is respectively connected with one end of a thirteenth resistor R13 and the output end of the second comparator 102;
one end of the twelfth resistor R12 is connected to the output end of the first comparator 101, and the other end of the twelfth resistor R12 is connected to the first input end of the and circuit 401;
a second input end of the and circuit 401 is connected with the other end of the thirteenth resistor R13, an output end of the and circuit 401 is connected with an input end of the switch circuit 402, a power supply end of the and circuit 401 is connected with a first power end of the third switch tube Q3, and a ground end of the and circuit 401 is connected with ground;
the output terminal of the switching circuit 402 outputs a control signal.
As shown in fig. 7, the switching circuit 402 in the embodiment of the present disclosure may include a fourth switching tube Q4, a fifth switching tube Q5, a sixth switching tube Q6, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, and a nineteenth resistor R19, wherein:
one end of the fourteenth resistor R14 is connected with the output end of the AND gate circuit 401;
a control end of a fourth switching tube Q4 is respectively connected with the other end of the fourteenth resistor R14 and one end of the fifteenth resistor R15, a first power end of the fourth switching tube Q4 is respectively connected with the other end of the fifteenth resistor R15 and ground, and a second power end of the fourth switching tube Q4 is respectively connected with one end of the sixteenth resistor R16 and one end of the seventeenth resistor R17;
the other end of the sixteenth resistor R16 is connected with an internal power supply end;
a control end of the fifth switching tube Q5 is connected to the other end of the seventeenth resistor R17 and one end of the eighteenth resistor R18, respectively, a first power end of the fifth switching tube Q5 is connected to one end of the nineteenth resistor R19 and a control end of the sixth switching tube Q6, respectively, and a second power end of the fifth switching tube Q5 is grounded;
the other end of the eighteenth resistor R18 and the other end of the nineteenth resistor R19 are connected with the internal power supply end;
a first power terminal of the sixth switching tube Q6 outputs a control signal, and a second power terminal of the sixth switching tube Q6 is grounded.
As can be seen from the above embodiments, the first level signal is a low level signal, the second level signal is a high level signal, the duration of the second level signal is the charging duration T of the RC charging circuit, and the fourth level signal is a high level signal.
The fourth level signal is high level, the logic gate circuit 401 works normally, the logic gate circuit 401 outputs low level, Q4 is closed, Q5 is opened, Q6 is closed, the control signal output by the signal integration circuit 40 is low level, the duration of the control signal is T, and the controlled device is controlled to be turned off.
Based on any one of the control circuits, an embodiment of the present invention further provides a method for controlling a shutdown of a device, where the control device includes a endurance power supply, for example, a storage battery, for automatically supplying power to the device with the storage battery after the external power supply is interrupted.
The device in the embodiment of the invention is described by taking an OPS computer in an interactive all-in-one machine as an example.
The following describes a flow of a method for controlling the turn-off of the OPS computer of the all-in-one interactive machine. As shown in fig. 8, the method comprises the following steps:
s801, electrifying the interactive all-in-one machine, charging a cruising power supply, supplying power to a Central Processing Unit (CPU) and supplying power to an OPS computer;
s802, the CPU sends an OPS computer starting instruction to the control circuit;
here, the OPS in the OPS computer may send an OPS boot instruction to the control circuit.
S803, the control circuit controls the OPS computer to start up;
s804, the OPS computer outputs a low level signal to the control circuit;
here, a low level on the OPS output indicates that the OPS computer is powered on.
S805, the control circuit compares the voltage value of the external power supply end with the voltage value of the internal power supply end and outputs a low-level signal;
s806, the control circuit determines that the external power supply is abnormally powered off;
s807a, supplying power to the OPS computer by the endurance power supply;
s807b, the control circuit determines that the OPS computer outputs a low level signal;
and if the control circuit determines that the OPS computer outputs high level, determining that the OPS computer is in a shutdown state, and ending the operation.
S808, the control circuit determines that the OPS computer is in a starting state;
s809, the control circuit sends a low level signal for controlling the OPS computer to shut down to the OPS computer;
s810, starting the power-off of the OPS computer;
s811, the control circuit determines that the level signal output to the control circuit by the OPS computer is a high level signal;
and S812, the control circuit controls the endurance power supply to be disconnected to supply power to the OPS computer.
Further, based on the same inventive concept, an embodiment of the present invention further provides a control device, which includes any one of the control circuits described above.
The implementation of the control device may refer to the implementation of the embodiment of the control circuit, which is not described herein again.
The present application is described above with reference to block diagrams and/or flowchart illustrations of methods, apparatus (systems) and/or computer program products according to embodiments of the application. It will be understood that one block of the block diagrams and/or flowchart illustrations, and combinations of blocks in the block diagrams and/or flowchart illustrations, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, and/or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer and/or other programmable data processing apparatus, create means for implementing the functions/acts specified in the block diagrams and/or flowchart block or blocks.
Accordingly, the present application may also be embodied in hardware and/or in software (including firmware, resident software, micro-code, etc.). Furthermore, the present application may take the form of a computer program product on a computer-usable or computer-readable storage medium having computer-usable or computer-readable program code embodied in the medium for use by or in connection with an instruction execution system. In the context of this application, a computer-usable or computer-readable medium may be any medium that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. A control circuit, comprising: the power-off detection circuit comprises a comparison circuit, a delay circuit, a power-off judgment circuit and a signal integration circuit; wherein the content of the first and second substances,
the comparison circuit is used for generating a first level signal for representing external power failure according to the input voltage value of the external power supply end and the input voltage value of the internal power supply end, generating a second level signal for representing the duration of the continuous output control signal of the signal integration circuit according to the voltage value of the output voltage output by the delay circuit and the voltage value of the internal power supply end, inputting the first level signal to the delay circuit and the signal integration circuit respectively, and inputting the second level signal to the signal integration circuit;
the delay circuit is used for generating the output voltage according to the first level signal and a voltage value of a endurance power supply, wherein the endurance power supply is a power supply for supplying power to controlled equipment after external power failure;
the shutdown judgment circuit is used for generating a fourth level signal for triggering the signal integration circuit to work according to an input third level signal for representing the standby state of the controlled equipment;
the signal integration circuit is configured to generate the control signal for controlling the controlled device to shut down according to the fourth level signal, the first level signal, and the second level signal, and output the control signal to the controlled device.
2. The circuit of claim 1, wherein the comparison circuit comprises a first comparator, a second comparator, a first resistor, a second resistor, a third resistor, and a fourth resistor, wherein:
one end of the first resistor is connected with the external power supply end, and the other end of the first resistor is respectively connected with one end of the second resistor and the negative input end of the first comparator;
the other end of the second resistor is grounded;
one end of the third resistor is connected with the internal power supply end, and the other end of the third resistor is respectively connected with the positive input end of the first comparator, the positive input end of the second comparator and one end of the fourth resistor;
the other end of the fourth resistor is grounded;
a power supply end of the first comparator is connected with the internal power supply end, and an output end of the first comparator outputs the first level signal;
and a power supply end of the second comparator is connected with the internal power supply end, a negative input end of the second comparator is connected with an output end of the delay circuit, the output voltage is input, and an output end of the second comparator outputs the second level signal.
3. The circuit of claim 2, wherein the comparison circuit further comprises a zener diode, an anode of the zener diode is grounded, a cathode of the zener diode is connected to the internal power supply terminal, and a common terminal of the zener diode is connected to the other terminal of the first resistor and the cathode input terminal of the first comparator, respectively.
4. The circuit of claim 2, wherein the delay circuit comprises a first switch tube, a second switch tube, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a resistor component, and a capacitor component, wherein:
one end of the fifth resistor is connected with the output end of the first comparator and one end of the sixth resistor respectively, and the other end of the fifth resistor is connected with the internal power supply end;
the control end of the first switch tube is respectively connected with the other end of the sixth resistor and one end of the ninth resistor, the first power end of the first switch tube is connected with one end of the eighth resistor, and the second power end of the first switch tube is grounded;
the control end of the second switching tube is respectively connected with the other end of the eighth resistor and one end of the seventh resistor, the first power end of the second switching tube is respectively connected with one end of the tenth resistor and one end of the resistor assembly, and the second power end of the second switching tube is respectively connected with the other end of the seventh resistor and the endurance power supply;
the other end of the resistor assembly is respectively connected with one end of the capacitor assembly and the negative electrode input end of the second comparator;
the other end of the capacitor assembly, the other end of the ninth resistor and the other end of the tenth resistor are respectively grounded.
5. The circuit of claim 4, wherein the delay circuit further comprises a diode, wherein,
the anode of the diode is connected with the other end of the resistor assembly, and the cathode of the diode is connected with one end of the resistor assembly.
6. The circuit of claim 4, wherein the resistive component comprises one resistor, or at least two resistors connected in parallel; and/or
The capacitor assembly comprises one capacitor or at least two capacitors connected in parallel.
7. The circuit of claim 1, wherein the shutdown determination circuit comprises a third switch tube, a first capacitor, and a second capacitor, wherein:
the control end of the third switching tube is connected with the controlled device, and a third level signal used for representing the starting state of the controlled device is input, the first power end of the third switching tube is respectively connected with one end of the second capacitor and the shutdown signal integration circuit, and the second power end of the third switching tube is respectively connected with one end of the first capacitor and the internal power supply end;
the other end of the first capacitor and the other end of the second capacitor are respectively grounded.
8. The circuit of claim 7, wherein the signal integration circuit comprises an and circuit, a switching circuit, an eleventh resistor, a twelfth resistor, and a thirteenth resistor, wherein:
one end of the eleventh resistor is connected with the internal power supply end, and the other end of the eleventh resistor is respectively connected with one end of the thirteenth resistor and the output end of the second comparator;
one end of the twelfth resistor is connected with the output end of the first comparator, and the other end of the twelfth resistor is connected with the first input end of the AND circuit;
the second input end of the AND-gate circuit is connected with the other end of the thirteenth resistor, the output end of the AND-gate circuit is connected with the input end of the switch circuit, the power supply end of the AND-gate circuit is connected with the first power end of the third switch tube, and the grounding end of the AND-gate circuit is connected with the ground;
the output end of the switch circuit outputs the control signal.
9. The circuit of claim 8, wherein the switching circuit comprises a fourth switching tube, a fifth switching tube, a sixth switching tube, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, and a nineteenth resistor, wherein:
one end of the fourteenth resistor is connected with the output end of the AND circuit;
a control end of the fourth switching tube is connected with the other end of the fourteenth resistor and one end of the fifteenth resistor respectively, a first power end of the fourth switching tube is connected with the other end of the fifteenth resistor and the ground respectively, and a second power end of the fourth switching tube is connected with one end of the sixteenth resistor and one end of the seventeenth resistor respectively;
the other end of the sixteenth resistor is connected with the internal power supply end;
a control end of the fifth switching tube is connected to the other end of the seventeenth resistor and one end of the eighteenth resistor, respectively, a first power end of the fifth switching tube is connected to one end of the nineteenth resistor and the control end of the sixth switching tube, respectively, and a second power end of the fifth switching tube is grounded;
the other end of the eighteenth resistor and the other end of the nineteenth resistor are connected with the internal power supply end;
the first power end of the sixth switching tube outputs the control signal, and the second power end of the sixth switching tube is grounded.
10. A control device comprising a control circuit as claimed in any one of claims 1 to 9.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110095312.5A CN112860044B (en) | 2021-01-25 | 2021-01-25 | Control circuit and control device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110095312.5A CN112860044B (en) | 2021-01-25 | 2021-01-25 | Control circuit and control device |
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| CN112860044A CN112860044A (en) | 2021-05-28 |
| CN112860044B true CN112860044B (en) | 2022-06-17 |
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| CN114583813A (en) * | 2022-03-15 | 2022-06-03 | 重庆海尔滚筒洗衣机有限公司 | Power supply circuit |
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| CN100562835C (en) * | 2006-01-05 | 2009-11-25 | 英业达股份有限公司 | Guard method of condition of instant error power-off of computer platform internal circuit and system |
| CN102213993B (en) * | 2010-04-01 | 2015-06-17 | 康佳集团股份有限公司 | Circuit for soft startup and soft shutdown |
| CN102541238A (en) * | 2011-12-31 | 2012-07-04 | 数源科技股份有限公司 | Outage protector used for embedded computer and realization method thereof |
| CN205375055U (en) * | 2016-01-18 | 2016-07-06 | 深圳唯创知音电子有限公司 | Power -off protection ware and socket |
| CN205753636U (en) * | 2016-07-15 | 2016-11-30 | 中国神华能源股份有限公司 | A kind of power-down protection circuit |
| CN207301964U (en) * | 2017-08-29 | 2018-05-01 | 浙江大华技术股份有限公司 | A kind of automatic boot circuit and electronic equipment |
| CN108304059B (en) * | 2018-02-26 | 2020-02-07 | 北京环境特性研究所 | Automatic shutdown system and method for abnormal power failure of computer |
| CN208752571U (en) * | 2018-09-18 | 2019-04-16 | 深圳荣品电子科技有限公司 | A kind of on/off circuit with forced shutdown function |
| CN210573655U (en) * | 2019-10-23 | 2020-05-19 | 山东金钟科技集团股份有限公司 | Time-delay power-off protection circuit |
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