CN112838857B - Soft error reinforcement method applied to combinational logic circuit - Google Patents

Soft error reinforcement method applied to combinational logic circuit Download PDF

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CN112838857B
CN112838857B CN202110106552.0A CN202110106552A CN112838857B CN 112838857 B CN112838857 B CN 112838857B CN 202110106552 A CN202110106552 A CN 202110106552A CN 112838857 B CN112838857 B CN 112838857B
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程旭
谭驰誉
韩军
曾晓洋
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Fudan University
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    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

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Abstract

The invention belongs to the technical field of semiconductors and integrated circuits, and particularly relates to a soft error reinforcement method applied to a combinational logic circuit. The invention comprises 4 processes: reading, marking, grouping and reinforcing; extracting the connection relation between the constituent elements and the elements of the circuit in the reading process; in the marking process, the logic gates to be reinforced are classified and marked, and the number and the positions of the logic gates to be reinforced can be selected arbitrarily according to design requirements; in the grouping process, a specific grouping scheme is obtained by solving all maximum connected subgraphs of a directed graph formed by logic gates to be reinforced; and in the reinforcing process, grouping triple modular redundancy reinforcement is carried out on the original circuit and the reinforced circuit is output. The invention has the advantages that: on one hand, the combined circuit is reinforced based on the triple modular redundancy, and higher reliability guarantee can be provided; on the other hand, a flexible and efficient reinforcement scheme can be provided, and compared with the traditional triple-modular redundancy reinforcement scheme, the reinforcement scheme can adapt to more diversified circuit design requirements.

Description

Soft error reinforcement method applied to combinational logic circuit
Technical Field
The invention belongs to the technical field of semiconductors and integrated circuits, and particularly relates to a soft error reinforcement method applied to a combinational logic circuit in an integrated circuit.
Background
As semiconductor feature sizes continue to shrink, integrated circuits become increasingly sensitive to soft errors caused by radiation particle attacks. When a radiation particle attack occurs in a combinational logic circuit, an erroneous transient signal is generated at the attacked circuit node. The error signal propagates along the logic path and is captured by the memory cell, and finally enters a system key module, which may cause the whole system to generate a functional error. Such non-permanent errors are referred to as soft errors. For electronic devices that are at risk of radiation attack and for electronic systems that have high reliability requirements, such as electronic devices in spacecraft, aircraft and nuclear installations, reinforcement design for soft errors is important.
The triple modular redundancy reinforcing method is a reinforcing method that a circuit to be reinforced is copied into three parts and then a voter is connected to an output end. The method can ensure that the final output is free from errors when any copy module has errors by utilizing the majority voting function of the voter. The traditional method for reinforcing the triple modular redundancy of the whole circuit has high reliability but huge area cost. In different designs, the area margin for the consolidation of the combinational circuit is limited and uncertain, and therefore, a trade-off needs to be made between the two indexes of reliability and area. Therefore, it is very important to design a flexible and efficient method for reinforcing a combinational circuit, which can satisfy any design margin.
Disclosure of Invention
The invention aims to provide a flexible and efficient soft error reinforcement method applied to a combinational logic circuit so as to adapt to various design margin conditions.
The soft error reinforcement method applied to the combinational logic circuit provided by the invention comprises the following 4 processes: the method comprises the steps of (A) a circuit reading process, (B) a logic gate marking process to be reinforced, (III) a logic gate grouping process to be reinforced and (IV) a reinforcement process; the circuit reading process extracts the connection relation between the constituent elements and the elements of the circuit and constructs a graph theory data structure; in the marking process of the logic gates to be reinforced, the logic gates are classified and marked by reading the selection information of the logic gates to be reinforced, and the number and the positions of the logic gates to be reinforced can be arbitrarily selected according to design requirements; in the grouping process of the logic gates to be reinforced, a specific grouping scheme is obtained by solving the maximum connected subgraph of the directed graph formed by the logic gates to be reinforced; and the reinforcement process carries out grouping triple modular redundancy reinforcement on the original circuit according to the grouping scheme.
The circuit reading process specifically comprises the following steps:
(1) and reading the combination circuit, and regarding the whole circuit as a directed graph G ═ V, E >. The vertex V in the directed graph comprises all input ends, output ends and logic gates in the circuit, and the directed edge E of the directed graph G comprises all connecting lines in the circuit;
(2) the number of input terminals of the circuit is recorded as NINumbering all the input ends according to the reading sequence, and marking the serial number of the ith input end as INi，i＝1，2，…，NI. The vertex set formed by all the input ends is recorded as VI，
Figure BDA0002917830680000021
Recording the number of output terminals of the circuitIs NONumbering all the output ends according to the reading sequence, and recording the serial number of the jth output end as OTi，j＝1，2，…，NO. Record the vertex set composed of all the output ends as VO，
Figure BDA0002917830680000022
Let the number of logic gates of the circuit be NGNumbering all logic gates according to reading sequence, and recording the serial number of the kth output end as GAi，k＝1，2，…，NG. Let the set of vertices formed by all logic gates be VG，
Figure BDA0002917830680000023
Therefore, the set of vertices V of the directed graph G is VI+VO+VG；
(3) Denote the directed edge from vertex u to vertex v as<u,v>. According to the connection relation of each element of the circuit, an edge set E of the directed graph G can be obtained as
Figure BDA0002917830680000024
Wherein V ∈ VI+VG，u∈VG+VO，
Figure BDA0002917830680000025
Representing the successor set of the vertex v in the directed graph G;
(4) the circuit reading process ends. The circuit process extracts key node and connection information in the circuit to facilitate analysis and execution of subsequent circuit grouping and consolidation processes.
The marking process of the logic gate to be reinforced of the circuit specifically comprises the following steps:
(1) and reading the selection information. The selection information is external data, comprises two kinds of information of the number of doors to be reinforced and the position in the circuit, and can be flexibly set according to specific design requirements;
(2) the number of doors to be reinforced is recorded as NH. From the set of vertices V according to the selection informationGSelecting corresponding reinforced vertex structureNew set VHReferred to as reinforcement sets. Set the vertex VGThe set of non-reinforced vertices in (1) is denoted as VN＝VG-VHReferred to as the non-consolidated set. Thus, the set of vertices V may be equivalent to VI+VO+VH+VN。
(III) the grouping process of the logic gates to be reinforced of the circuit specifically comprises the following steps:
(1) constructing a length of NHIs denoted as VISIT. VISIT for recording VHThe visited state, the not-visited state, and the visited state are each set to 0 and 1, respectively. Initializing all vertex access states in VISIT to be 0;
(2) according to VHOrder of middle vertices, visit VHMiddle 1 st vertex, denoted as v1And v in VISIT1The access state of (1) is changed. Search VHIn (a) contains v1The maximum connected subgraph of (2) and all the vertexes in the maximum connected subgraph are divided into one group and recorded.
Wherein, search VHIn (a) contains v1The specific search process of the maximum connected subgraph is as follows:
initializing a null LIST, recording as LIST1, and recording the vertex of the maximum connected subgraph; v is to be1Adding into LIST 1;
initializing a null two-dimensional list, and recording the list as OUTL 1; the number of rows of OUTL1 is always consistent with the number of elements in LIST1, and each row in OUTL1 is a separate LIST for recording the successor set of vertices to V in LIST1 corresponding to the sequence numberNOr belong to NOThe vertex of (a); add the first row in OUTL1, the first row element is empty;
thirdly, according to the front-back order of the vertexes in LIST1, the first vertex in LIST1 is visited and marked as u1；
(iv) search for all u in E1Obtaining the final vertex of all the edges meeting the conditions for the edges of the initial vertex; condition of use 1 (of V)HAnd the access state in VISIT is 0) and condition 2 (belonging to V)NOr belong to VO) Screening the vertexes; if the vertexes meeting the condition 1 exist, adding the vertexes meeting the condition 1 to the tail of the LIST1 in sequence, and changing the VISIT state of the vertexes meeting the condition 1 in the VISIT to be 1; recording the number of the top points meeting the condition 1 as x, adding x rows in OUTL1, wherein elements in the newly added rows are null; if there is a vertex that satisfies condition 2, add the vertex that satisfies condition 2 to the first row of OUTL 1;
searching all the terms u in E1Obtaining initial vertexes of all edges meeting the conditions for the edges ending to the vertexes; condition of use 1 (of V)HAnd the VISIT state in VISIT is 0), and if there is a vertex satisfying condition 1, sequentially adding vertices satisfying condition 1 to the end of LIST1, and changing the VISIT state in VISIT of the vertex satisfying condition 1 to 1; recording the number of the top points meeting the condition 1 as x, adding x rows in OUTL1, wherein elements in the newly added rows are null;
sixthly, according to the front-back order of the vertexes in LIST1, if the second vertex exists in LIST1, the second vertex in LIST1 is visited and is marked as u2；
Seventhly, all the groups u in E are searched2Obtaining final vertexes of all edges meeting the conditions for the edges of the initial vertexes; condition of use 1 (of V)HAnd the access state in VISIT is 0) and condition 2 (belonging to V)NOr belong to VO) Screening the vertexes; if the vertexes meeting the condition 1 exist, adding the vertexes meeting the condition 1 to the tail of the LIST1 in sequence, and changing the VISIT state of the vertexes meeting the condition 1 in the VISIT to be 1; recording the number of the top points meeting the condition 1 as x, adding x rows in OUTL1, wherein elements in the newly added rows are null; if there is a vertex that satisfies condition 2, add the vertex that satisfies condition 2 to the second row of OUTL 1;
eighthly search all the groups u in E2Obtaining the initial vertexes of all the edges meeting the conditions for the edges ending to the vertexes; condition of use 1 (of V)HAnd the VISIT state in VISIT is 0) of the vertices, and if there is a vertex satisfying condition 1, the vertices satisfying condition 1 are sequentially added to the end of LIST1, and the vertex satisfying condition 1 is addedThe access state of the point in VISIT is changed to 1; recording the number of the top points meeting the condition 1 as x, adding x rows in OUTL1, wherein elements in the newly added rows are null;
ninthly, so on;
when the last vertex in LIST1 is visited completely and the number of vertices in LIST1 is not increased any more, the search is ended; at this time LIST1 is VHIn (a) contains v1The OUTL1 records the attributes of V existing in the set of successors of all vertices in the maximally connected subgraphNOr belong to VOThe vertex of (2).
(3) According to VHAnd searching the vertex with the next VISIT state of 0 in VISIT. If VHThere is no vertex whose access state in VISIT is 0, and the process proceeds to step (7). If a vertex with access state 0 in VISIT is searched, the vertex is marked as v2V in VISIT2The access state of (1) is changed to 1. Search VHIn (a) contains v2The maximum connected subgraph of (2) is that all the vertexes in the maximum connected subgraph are divided into a group and recorded.
Wherein, search VHIn (a) contains v2The specific search process of the maximum connected subgraph of (1) is as follows:
first, initialize a null LIST, denoted LIST2, for recording the vertices of the maximally connected subgraph. V is to be2Adding into LIST 2;
and secondly, initializing an empty two-dimensional list, namely OUTL 2. The number of rows of OUTL2 is always consistent with the number of elements in LIST2, and each row in OUTL2 is a separate LIST for recording the successor set of vertices to V in LIST2 corresponding to the sequence numberNOr belong to VOThe vertex of (2). Add the first row in OUTL2, the first row element is empty;
thirdly, according to the front-back order of the vertexes in LIST2, the first vertex in LIST2 is visited and marked as u1；
Retrieving all the terms u in E1For the edge of the starting vertex, the final vertex of all the edges satisfying the condition is obtained. Condition of use 1 (belonging to V)HAnd is arranged atAccess status in VISIT is 0) and condition 2 (belonging to V)NOr belong to VO) These vertices are screened. If there is a vertex satisfying condition 1, vertices satisfying condition 1 are sequentially added to the end of LIST2, and the visitation state of vertices satisfying condition 1 in VISIT is changed to 1. The number of vertices satisfying condition 1 is noted as x, line x is added in OUTL2, and the elements in the newly added line are null. If there is a vertex that satisfies condition 2, add the vertex that satisfies condition 2 to the first row of OUTL 2;
searching all the terms u in E1To end the edges of the vertex, the starting vertices of all the edges that satisfy the condition are obtained. Condition of use 1 (of V)HAnd the visitation state in VISIT is 0), and if there is a vertex satisfying condition 1, vertices satisfying condition 1 are sequentially added to the end of LIST2, and the visitation state in VISIT of a vertex satisfying condition 1 is changed to 1. Recording the number of the top points meeting the condition 1 as x, adding x rows in OUTL2, wherein elements in the newly added rows are null;
sixthly, according to the front-back order of the vertexes in LIST1, if the second vertex exists in LIST2, the second vertex in LIST2 is visited and is marked as u2；
Seventhly, search for all u in E2For the edge of the start vertex, the final vertex of all the edges satisfying the condition is obtained. Condition of use 1 (belonging to V)HAnd the access state in VISIT is 0) and condition 2 (belonging to V)NOr belong to VO) These vertices are screened. If there is a vertex satisfying condition 1, vertices satisfying condition 1 are sequentially added to the end of LIST2, and the visitation state of vertices satisfying condition 1 in VISIT is changed to 1. The number of vertices satisfying condition 1 is noted as x, line x is added in OUTL2, and the elements in the newly added line are null. If there is a vertex that satisfies condition 2, add the vertex that satisfies condition 2 to the second row of OUTL 2;
eighthly search all the groups u in E2And obtaining the initial vertex of all the edges meeting the condition for ending the edges of the vertex. Condition of use 1 (of V)HAnd the VISIT state in VISIT is 0) to screen the vertices if there are vertices satisfying condition 1Vertices satisfying condition 1 are sequentially added to the end of LIST2, and the visitation state of vertices satisfying condition 1 in VISIT is changed to 1. Recording the number of the top points meeting the condition 1 as x, adding x rows in OUTL2, wherein elements in the newly added rows are null;
ninthly, so on;
when the last vertex in LIST2 is visited and the number of vertices in LIST2 no longer increases, the search ends. At this time LIST2 is VHIn (a) contains v2Of the maximum connected subgraph, OUTL2 records the attributes of V existing in the successor set of all vertices in the maximum connected subgraphNOr belong to VOThe vertex of (2).
(4) According to VHOrder of middle vertex at VHSearches for the next vertex with access state 0 in VISIT. If there is no vertex whose access state in VISIT is 0 next, it jumps to step (7). If there is a vertex with the next VISIT state of 0 in VISIT, the vertex is marked as v3V in VISIT3The access state of (1) is changed to 1. Search VHIn (a) contains v3The maximum connected subgraph of (2) is that all the vertexes in the maximum connected subgraph are divided into a group and recorded. The specific maximum connected subgraph searching method is the same as above.
(5) And so on.
(6) Finish accessing VHAll the vertices in the VISIT are accessed to be 1 at the moment, and V is obtainedHMarking a list formed by the vertexes in the last maximum connected subgraph as LISTn, and enabling the successor set recorded with the vertexes in the LISTn to belong to VNOr belong to VOThe two-dimensional list of vertices of (d) is denoted as OUTLn.
(7) To this end, VHAll the largest connected subgraphs have been found. VHThe grouping mode of all the vertexes is as follows: LIST1, LIST2, …, LIST.
(8) The grouping process ends. The grouping process is based on a maximum connected subgraph algorithm, and all the reinforcement units can be quickly grouped according to the electrical connection relation.
The reinforcing process specifically comprises the following steps:
(1) regarding the logic gates contained in the LIST1 as a whole, the sub-circuit formed by the whole is reinforced with triple modular redundancy, and voting units are added according to the OUTL 1.
The specific process of the redundancy reinforcement is as follows:
marking a SET formed by all logic gates in the LIST1 as GSET1, a SET formed by connecting lines among the logic gates in the GSET1 as W1SET1, and a SET formed by connecting lines among the logic gates in the GSET1 and the circuit input end or the output end of the non-reinforced logic gate as W2SET 1; copying all elements in GSET1, W1SET1 and W2SET1 into two parts as a whole, adding the two parts into an original circuit, and distinguishing the names of all copied bodies (copied logic gates and connecting lines) from the names of copied bodies (copied logic gates and connecting lines);
access the 1 st element non-empty row in the order of rows in OUTL 1; marking serial numbers of logic gates in circuits corresponding to the row as GIN11, and marking serial numbers of two copies obtained after the GIN11 is copied in the step I as GIN11 'and GIN 11'; the number of elements in the row is noted as y11The serial numbers of logic gates or output ends in the circuit corresponding to all elements in the row are recorded as
Figure BDA0002917830680000051
Adding a voting unit in the original circuit, and marking the voting unit as VOT 11; will be provided with
Figure BDA0002917830680000052
Deleting the connection with the GIN11 in the original circuit; three inputs of the VOT11 are connected to the outputs of GIN11, GIN11 'and GIN11 ", respectively, and an output of the VOT11 is connected to the output of GIN11, GIN 11' and GIN11 ″
Figure BDA0002917830680000053
The input end of the connecting line is just deleted;
③ access the 2 nd element non-empty row in the order of the rows in OUTL 1; marking the serial number of a logic gate in a circuit corresponding to the row as GIN12, and copying the sequence of two copy bodies obtained by GIN12 through the step INumbers GIN12 'and GIN 12'; the number of elements in the row is noted as y12The serial numbers of logic gates or output ends in the circuit corresponding to all elements in the row are recorded as
Figure BDA0002917830680000061
Adding a voting unit in the original circuit, and marking the voting unit as VOT 12; will be provided with
Figure BDA0002917830680000062
Deleting the connection with the GIN12 in the original circuit; three inputs of VOT12 are connected to the outputs of GIN12, GIN12 'and GIN 12' respectively, and an output of VOT12 is connected to
Figure BDA0002917830680000063
The input end of the connecting line is just deleted;
fourthly, by analogy, accessing the No. 3 to NV in OUTL11Non-empty line of elements, add No. 3 to NV1Voting units and modifying the connections in the circuit.
(2) Regarding the logic gates contained in the LIST2 as a whole, performing triple modular redundancy on a sub-circuit formed by the whole, and adding a voting unit according to OUTL 2;
the specific process of the redundancy reinforcement is as follows:
recording a SET formed by all logic gates in the LIST2 as GSET2, a SET formed by connecting lines among the logic gates in the GSET2 as W1SET2, and a SET formed by connecting the logic gates in the GSET2 with connecting lines among circuit input ends or non-reinforced logic gate output ends as W2SET 2; all elements in GSET2, W1SET2 and W2SET2 are copied into two copies as a whole and added into an original circuit, and the names of all copies (copied logic gates and connecting lines) are distinguished from the name of a copied object (copied logic gates and connecting lines);
second, access the 1 st element non-empty row in the order of the rows in OUTL 2; marking serial numbers of logic gates in circuits corresponding to the row as GIN21, and marking serial numbers of two copies obtained after the GIN21 is copied in the step I as GIN21 'and GIN 21'; the number of elements in the row is noted as y21All elements in the row are sortedThe serial number of the logic gate or the output end in the corresponding circuit is recorded as
Figure BDA0002917830680000064
Adding a voting unit in the original circuit, and marking as VOT 21; will be provided with
Figure BDA0002917830680000065
Deleting the connection with the GIN21 in the original circuit; three inputs of the VOT21 are connected to the outputs of GIN21, GIN21 'and GIN21 ", respectively, and an output of the VOT21 is connected to the output of GIN21, GIN 21' and GIN21 ″
Figure BDA0002917830680000066
The input end of the connecting line is just deleted;
③ access the 2 nd element non-empty row in the order of the rows in OUTL 2; marking serial numbers of logic gates in circuits corresponding to the row as GIN22, and marking serial numbers of two copies obtained after the GIN22 is copied in the step I as GIN22 'and GIN 22'; denote the number of elements in the row as y22The serial numbers of logic gates or output ends in the circuit corresponding to all elements in the row are recorded as
Figure BDA0002917830680000067
Adding a voting unit in the original circuit, and marking the voting unit as VOT 22; will be provided with
Figure BDA0002917830680000068
Deleting the connection with the GIN22 in the original circuit; three inputs of the VOT22 are connected to the outputs of GIN22, GIN22 'and GIN22 ", respectively, and an output of the VOT22 is connected to the output of GIN22, GIN 22' and GIN22 ″
Figure BDA0002917830680000069
The input end of the connecting line is just deleted;
fourthly, by analogy, accessing the No. 3 to NV in OUTL22Non-empty rows of elements, add 3 rd to NV2Voting units and modifying the connections in the circuit.
(3) In the same way, the logic gates contained in LIST 3-LISTn are respectively regarded as n-2 integers, and the sub-circuits formed by the n-2 integers are subjected to three-mode operationRedundancy, adding voting units according to OUTL 3-OUTN, and NV3，NV4，…，NVnAnd a voting unit. The specific redundant reinforcement process is the same as above. After the reinforcement of the LISTn is completed, VHAll logic cells in the stack have been consolidated and cumulatively added
Figure BDA0002917830680000071
And a voting unit.
(4) And (5) finishing the reinforcing process and outputting the reinforced circuit. In the reinforcing process, only the voting unit is added at the output end of each grouping sub-circuit, the structure of the circuit is fully utilized, and the extra area overhead brought by the voting unit is reduced to the maximum extent.
Compared with the prior art of combining circuit reinforcement, the invention has two advantages. On one hand, the invention reinforces the combined circuit based on the triple modular redundancy and can provide very high reliability guarantee; on the other hand, the invention can provide a flexible and efficient reinforcement scheme, and can adapt to more diversified circuit design requirements compared with the traditional triple-modular redundancy reinforcement scheme.
Drawings
FIG. 1 is a flow chart of the consolidation method of the present invention.
Fig. 2 is an example of a combined circuit.
FIG. 3 is an example of a voting unit structure and truth table for use with the present invention.
Fig. 4 is an example of an intermediate circuit produced by the present invention after the target circuit of fig. 2 has been hardened.
Fig. 5 is an example of a final reinforcing circuit output after the target circuit of fig. 2 is subjected to the reinforcement of the present invention.
Detailed Description
The present invention is described in further detail below with reference to examples.
Example (b): a combined circuit strengthening method includes four processes, as shown in fig. 1. A circuit reading process (110), a logic gate to be hardened marking process (120), a grouping process (130) of logic gates to be hardened and a hardening process (140), respectively. The target reinforcement circuit 100 in fig. 1 is shown, and the target circuit of this embodiment is shown in fig. 2. The information of the selected logic gate to be reinforced in the target circuit is shown at 101 in fig. 1, and the logic gate to be reinforced in this embodiment is the logic gate marked by red circle in fig. 2. Fig. 1 shows a circuit 103 where the target circuit is output after being reinforced by the reinforcing method of the present invention.
In this embodiment, the circuit reading process specifically includes the following steps:
(1) the combinatorial circuit shown in fig. 2 is read in and the entire circuit is considered as a directed graph G ═ V, E >. Vertex V in directed graph G contains all the inputs (201, 202, and 203), outputs (211 and 212), and logic gates (221, 222, 223, 224, 225, 226, 227, and 228) in the circuit, and directed edge E of directed graph G contains all the wires in the circuit.
(2) The number of input terminals in the circuit is recorded as NI，NIAll the inputs are numbered IN the reading order, and the serial number of the ith input is marked as INiI is 1, 2, 3. The vertex set formed by all the input ends is recorded as VI，VI＝{IN1,IN2,IN3}; the number of output terminals in the circuit is recorded as NONumbering all the output ends according to the reading sequence, and recording the serial number of the jth output end as OT2iAnd j is 1 or 2. Record the vertex set composed of all the output ends as VO，VO＝{OT1,OT2}; the number of logic gates in the circuit is denoted as NG，NGAll logic gates are numbered in reading order, and the serial number of the kth output end is marked as GAiAnd k is 1, 2, …, 8. Let the vertex set composed of all logic gates be denoted as VG，VG＝{GA1,GA2,…GA8}. Therefore, the set of vertices V of the directed graph G is VI+VO+VG。
(3) The directed edge from vertex u to vertex v is denoted as < u, v >. According to the connection relationship of each element of the circuit in fig. 2, an edge set E of the directed graph G can be obtained as follows:
Figure BDA0002917830680000081
(4) the circuit reading process ends.
In this embodiment, the marking process of the logic gate to be reinforced of the circuit is specifically as follows:
(1) the gate to be reinforced in this embodiment is exemplified by the logic gate selected by the red circle in fig. 1. Denote the number of logic gates to be reinforced as NH，NHLet V denote the vertex set of the logic gate to be reinforcedH，VH＝{GA2,GA4,GA5,GA7And, called reinforcement set.
(2) Set the vertexes VGThe set of non-reinforced vertices in (1) is denoted as VN，VN＝VG-VH＝{GA1,GA3,GA6,GA8And, called a non-consolidated set. Thus, the set of vertices V may be equivalent to VI+VO+VH+VN。
In this embodiment, the grouping process of the logic gates to be reinforced of the circuit specifically includes the following steps:
(1) constructing a length of NHIs denoted as VISIT. VISIT for recording VHThe visited state is set to 0 and the visited state is set to 1. All vertex access states in the initialization VISIT are 0, namely: VISIT ═ 0, 0, 0]。
(2) According to VHOrder of middle vertices, visit VHMiddle 1 st vertex, denoted as v1，v1＝GA2And v in VISIT1To 1, i.e.: VISIT ═ 1, 0, 0, 0]. Search VHIn (a) contains v1The maximum connected subgraph of (2) is that all the vertexes in the maximum connected subgraph are divided into a group and recorded. The following is a specific maximum connected subgraph search process:
first, a null LIST is initialized, which is denoted as LIST1, LIST1 ═]The vertex of the maximum connected subgraph is recorded; v is to be1Added to LIST1, namely: LIST1 ═ GA2]；
② initializing a space two-dimensional columnTABLE, marked as OUTL1, OUTL1 ═ 2 [, [ 2 ]](ii) a The number of rows of OUTL1 is always consistent with the number of elements in LIST1, and each row in OUTL1 is a separate LIST for recording the successor set of vertices to V in LIST1 corresponding to the sequence numberNOr belong to VOThe vertex of (a); add first row in OUTL1, with first row element empty, i.e.: OUTL1 [ [ solution ] ] [ [ solution ] ]]]；
③ visit the first vertex in LIST1, denoted as u, in the front-to-back order of the vertices in LIST11，u1＝GA2；
Retrieving all the terms u in E1The edges that are the starting vertices, i.e.:<GA2,GA5>and obtaining the final vertex of the edge, namely: GA5(ii) a Condition of use 1 (of V)HAnd the access state in VISIT is 0) and condition 2 (belonging to V)NOr belong to VO) Opposite vertex GA5Screening is carried out; because of the GA5Satisfies the condition 1, and the GA5Added to the end of LIST1, namely: LIST1 ═ GA2，GA5](ii) a Mixing GA5The access state in VISIT changes to 1, i.e.: VISIT ═ 1, 0, 1, 0](ii) a Recording the number of vertices satisfying condition 1 as x, where x is 1, adding x rows to OUTL1, and elements in the newly added rows are empty, that is: OUTL1 [, [ solution ]]，[]](ii) a Because of the GA5Condition 2 is not satisfied, so no further operation is performed;
searching all the terms u in E1The edges that end up at the vertices, i.e.:<GA1,GA2>get the starting vertex of the edge, namely GA1(ii) a Condition of use 1 (belonging to V)HAnd the access state in VISIT is 0) to GA1Screening is carried out; because of the GA1Condition 1 is not satisfied, so no further operation is performed;
sixthly, according to the front-back order of the vertexes in LIST1, because the second vertex exists in LIST1, the second vertex in LIST1 is visited and is marked as u2，u2＝GA5；
Seventhly, search for all u in E2The edges that are the starting vertices, namely:<GA5,GA6>and obtaining the final vertex of the edge, namely: GA6(ii) a Condition of use 1 (belonging to V)HAnd the access state in VISIT is 0) and condition 2 (belonging to V)NOr belong to VO) To GA6Screening is carried out; because of the GA6Condition 1 is not satisfied, so no further operation is performed; because of the GA6Satisfying Condition 2, and subjecting GA6Added to the second row of OUTL1, namely: OUTL1 [ [ solution ] ] [ [ solution ] ]]，[GA6]]；
Eighthly search all the groups u in E2The edges that end up at the vertices, i.e.:<GA2,GA5>and<GA4,GA5>obtaining the starting vertices of all edges, i.e. GA2And GA4(ii) a Condition of use 1 (belonging to V)HAnd the VISIT status in VISIT is 0) to screen these vertices; because of the GA4 Satisfying condition 1, GA4Added to the end of LIST1, namely: LIST1 ═ GA2，GA5，GA4]A GA4The access state in VISIT changes to 1, i.e.: VISIT ═ 1, 1, 1, 0](ii) a Recording the number of vertices satisfying condition 1 as x, where x is 1, adding x rows to OUTL1, and elements in the newly added rows are empty, that is: OUTL1 [, [ solution ]]，[GA6]，[]]；
Ninthly, in the front-back order of the vertices in LIST1, because there is a third vertex in LIST1, the third vertex in LIST1 is visited and marked as u3，u3＝GA4；
Search in E all in u3The edges that are the starting vertices, namely:<GA4,GA5>and obtaining the final vertex of the edge, namely: GA5(ii) a Condition of use 1 (of V)HAnd the access state in VISIT is 0) and condition 2 (belonging to V)NOr belong to VO) For GA5Screening is carried out; because of the GA5Condition 1 is not satisfied and condition 2 is not satisfied, so no further operation is performed;
Figure BDA0002917830680000091
retrieve all the terms u in E3The edges that end up at the vertices, namely:<GA3,GA4>and obtaining the starting vertex of the edge, namely: GA3(ii) a Condition of use 1 (of V)HAnd the access state in VISIT is 0) to GA3Screening is carried out; because of the GA3Condition 1 is not satisfied, so no further operation is performed;
Figure BDA0002917830680000092
because there is no fourth element in LIST1, the search ends; at this time LIST1 is VHIn (a) contains v1Of the maximum connected subgraph, OUTL1 records the attributes of V existing in the successor set of all vertices in the maximum connected subgraphNOr belong to VOThe vertex of (2).
(3) According to VHAnd searching the vertex with the next VISIT state of 0 in VISIT. Since there is a vertex whose access state is 0 next in VISIT, this vertex is denoted as v2，v2＝GA7V in VISIT2To 1, i.e.: VISIT ═ 1, 1, 1, 1]. Search VHIn (a) contains v2The maximum connected subgraph of (2) is that all the vertexes in the maximum connected subgraph are divided into a group and recorded. The following is a specific maximum connected subgraph search process:
first, a null LIST is initialized, which is denoted as LIST2, LIST2 ═]And recording the vertex of the maximum connected subgraph. V is to be2Added to LIST2, namely: LIST2 ═ GA7]；
② initialize a hollow two-dimensional list, which is marked as OUTL2, OUTL2 ═ OUTL 2-]. The number of rows of OUTL2 is always consistent with the number of elements in LIST2, and each row in OUTL2 is a separate LIST for recording the successor set of vertices to V in LIST2 corresponding to the sequence numberNOr belong to NOThe vertex of (2). Add first row in OUTL2, with first row element empty, i.e.: OUTL2 [, [ solution ]]]；
Thirdly, according to the front-back order of the vertexes in LIST2, the first vertex in LIST2 is visited and marked as u1，u1＝GA7；
(iv) search for all u in E1The edge that is the starting point, i.e.:<GA7,OT1>to obtain the final vertex of the edgeNamely: OT1. Condition of use 1 (of V)HAnd the access state in VISIT is 0) and condition 2 (belonging to V)NOr belong to VO) To OT1And (4) screening. Because of OT1Condition 1 was not satisfied and no further operation was performed. Because OT1Satisfy Condition 2, OT1Added to the second row of OUTL2, namely: OUTL2 [ [ OT ]1]]；
Searching all the u in E1The edges that end up at the vertices, i.e.:<GA6,GA7>and obtaining the starting vertex of the edge, namely: GA6. Condition of use 1 (belonging to V)HAnd access status in VISIT is 0) to GA6And (4) screening. Because of the GA6Condition 1 is not satisfied, and thus no further operation is performed;
sixthly, because the LIST2 has no second element, the search is finished. At this time LIST2 is VHIn (a) contains v2The OUTL2 records the attributes of V existing in the set of successors of all vertices in the maximally connected subgraphNOr belong to VOThe vertex of (2).
(4) At this time, the visitation states of all vertices in VISIT are 1, so far, VHAll the largest connected subgraphs have been found. VHThe grouping mode of all the vertexes is as follows: LIST1 ═ GA2，GA5，GA4]，LIST2＝[GA7]。
(5) The grouping process ends.
In this embodiment, the circuit strengthening process specifically includes the following steps.
(1) On the basis of the original circuit, the logic gates contained in LIST1 are regarded as a whole, the sub-circuit formed by the whole is subjected to triple modular redundancy, a voting unit is added according to OUTL1, and an example structure and a truth table of the voting unit are shown in fig. 3. The redundant post circuit is shown in fig. 4. The following is a specific redundant consolidation process:
let us denote the set of all logic gates in LIST1 as GSET1, GSET1 ═ GA2，GA5，GA4Let the SET of the connection lines between logic gates in GSET1 be W1SET1，W1SET1＝{<GA2,GA5>,<GA4,GA5>Let the connection between the logic gate in GSET1 and the circuit input or the non-hardened logic gate output be W2SET1, W2SET1 ═ hard-up<GA1,GA2>,<GA3,GA4>}. All elements in GSET1, W1SET1, and W2SET1 are added in duplicate as a whole to the original circuit, namely the added 222 ', 224', 225 ', 222 ", 224", 225 ", 221 to 222', 221 to 222", 223 to 224 ", 222 'to 225', 224 'to 225', 222" to 225 ", and 224" to 225 "lines in fig. 4 compared to fig. 2;
record the number of non-empty rows of elements in OUTL1 as NV1，NV 11. The 1 st element non-empty row, row 2, is accessed in the order of the rows in OUTL 1. The logic gate number in the corresponding circuit of the column is marked as GIN11, GIN11 is GA5That is, 225 in fig. 4, the serial numbers of the two replicates obtained after GIN11 is replicated in step r are denoted as GIN11 'and GIN11 ″, that is, 225' and 225 ″ in fig. 4. The number of elements in the row is 1, and the serial numbers of logic gates or output ends in the circuits corresponding to all the elements in the row are recorded as NOUT111I.e., 226 in fig. 4. A voting unit, denoted as VOT11, 231 in FIG. 4, is added to the original circuit. NOUT111The connection to the GIN11 in the original circuit is removed, i.e., the connection 225 to 226 in fig. 2 is removed. The three inputs of VOT11 are connected to the outputs of GIN11, GIN11 'and GIN11 ", i.e., the connection 225 to 231, the connection 225' to 231 and the connection 225" to 231 in FIG. 4, respectively, and the output of VOT11 is connected to NOUT111The input of the link, i.e. the link 231 to 226 in fig. 4, has just been deleted;
third, because there is no second non-empty row in OUTL1, the triple modular redundancy reinforcement of the group ends.
(2) On the basis of the original circuit, the logic gates contained in the LIST2 are regarded as a whole, the sub-circuit formed by the whole is subjected to triple modular redundancy, and a voting unit is added according to OUTL 2. The redundant post circuit is shown in fig. 5. The following is a specific redundancy consolidation process:
let us denote the set of all logic gates in LIST2 as GSET2, GSET2 ═ GA7And the connection line among logic gates in the GSET1 is taken as W1SET2,
Figure BDA0002917830680000111
the connection between the logic gate and the circuit input terminal or the output terminal of the non-reinforced logic gate in GSET2 is referred to as W2SET2, W2SET2 is a hard unit<GA6,GA7>}. All elements in GSET2, W1SET2 and W2SET2 are added in duplicate as a whole to the original circuit, i.e., 227 ', 227 ", 226 to 227' and 226 to 227" in fig. 5 compared to the addition in fig. 4;
(iv) number of non-empty rows of elements in OUTL2 is denoted as NV2，NV 21. The 1 st element is accessed in the order of the rows in OUTL2, which is not an empty row, row 1. The logic gate number in the corresponding circuit of the column is marked as GIN21, GIN21 is GA7That is, 227 in fig. 5, the sequence numbers of the two copies obtained by replicating GIN21 through step (r) are denoted as GIN21 'and GIN21 ″, that is, 227' and 227 ″ in fig. 5. The number of elements in the row is 1, and the serial numbers of logic gates or output ends in the circuit corresponding to all the elements in the row are recorded as NOUT211I.e. 211 in fig. 5. A voting unit, denoted as VOT21, 232 in fig. 5, is added to the original circuit. NOUT211The connections to GIN21 in the original circuit are deleted, i.e., the connections 227 through 211 in fig. 4 are deleted. The three inputs of VOT21 are connected to the outputs of GIN21, GIN21 'and GIN21 ", i.e., the connection 227 to 232, the connection 227' to 232 and the connection 227" to 232 in FIG. 5, respectively, and the output of VOT21 is connected to NOUT211The input of the link, i.e. the link 232 to 211 in fig. 5, has just been deleted;
third, because there is no second non-empty row in OUTL2, the triple modular redundancy reinforcement of the group ends.
(5) The reinforcing process is finished, and fig. 5 shows the reinforced circuit of this embodiment.

Claims (8)

1. A soft error reinforcement method applied to a combinational logic circuit is characterized by comprising the following four processes: the method comprises the steps of (A) a circuit reading process, (B) a logic gate marking process to be reinforced, (III) a logic gate grouping process to be reinforced and (IV) a reinforcement process; the circuit reading process extracts the connection relation between the constituent elements and the elements of the circuit and constructs a graph theory data structure; in the marking process of the logic gates to be reinforced, the logic gates are classified and marked by reading the selection information of the logic gates to be reinforced, and the number and the positions of the logic gates to be reinforced can be selected arbitrarily according to design requirements; in the grouping process of the logic gates to be reinforced, a specific grouping scheme is obtained by solving the maximum connected subgraph of the directed graph formed by the logic gates to be reinforced; in the reinforcement process, grouping triple modular redundancy reinforcement is carried out on the original circuit according to the grouping scheme;
the circuit reading process specifically comprises the following steps:
(1) the whole circuit is regarded as a directed graph G which is < V, E >, a vertex V in the directed graph G comprises all input ends, output ends and logic gates in the circuit, and a directed edge E in the directed graph G comprises all connecting lines in the circuit;
(2) the number of input terminals of the circuit is recorded as NINumbering all the input ends according to the reading sequence, and recording the serial number of the ith input end as INi，i＝1，2，…，NILet the vertex set composed of all the inputs be denoted as VI，
Figure FDA0003627462610000011
Denote the number of output terminals of the circuit as NONumbering all the output ends according to the reading sequence, and recording the serial number of the jth output end as OTi，j＝1，2，…，NOLet the vertex set composed of all the output ends be denoted as VO，
Figure FDA0003627462610000012
Let the number of logic gates of the circuit be NGNumbering all logic gates according to reading sequence, and recording the serial number of the kth output end as GAi，k＝1，2，…，NGAll logic gates are constructedThe vertex set of is denoted as VG，
Figure FDA0003627462610000013
Then, the vertex set V ═ VI+VO+VG；
(3) Denote the directed edge from vertex u to vertex v as<u,v>According to the connection relation of each element of the circuit, an edge set E of the directed graph G is obtained as
Figure FDA0003627462610000014
Wherein V ∈ VI+VG，u∈VG+VO，
Figure FDA0003627462610000015
Representing the successor set of vertices v in the directed graph G.
2. The soft error reinforcement method according to claim 1, wherein the marking process of the logic gate to be reinforced specifically comprises the following steps:
(1) reading the selection information; the selection information is external data, comprises two kinds of information of the number of doors to be reinforced and the position in the circuit, and is flexibly set according to specific design requirements;
(2) the number of doors to be reinforced is recorded as NHFrom the set of vertices V according to the selection informationGSelecting corresponding reinforced vertex to form new set VHReferred to as a reinforcement set; set the vertex VGThe set of non-reinforced vertices in (1) is denoted as VN＝VG-VHReferred to as the non-consolidated set; thus, the set of vertices V is equivalent to VI+VO+VH+VN。
3. The soft error reinforcement method of claim 1, wherein the grouping process of the logic gates to be reinforced specifically comprises the following steps:
(1) constructing a length of NHIs marked as VISIT, which is used to record VHThe visited state of each vertex in the VISIT is recorded as 0, the visited state is recorded as 1, and the visited states of all the vertices in the initialized VISIT are all 0;
(2) according to VHOrder of middle vertices, visit VHMiddle 1 st vertex, denoted as v1And v in VISIT1Change the access state of (1) to search for VHIn (a) contains v1Dividing all vertexes in the maximum connected subgraph into a group and recording;
(3) according to VHSearching the vertex with the next VISIT state of 0 in VISIT if V is in the order of the vertexHIf there is no vertex whose access state in VISIT is 0 next, the process proceeds to step (7), and if a vertex whose access state in VISIT is 0 next is found, the vertex is marked as v2V in VISIT2Change the access state of (1) to search for VHIn (a) contains v2Dividing all vertexes in the maximum connected subgraph into a group and recording;
(4) according to VHOrder of middle vertex at VHSearching for a vertex whose access state in VISIT is 0, jumping to step (7) if there is no vertex whose access state in VISIT is 0, and marking the vertex as v if there is a vertex whose access state in VISIT is 03V in VISIT3Is changed to 1, search VHIn (a) contains v3Dividing all vertexes in the maximum connected subgraph into a group and recording;
(5) and so on;
(6) finish accessing VHAll the vertices in the VISIT are accessed to be 1 at the moment, and V is obtainedHMarking a list formed by the vertexes in the last maximum connected subgraph as LISTn, and enabling the successor set recorded with the vertexes in the LISTn to belong to VNOr belong to VOThe two-dimensional list of the vertices of (1) is recorded as OUTLn;
(7) to this end, VHWhere all maximum connected subgraphs have been found, VHThe grouping mode of all the vertexes is as follows: LIST1, LIST2, …, LIST;
(8) the grouping process ends.
4. A soft error reinforcement method according to claim 1, characterized in that the reinforcement process comprises the following steps:
(1) regarding the logic gates contained in the LIST1 as a whole, performing triple modular redundancy reinforcement on a sub-circuit formed by the whole, and adding a voting unit according to OUTL 1;
(2) regarding the logic gates contained in the LIST2 as a whole, performing triple modular redundancy reinforcement on a sub-circuit formed by the whole, and adding a voting unit according to OUTL 2;
(3) in analogy, logic gates contained in LIST 3-LISTn are respectively regarded as n-2 integers, triple modular redundancy is carried out on n-2 sub-circuits formed by the n-2 integers, voting units are respectively added according to OUTL 3-OUTLN, and NV is respectively added3，NV4，…，NVnThe concrete redundant reinforcing process of each voting unit is the same as that of the voting unit, and V is obtained after the LISTn is reinforcedHAll logic cells in the stack have been consolidated and cumulatively added
Figure FDA0003627462610000021
A voting unit;
(4) and (5) after the reinforcing process is finished, outputting a reinforced circuit.
5. The soft error reinforcement method of claim 3, wherein the search V in step (2) of the grouping procedureHIn (a) contains v1The specific search process of the maximum connected subgraph is as follows:
firstly, initializing a null LIST, marked as LIST1, for recording the vertex of the maximum connected subgraph and taking v1Adding into LIST 1;
initializing an empty two-dimensional LIST, recording as OUTL1, keeping the line number of OUTL1 consistent with the element number in LIST1 all the time, wherein each line in OUTL1 is an independent LIST for recording the subsequent element set of the vertex of the corresponding serial number in LIST1Belong to VNOr belong to NOAt the vertex of OUTL1, add the first row in OUTL1, the first row element being null;
thirdly, according to the front-back order of the vertexes in LIST1, the first vertex in LIST1 is visited and marked as u1；
Retrieving all the terms u in E1For the edge of the start vertex, get the end vertex of all the edges that satisfy the condition, using condition 1: belong to VHAnd the access state in VISIT is 0, and condition 2: belong to VNOr belong to VOScreening the vertexes, if the vertexes meeting the condition 1 exist, sequentially adding the vertexes meeting the condition 1 to the end of the LIST1, changing the access state of the vertexes meeting the condition 1 in VISIT to 1, recording the number of the vertexes meeting the condition 1 as x, adding x rows in the OUTL1, wherein elements in the newly added rows are null, and if the vertexes meeting the condition 2 exist, adding the vertexes meeting the condition 2 to the first row of the OUTL 1;
searching all the u in E1To end the edges of the vertex, get the starting vertices of all edges that satisfy the condition, use condition 1: belong to VHIf the access state in VISIT is 0, screening the vertexes, sequentially adding the vertexes meeting the condition 1 to the tail of LIST1 if the vertexes meeting the condition 1 exist, changing the access state of the vertexes meeting the condition 1 in VISIT to 1, recording the number of the vertexes meeting the condition 1 as x, adding x rows in OUTL1, and enabling elements in the newly added rows to be null;
sixthly, according to the front-back order of the vertexes in LIST1, if the second vertex exists in LIST1, the second vertex in LIST1 is visited and is marked as u2；
Seventhly, all the groups u in E are searched2For the edge of the starting vertex, the final vertex of all the edges satisfying the condition is obtained, using condition 1: belong to VHAnd the access state in VISIT is 0, and condition 2: belong to VNOr belong to VOThe vertices are screened, and if there is a vertex satisfying condition 1, the vertices satisfying condition 1 are sequentially added to the end of LIST1, the visitation state of the vertex satisfying condition 1 in VISIT is changed to 1, and the number of vertices satisfying condition 1 is countedX, adding x rows in OUTL1, wherein elements in the newly added rows are null, and if a vertex meeting condition 2 exists, adding the vertex meeting condition 2 to the second row of OUTL 1;
searching all the symbols u in E2To end the edges of the vertex, get the starting vertices of all the edges that satisfy the condition, using condition 1: belong to VHIf the access state in VISIT is 0, the vertexes are screened, if the vertexes meeting the condition 1 exist, the vertexes meeting the condition 1 are sequentially added to the tail of LIST1, the access state of the vertexes meeting the condition 1 in VISIT is changed to 1, the number of the vertexes meeting the condition 1 is recorded as x, x rows are added to OUTL1, and elements in the newly added rows are null;
ninthly, so on;
when the last vertex in LIST1 is visited and the number of vertices in LIST1 is not increased, the search is ended, and LIST1 is VHIn (a) contains v1Of the maximum connected subgraph, OUTL1 records the attributes of V existing in the successor set of all vertices in the maximum connected subgraphNOr belong to VOThe vertex of (2).
6. A soft error reinforcement method according to claim 3, characterized in that the search V in step (3) of the grouping procedureHIn (a) contains v2The specific search process of the maximum connected subgraph is as follows:
firstly, initializing a null LIST, recording as LIST2, for recording the vertex of the maximum connected subgraph, and enabling v to be2Adding into LIST 2;
initializing a hollow two-dimensional LIST, recording as OUTL2, keeping the line number of OUTL2 consistent with the element number in LIST2 all the time, wherein each line in OUTL2 is an independent LIST for recording that the successor of the vertex of the corresponding sequence number in LIST2 belongs to V in a centralized mannerNOr belong to VOAt the vertex of OUTL2, add the first row in OUTL2, the first row element being null;
thirdly, according to the front-back order of the vertexes in LIST2, the first vertex in LIST2 is visited and marked as u1；
Fourthly, search inAll in E are u1For the edge of the start vertex, get the end vertex of all the edges that satisfy the condition, using condition 1: belong to VHAnd the access state in VISIT is 0, and condition 2: belong to VNOr belong to VOScreening the vertexes, if a vertex meeting the condition 1 exists, sequentially adding the vertexes meeting the condition 1 to the tail of the LIST2, changing the access state of the vertexes meeting the condition 1 in VISIT to 1, recording the number of the vertexes meeting the condition 1 as x, adding an x row in OUTL2, wherein elements in the newly added row are null, and if a vertex meeting the condition 2 exists, adding a vertex meeting the condition 2 to the first row of OUTL 2;
searching all the terms u in E1To end the edges of the vertex, get the starting vertices of all the edges that satisfy the condition, using condition 1: belong to VHIf the access state in VISIT is 0, screening the vertexes, sequentially adding the vertexes meeting the condition 1 to the tail of LIST2 if the vertexes meeting the condition 1 exist, changing the access state of the vertexes meeting the condition 1 in VISIT to 1, recording the number of the vertexes meeting the condition 1 as x, adding x rows in OUTL2, and enabling elements in the newly added rows to be null;
sixthly, according to the front-back order of the vertexes in LIST1, if the second vertex exists in LIST2, the second vertex in LIST2 is visited and is marked as u2；
Seventhly, all the groups u in E are searched2For the edge of the start vertex, get the end vertex of all the edges that satisfy the condition, using condition 1: belong to VHAnd the access state in VISIT is 0, and condition 2: belong to VNOr belong to VOScreening the vertexes, if the vertexes meeting the condition 1 exist, sequentially adding the vertexes meeting the condition 1 to the tail of the LIST2, changing the access state of the vertexes meeting the condition 1 in VISIT to 1, recording the number of the vertexes meeting the condition 1 as x, adding x rows in OUTL2, wherein elements in the newly added rows are null, and if the vertexes meeting the condition 2 exist, adding the vertexes meeting the condition 2 to a second row of OUTL 2;
searching all the symbols u in E2All edges satisfying the condition are obtained for the edges ending at the vertexUsing condition 1: belong to VHIf the access state in VISIT is 0, the vertexes are screened, if the vertexes meeting the condition 1 exist, the vertexes meeting the condition 1 are sequentially added to the tail of LIST2, the access state of the vertexes meeting the condition 1 in VISIT is changed to 1, the number of the vertexes meeting the condition 1 is recorded as x, x rows are added to OUTL2, and elements in the newly added rows are null;
ninthly, so on;
when the last vertex in LIST2 is visited and the number of vertices in LIST2 is not increased, the search is ended, and LIST2 is VHIn (a) contains v2The OUTL2 records the attributes of V existing in the set of successors of all vertices in the maximally connected subgraphNOr belong to VOThe vertex of (2).
7. The soft error reinforcement method according to claim 4, wherein the redundancy reinforcement in step (1) of the reinforcement process is as follows:
recording a SET formed by all logic gates in the LIST1 as GSET1, a SET formed by connecting lines among the logic gates in the GSET1 as W1SET1, a SET formed by connecting the logic gates in the GSET1 with connecting lines among circuit input ends or non-reinforced logic gate output ends as W2SET1, copying all elements in the GSET1, the W1SET1 and the W2SET1 as a whole to be added into an original circuit in two copies, and distinguishing names of all copies from names of copied objects;
secondly, according to the sequence of the rows in OUTL1, accessing the 1 st element non-empty row, recording the serial numbers of logic gates in the circuits corresponding to the row as GIN11, recording the serial numbers of two copies obtained by copying GIN11 through the step I as GIN11 'and GIN 11', and recording the number of the elements in the row as y11The serial numbers of logic gates or output ends in the circuit corresponding to all elements in the row are recorded as
Figure FDA0003627462610000051
Adding a voting unit, denoted as VOT11, to the original circuit
Figure FDA0003627462610000052
The wiring to GIN11 in the original circuit is deleted, the three inputs of VOT11 are connected to the outputs of GIN11, GIN11 'and GIN 11' respectively, and the output of VOT11 is connected to the output of GIN11
Figure FDA0003627462610000053
The input end of the connecting line is just deleted;
thirdly, according to the sequence of the rows in the OUTL1, accessing the 2 nd element non-empty row, marking the serial number of the logic gate in the circuit corresponding to the row as GIN12, marking the serial numbers of two copies obtained by copying GIN12 through the step (I) as GIN12 'and GIN 12', and marking the number of the elements in the row as y12The serial numbers of the logic gates or the output ends in the circuits corresponding to all the elements in the row are recorded as
Figure FDA0003627462610000054
Adding a voting unit, denoted as VOT12, to the original circuit
Figure FDA0003627462610000055
The wiring to GIN12 in the original circuit is deleted, the three inputs of VOT12 are connected to the outputs of GIN12, GIN12 'and GIN 12' respectively, and the output of VOT12 is connected to the output of GIN12
Figure FDA0003627462610000056
The input end of the connecting line is just deleted;
fourthly, accessing 3 rd to NV (virtual network addresses) in OUTL1 by analogy1Non-empty rows of elements, add No. 3 to NV1Voting units and modifying the connections in the circuit.
8. The soft error reinforcement method according to claim 4, wherein the redundancy reinforcement in step (2) of the reinforcement process is as follows:
recording a SET formed by all logic gates in the LIST2 as GSET2, a SET formed by connecting lines among the logic gates in the GSET2 as W1SET2, a SET formed by connecting the logic gates in the GSET2 with connecting lines among circuit input ends or non-reinforced logic gate output ends as W2SET2, copying all elements in the GSET2, the W1SET2 and the W2SET2 as a whole to be added into an original circuit in two copies, and distinguishing names of all copied bodies (copied logic gates and connecting lines) from names of copied bodies (copied logic gates and connecting lines);
secondly, according to the sequence of the rows in OUTL2, accessing the 1 st element non-empty row, recording the serial numbers of logic gates in the circuits corresponding to the row as GIN21, recording the serial numbers of two copies obtained by copying GIN21 through the step I as GIN21 'and GIN 21', and recording the number of the elements in the row as y21The serial numbers of logic gates or output ends in the circuit corresponding to all elements in the row are recorded as
Figure FDA0003627462610000061
Adding a voting unit, denoted as VOT21, to the original circuit
Figure FDA0003627462610000062
The wiring to GIN21 in the original circuit is deleted, the three inputs of VOT21 are connected to the outputs of GIN21, GIN21 'and GIN 21' respectively, and the output of VOT21 is connected to the output of GIN21
Figure FDA0003627462610000063
The input end of the connecting line is just deleted;
thirdly, according to the sequence of the rows in OUTL2, accessing the 2 nd element non-empty row, recording the serial number of the logic gate in the circuit corresponding to the row as GIN22, recording the serial numbers of two copies obtained by copying GIN22 through the step I as GIN22 'and GIN 22', and recording the number of the elements in the row as y22The serial numbers of logic gates or output ends in the circuit corresponding to all elements in the row are recorded as
Figure FDA0003627462610000064
Adding a voting unit, denoted as VOT22, to the original circuit
Figure FDA0003627462610000065
The wiring to GIN22 in the original circuit is deleted, the three inputs of VOT22 are connected to the outputs of GIN22, GIN22 'and GIN 22' respectively, and the output of VOT22 is connected to the output of GIN22
Figure FDA0003627462610000066
The input end of the connecting line is just deleted;
fourthly, by analogy, accessing the No. 3 to NV in OUTL22Non-empty rows of elements, add 3 rd to NV2Voting units and modifying the connections in the circuit.
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