CN112838049A - Preparation method of conductive structure and preparation method of thin film transistor array substrate - Google Patents
Preparation method of conductive structure and preparation method of thin film transistor array substrate Download PDFInfo
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- CN112838049A CN112838049A CN201911167176.5A CN201911167176A CN112838049A CN 112838049 A CN112838049 A CN 112838049A CN 201911167176 A CN201911167176 A CN 201911167176A CN 112838049 A CN112838049 A CN 112838049A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76865—Selective removal of parts of the layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
Abstract
A method of making a conductive structure comprising the steps of: forming a conductive layer; forming a photoresist layer on the conductive layer; and patterning the conductive layer by using the photoresist layer to form a conductive structure, wherein the deviation of the conductive structure compared with the bilateral critical dimension of the photoresist layer is 0.3-0.8 micrometer. Also provides a preparation method of the thin film transistor array substrate.
Description
Technical Field
The invention relates to the technical field of display, in particular to a preparation method of a conductive structure and a preparation method of a thin film transistor array substrate.
Background
The display device with a narrow bezel requires the area occupied by the peripheral circuits at the edge of the display panel to be as small as possible, and thus requires the line pitch of the peripheral circuits to be as small as possible.
However, after the conductive structure of the conventional peripheral circuit is formed by etching, the critical dimension bias (CD bias) is too large, so that the line pitch cannot be further reduced, which is not favorable for realizing the narrow frame of the display panel.
Disclosure of Invention
The invention provides a preparation method of a conductive structure, which comprises the following steps:
forming a conductive layer;
forming a photoresist layer on the conductive layer;
and patterning the conductive layer by using the photoresist layer to form a conductive structure, wherein the deviation of the conductive structure compared with the bilateral critical dimension of the photoresist layer is 0.3-0.8 micrometer.
The invention also provides a preparation method of the thin film transistor array substrate, which comprises the following steps:
forming a conductive layer;
forming a photoresist layer on the conductive layer;
and patterning the conductive layer by using the photoresist layer to form a conductive structure, wherein the deviation of the conductive structure compared with the bilateral critical dimension of the photoresist layer is 0.3-0.8 micrometer.
According to the preparation method of the conductive structure and the preparation method of the thin film transistor array substrate, after the conductive layer is etched, the deviation of the obtained conductive structure compared with the double-side critical dimension of the photoresist layer can be reduced to 0.3-0.8 micrometer, namely, the distance between the adjacent conductive structures is reduced, and the realization of the narrow frame of the display panel using the conductive structure as a lead is facilitated.
Drawings
Fig. 1 is a flowchart of a method for manufacturing a conductive structure according to an embodiment of the present invention.
Fig. 2 to 4 are schematic cross-sectional views of steps of a method for manufacturing a conductive structure according to an embodiment of the invention.
Fig. 5 is a scanning electron microscope image of a conductive structure according to an embodiment of the invention.
Fig. 6 is a scanning electron microscope image of a conductive structure according to another embodiment of the invention.
Fig. 7 is a flowchart of a method for manufacturing a thin film transistor array substrate according to an embodiment of the invention.
Fig. 8 is a schematic cross-sectional view of a thin film transistor array substrate according to an embodiment of the invention.
Fig. 9 is a scanning electron microscope image of a conductive structure of the prior art.
Description of the main elements
First conductive layer 21
Second conductive layer 22
Third conductive layer 23
The photoresist layer 30
Thin film transistor array substrate 100
Contact hole 61
The following detailed description will further illustrate the invention in conjunction with the above-described figures.
Detailed Description
As shown in fig. 1, a method for manufacturing a conductive structure 40 according to an embodiment of the present invention includes the following steps:
step S11: a conductive layer 20 is formed.
As shown in fig. 2, a substrate 10 is provided, and a conductive layer 20 is formed on the substrate 10. The conductive layer 20 includes a first conductive layer 21, a second conductive layer 22, and a third conductive layer 23 stacked in this order.
Step S12: a photoresist layer 30 is formed on the conductive layer 20.
As shown in fig. 3, a photoresist layer 30 is formed on the surface of the third conductive layer 23 away from the substrate 10.
Step S13: the conductive layer 20 is patterned by using the photoresist layer 30 to form a conductive structure 40, wherein the deviation of the critical dimension of the conductive structure 40 is 0.3 to 0.8 μm compared to the photoresist layer 30.
As shown in fig. 4, the dimension of the photoresist layer 30 on the conductive structure 40 is L1, the dimension of the conductive structure 40 is L2, and the double-sided critical dimension deviation (CDbias) of the conductive structure 40 compared to the photoresist layer 30 is the difference between L1 and L2. The conductive structure 40 has a substantially trapezoidal shape in a cross section perpendicular to the thickness direction of the substrate 10, and the base angle of the trapezoidal shape is the inclination angle α (Taper).
In the method for manufacturing the conductive structure 40 according to the embodiment of the present invention, the deviation of the critical dimension of the conductive structure 40 formed after patterning the conductive layer 20 may be reduced to 0.3 micron to 0.8 micron compared to the photoresist layer 30, so that the distance between adjacent conductive structures 40 may be further reduced.
In one embodiment, the material of the first conductive layer 21 and the third conductive layer 23 is molybdenum nitride (MoN), and the material of the second conductive layer 22 is aluminum (Al). That is, the conductive layer 20 is a stack of MoN/Al/MoN. And simultaneously patterning the MoN/Al/MoN by wet etching to form the conductive structure 40. Compared with the stacked structure of Mo/Al/Mo, the stacked structure of MoN/Al/MoN can adjust the etching rates of the two MoN layers and the Al layer to be similar by adjusting the content of N element in MoN, thereby adjusting the inclination angle alpha of the conductive structure 40.
In one embodiment, in the MoN/Al/MoN stack, the first conductive layer 21, the second conductive layer 22, and the third conductive layer 23 are sequentially formed by sputter coating. Wherein, when the first conductive layer 21(bottom MoN layer) and the third conductive layer 23(top MoN layer) are formed, Ar and N are used2The gas mixing ratio is 1:1 to 1:1.5, and the film coating power of the first conductive layer 21 is less than that of the third conductive layer 23. Therefore, the film forming quality of the MoN layer can be adjusted by adjusting the film coating power of the MoN layer, so that the inclination angle alpha can be adjusted and controlled at will between 20 and 90 degrees.
Specifically, when the plating power of the first conductive layer 21 is 15KW and the plating power of the third conductive layer 23 is 30KW, the tilt angle α of the conductive structure 40 formed after etching may be maintained at 45 ° or more. In addition, the closer the plating power of the first conductive layer 21 and the plating power of the third conductive layer 23 are, the larger the inclination angle α of the conductive structure 40 formed after etching is, and the smaller the defect of the third conductive layer 23(top MoN layer) is.
In addition, when the first conductive layer 21(bottom MoN layer) and the third conductive layer 23(top MoN layer) are formed, when Ar and N are formed2The uneven mixing of the gases can cause too large local film quality difference of the MoN layer, so that the etching rate is reduced in the MoN/Al/MoN patterning process, and the problem of residual (residual) of the MoN layer is caused. In one embodiment, the film forming quality of the third conductive layer 23(top MoN) can be improved by adjusting the film forming power of the third conductive layer 23, so as to avoid the problem of MoN layer residue. For example, when the thickness of the third conductive layer 23(top MoN) to be formed is 500 angstroms, the plating power at the time of forming the layer can be adjusted to 25KW or more. In another embodiment, the problem of residual MoN layer can be avoided by adjusting the etching time in the wet etching process. Specifically, the etching time in the wet etching process may be adjusted to 45 seconds or more.
In the embodiment of the present invention, for the stacked structure of MoN/Al/MoN, Ar and N are adjusted when the first conductive layer 21 and the third conductive layer 23 are formed2The gas mixing proportion and the coating power enable the etching rates of the upper MoN layer and the lower MoN layer to be close to those of the Al layer, so that the inclination angle alpha is steeper, the loss of the third conducting layer 23 is smaller, the deviation of the key size of the two sides is smaller, and the size can be reduced to 0.6-0.8 micrometer. In one embodiment, Ar and N are used to form the first conductive layer 21(bottom MoN layer)2The flow rates of the first and second conductive layers are 235sccm and 300sccm, respectively, the plating power is 15KW, and Ar and N are used for forming the third conductive layer 23(top MoN layer)2The flow rates of the plating solution are 235sccm and 235sccm respectively, and the plating power is 35 KW. Referring to fig. 5 and 9, it can be seen that, for the stack structure of MoN/Al/MoN, the tilt angle α is significantly steeper, the absence of the third conductive layer 23(topMoN) is smaller, and the bilateral critical dimension deviation is smaller.
In another embodiment, the material of the first conductive layer 21 and the third conductive layer 23 is titanium (Ti), and the material of the second conductive layer 22 is aluminum (Al). That is to say that the first and second electrodes,the conductive layer 20 is a stack of Ti/Al/Ti. In the Ti/Al/Ti stack, the first conductive layer 21, the second conductive layer 22, and the third conductive layer 23 may be formed in this order by sputtering, as well. The plating power of the first conductive layer 21(bottom Ti) is the same as the plating power of the first conductive layer 21(bottom MoN), and the plating power of the third conductive layer 23(top Ti) is the same as the plating power of the third conductive layer 23(top MoN), which will not be described herein again. Different from the way in which the stack structure of MoN/Al/MoN is patterned: the Ti/Al/Ti stack is patterned using a pure dry etch to form conductive structure 40. In the dry etching process, the etching gas is Cl2And BCl3。
As can be seen from a combination of fig. 6 and 9, the tilt angle α is significantly steeper, specifically 42.46 °, for the Ti/Al/Ti stack structure.
In another embodiment, before forming the Ti/Al/Ti stack, a process of forming a semiconductor layer 53 (as shown in fig. 8) is further included, and the Ti/Al/Ti stack is formed on the semiconductor layer 53. After patterning, conductive structure 40 serves as source 55 and drain 54 of thin film transistor 50, and semiconductor layer 53 serves as a channel layer of thin film transistor 50.
Generally, in the process of simultaneously patterning the Ti/Al/Ti stack by dry etching, the etching depth of the semiconductor layer under the Ti/Al/Ti stack cannot be controlled, i.e. there is a problem of under layer loss (under layer loss), so that the electrical property of the thin film transistor is abnormal, such as off-state current IoffHigh or low, making the thin film transistor ineffective.
In the embodiment of the present invention, by adjusting the etching uniformity U% of the conductive layer 20 (i.e., the stack of Ti/Al/Ti), or by decreasing the thickness of the second conductive layer 22 (i.e., Al), or by increasing the thickness of the semiconductor layer 53, the bottom layer missing problem can be controlled, and the deviation of the bilateral critical dimension can be reduced to 0.3 to 0.6 μm.
Specifically, the etching uniformity U% of the conductive layer 20 is not more than 15%, and the smaller the etching uniformity U% is, the better, and the etching uniformity U% may be not more than 15% by adjusting the proportion, pressure, power of the etching gas, the types of the coil and the nozzle, and the like; the thickness of the second conductive layer 22(Al) is 2000 a to 3000 a, which can be adjusted according to the product's requirement for the impedance of the conductive structure 40; the material of the semiconductor layer 53 may be amorphous silicon (α -Si), which has a thickness of 1300 to 1900 angstroms and can be adjusted according to the electrical performance of the thin film transistor 50. In other embodiments, the conductive layer 20 is not limited to the three-layer structure, and may be a single-layer structure, a double-layer structure, or even a structure with more than three layers, and may be made of other conductive materials besides molybdenum nitride, aluminum, and titanium, such as gold, copper, and the like.
As shown in fig. 7, an embodiment of the invention further provides a method for manufacturing a thin film transistor array substrate 100, where the thin film transistor array substrate 100 includes the conductive structure 40. The method for manufacturing the thin film transistor array substrate 100 at least includes the following steps:
step S21: a conductive layer 20 is formed.
Step S22: a photoresist layer 30 is formed on the conductive layer 20.
Step S23: the conductive layer 20 is patterned by using the photoresist layer 30 to form a conductive structure 40, wherein the deviation of the critical dimension of the conductive structure 40 is 0.3 to 0.8 μm compared to the photoresist layer 30.
The steps S21 to S23 are the same as the steps S11 to S13, and refer to fig. 2 to 4, which are not repeated herein.
As shown in fig. 8, the thin film transistor array substrate 100 includes a substrate 10, a plurality of thin film transistors 50 (only one is schematically shown in the figure) formed on the substrate 10, and a passivation layer 60 covering a side of the plurality of thin film transistors 50 away from the substrate 10. The thin film transistor 50 includes a gate electrode 51, a gate insulating layer 52 disposed on the gate electrode 51, a semiconductor layer 53 disposed on the gate insulating layer 52, and a source electrode 55 and a drain electrode 54 disposed on the semiconductor layer 53 and the gate insulating layer 52. The tft array substrate 100 further includes a plurality of scan lines (not shown) and a plurality of data lines (not shown). The gate 51 of the thin film transistor 50 is electrically connected to the scan line, and the drain 54 of the thin film transistor 50 is electrically connected to the data line.
In one embodiment, the conductive structure 40 can be at least one of the source 55 of the thin film transistor 50, the drain 54 of the thin film transistor 50, the gate 51 of the thin film transistor 50, a data line, or a scan line. For example, in step S23, when the conductive layer 20 is patterned, the scan line and the gate 51 of the thin film transistor 50 may be formed at the same time; or in step S23, when the conductive layer 20 is patterned, the data line and the source electrode 55 and the drain electrode 54 of the thin film transistor 50 may be formed at the same time.
In the manufacturing method of the thin film transistor array substrate 100, in the process of forming the conductive structure 40 by patterning, the deviation of the critical dimension of both sides is small, so that in a product using the conductive structure 40 as a conducting wire (such as a scanning wire or a data wire), the distance between adjacent conducting wires is equivalently reduced, and the display device using the thin film transistor array substrate 100 can realize a narrow frame design.
With continued reference to fig. 8, the passivation layer 60 has a contact hole 61 exposing the drain electrode 54 of the thin film transistor 50. The thin film transistor array substrate 100 further includes an electrode layer 70, and the electrode layer 70 is electrically connected to the drain 54 of the thin film transistor 50 through the contact hole 61.
In one embodiment, when the tft array substrate 100 is applied to a liquid crystal display device, the electrode layer 70 is a pixel electrode. Further, the thin film transistor array substrate 100 may further include a common electrode.
In another embodiment, when the tft array substrate 100 is applied to an oled display device, the electrode layer 70 is an anode. Further, the thin film transistor array substrate 100 may further include an organic material layer and a cathode electrode.
Although the present invention has been described in detail with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the spirit and scope of the present invention.
Claims (10)
1. A method of making a conductive structure comprising the steps of:
forming a conducting layer, wherein the conducting layer comprises a first conducting layer, a second conducting layer and a third conducting layer which are sequentially stacked, the first conducting layer and the third conducting layer are made of molybdenum nitride, and the second conducting layer is made of aluminum;
forming a photoresist layer on the third conductive layer; and
and patterning the conductive layer by using the photoresist layer to form a conductive structure, wherein the first conductive layer, the second conductive layer and the third conductive layer are simultaneously patterned by adopting a wet etching mode to form the conductive structure, and the deviation of the bilateral critical dimension of the conductive structure compared with the photoresist layer is 0.3-0.8 micrometer.
2. The method according to claim 1, wherein the first conductive layer and the third conductive layer are formed by sputter coating, and wherein a coating power of the first conductive layer is lower than a coating power of the third conductive layer.
3. The method for manufacturing a conductive structure according to claim 2, wherein when the first conductive layer and the third conductive layer are formed, argon gas and nitrogen gas are used as working gases, and a ratio of an argon gas flow rate to a nitrogen gas flow rate is 1:1 to 1: 1.5.
4. The method for producing a conductive structure according to claim 1, wherein an etching time is 45 seconds or more in the wet etching.
5. A method of making a conductive structure comprising the steps of:
forming a conducting layer, wherein the conducting layer comprises a first conducting layer, a second conducting layer and a third conducting layer which are sequentially stacked, the first conducting layer and the third conducting layer are made of titanium, and the second conducting layer is made of aluminum;
forming a photoresist layer on the third conductive layer; and
and patterning the conductive layer by using the photoresist layer to form a conductive structure, wherein the first conductive layer, the second conductive layer and the third conductive layer are simultaneously patterned by adopting a dry etching mode to form the conductive structure, and the deviation of the critical dimension of the conductive structure compared with the photoresist layer is 0.3-0.8 micrometer.
6. The method for manufacturing a conductive structure according to claim 5, further comprising a step of forming a semiconductor layer before forming the conductive layer, wherein the semiconductor layer is a channel layer of a thin film transistor, and the conductive structure is a source electrode and a drain electrode of the thin film transistor.
7. The method of claim 6, wherein the conductive layer has an etch uniformity of no greater than 15%.
8. The method for manufacturing a conductive structure according to claim 6, wherein the second conductive layer has a thickness of 2000 to 3000 angstroms, and the semiconductor layer has a thickness of 1300 to 1900 angstroms.
9. A preparation method of a thin film transistor array substrate comprises the following steps:
forming a conductive layer;
forming a photoresist layer on the conductive layer; and
and patterning the conductive layer by using the photoresist layer to form a conductive structure, wherein the deviation of the conductive structure compared with the bilateral critical dimension of the photoresist layer is 0.3-0.8 micrometer.
10. The method of manufacturing a thin film transistor array substrate of claim 9, wherein the conductive structure is used as at least one of a source electrode of a thin film transistor, a drain electrode of a thin film transistor, a gate electrode of a thin film transistor, a data line, and a scan line.
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| CN201911167176.5A CN112838049B (en) | 2019-11-25 | 2019-11-25 | Preparation method of conductive structure and preparation method of thin film transistor array substrate |
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|---|---|---|---|---|
| US5554488A (en) * | 1994-07-28 | 1996-09-10 | Northern Telecom Limited | Semiconductor device structure and method of formation thereof |
| US6255706B1 (en) * | 1999-01-13 | 2001-07-03 | Fujitsu Limited | Thin film transistor and method of manufacturing same |
| US6376861B1 (en) * | 2000-02-10 | 2002-04-23 | Fujitsu Limited | Thin film transistor and method for fabricating the same |
| US20060281317A1 (en) * | 2005-05-24 | 2006-12-14 | Sharp Kabushiki Kaisha | Thin film transistor substrate and method of fabricating the same |
| US20110186843A1 (en) * | 2010-02-03 | 2011-08-04 | Byeong-Beom Kim | Manufacturing method of thin film and metal line for display using the same, thin film transistor array panel, and method for manufacturing the same |
| WO2013020322A1 (en) * | 2011-08-11 | 2013-02-14 | 深圳市华星光电技术有限公司 | Method for manufacturing thin film transistor matrix substrate and display panel |
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2019
- 2019-11-25 CN CN201911167176.5A patent/CN112838049B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5554488A (en) * | 1994-07-28 | 1996-09-10 | Northern Telecom Limited | Semiconductor device structure and method of formation thereof |
| US6255706B1 (en) * | 1999-01-13 | 2001-07-03 | Fujitsu Limited | Thin film transistor and method of manufacturing same |
| US6376861B1 (en) * | 2000-02-10 | 2002-04-23 | Fujitsu Limited | Thin film transistor and method for fabricating the same |
| US20060281317A1 (en) * | 2005-05-24 | 2006-12-14 | Sharp Kabushiki Kaisha | Thin film transistor substrate and method of fabricating the same |
| US20110186843A1 (en) * | 2010-02-03 | 2011-08-04 | Byeong-Beom Kim | Manufacturing method of thin film and metal line for display using the same, thin film transistor array panel, and method for manufacturing the same |
| WO2013020322A1 (en) * | 2011-08-11 | 2013-02-14 | 深圳市华星光电技术有限公司 | Method for manufacturing thin film transistor matrix substrate and display panel |
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