CN112838007A - Trench gate power device and preparation method thereof - Google Patents
Trench gate power device and preparation method thereof Download PDFInfo
- Publication number
- CN112838007A CN112838007A CN202011638560.1A CN202011638560A CN112838007A CN 112838007 A CN112838007 A CN 112838007A CN 202011638560 A CN202011638560 A CN 202011638560A CN 112838007 A CN112838007 A CN 112838007A
- Authority
- CN
- China
- Prior art keywords
- trench
- region
- insulating layer
- groove
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000002360 preparation method Methods 0.000 title claims abstract description 16
- 239000010410 layer Substances 0.000 claims abstract description 289
- 210000000746 body region Anatomy 0.000 claims abstract description 116
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 86
- 239000000758 substrate Substances 0.000 claims abstract description 78
- 239000004065 semiconductor Substances 0.000 claims abstract description 63
- 238000005530 etching Methods 0.000 claims abstract description 37
- 238000004519 manufacturing process Methods 0.000 claims abstract description 24
- 239000011229 interlayer Substances 0.000 claims abstract description 23
- 238000000151 deposition Methods 0.000 claims abstract description 12
- 229910052751 metal Inorganic materials 0.000 claims description 73
- 239000002184 metal Substances 0.000 claims description 73
- 229920005591 polysilicon Polymers 0.000 claims description 63
- 238000000034 method Methods 0.000 claims description 40
- 230000004888 barrier function Effects 0.000 claims description 34
- 238000011049 filling Methods 0.000 claims description 16
- 238000005468 ion implantation Methods 0.000 claims description 11
- 230000000149 penetrating effect Effects 0.000 claims description 5
- 238000004886 process control Methods 0.000 abstract description 5
- 230000008569 process Effects 0.000 description 30
- 239000000463 material Substances 0.000 description 14
- 238000000137 annealing Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 7
- 238000001259 photo etching Methods 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 239000003989 dielectric material Substances 0.000 description 6
- 238000002513 implantation Methods 0.000 description 6
- 239000012535 impurity Substances 0.000 description 6
- 238000002347 injection Methods 0.000 description 5
- 239000007924 injection Substances 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 230000002349 favourable effect Effects 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 239000005388 borosilicate glass Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000000276 deep-ultraviolet lithography Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000009969 flowable effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000002861 polymer material Substances 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000005204 segregation Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
The embodiment of the application provides a trench gate power device and a preparation method thereof, wherein the preparation method of the trench gate power device comprises the following steps: forming a groove gate type MOS structure in a semiconductor substrate, wherein the groove gate type MOS structure comprises a body region, a first groove, a second groove, a first insulating layer, a second insulating layer, a third insulating layer, first polycrystalline silicon, second polycrystalline silicon, a source region and a fourth insulating layer; depositing a stop layer and an interlayer dielectric layer in sequence; etching the interlayer dielectric layer, the stop layer and the first insulating layer to form a first contact hole; etching the body region around the first groove and the bottom of the first contact hole; and doping the surface of the body region around the first groove to form a contact region. By adopting the scheme in the application, the conducting layer can be uniformly manufactured in the main unit area to realize the leading-out of the electrode, so that the process control difficulty is reduced, the yield is improved, and the manufacturing cost is reduced.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a trench gate power device and a preparation method thereof.
Background
The power Semiconductor device is a basic electronic component for energy conversion and control of a power electronic system, the continuous development of the power electronic technology opens up a wide application Field for the power Semiconductor device, and the power Semiconductor device marked by Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) and Insulated Gate Bipolar Transistor (IGBT) is the mainstream in the Field of the power electronic device at present.
The gate structures of MOSFETs and IGBTs include a trench type and a planar type. The trench gate is usually formed by growing a gate oxide layer on the sidewall of the trench and filling polysilicon, and this gate structure improves the utilization efficiency of the planar area of the power semiconductor device, so that the available channel width and current density per unit area are larger, and the device obtains larger current conduction capability, therefore, the power semiconductor device with the trench gate has been widely applied to various fields such as motor speed regulation, inverters, power supplies, electronic switches, audio devices, automobile electric appliances, and the like.
The mainstream power semiconductor devices with trench type gates are designed by repeating and finally connecting a plurality of cells in parallel according to a certain step pitch. Driven by moore's law, the number of cells per unit area ultimately determines the performance of the device, and thus it is necessary to reduce the size of the trenches and contact holes as much as possible to reduce the size of the cells as much as the fabrication capability allows. The smaller step size places higher demands on the equipment, such as the use of a deep ultraviolet lithography tool with a 248nm or shorter wavelength light source to etch process-sized trenches and contact holes when etching trenches and contact holes. In addition, the step pitch is reduced, and the two-time photoetching patterns for preparing the grooves and the contact holes are required to have higher alignment precision, so that the problems of high process control difficulty, reduced yield, high manufacturing cost and the like are caused.
Disclosure of Invention
The embodiment of the application provides a trench gate power device and a preparation method thereof, which are used for solving the problems of high process control difficulty, yield reduction and high manufacturing cost of the power semiconductor device.
According to a first aspect of embodiments of the present application, there is provided a method for manufacturing a power semiconductor device, including:
forming a trench-gate MOS structure in a semiconductor substrate, the trench-gate MOS structure comprising: a body region extending from the surface of the semiconductor substrate into the semiconductor substrate; a first trench and a second trench penetrating the body region and extending into the semiconductor substrate, the second trench having a width greater than a width of the first trench; a first insulating layer on the surface of the body region; the second insulating layer is positioned on the inner wall of the first groove; the third insulating layer is positioned on the inner wall of the second groove; first polysilicon filling the first trench, the first polysilicon surface being lower than the body surface; filling the second groove and covering the second polysilicon on the partial surface of the first insulating layer, wherein the horizontal projection of the second groove falls into the horizontal projection of the second polysilicon; the source region is positioned on the surface of the body region and on the side face of the body region around the first groove, and the doping type of the source region is opposite to that of the body region; the fourth insulating layer is positioned on the surface of the first polycrystalline silicon;
sequentially depositing a stop layer and an interlayer dielectric layer on the surface of the first insulating layer, the surface of the fourth insulating layer and the surface of the second polycrystalline silicon, wherein the stop layer completely fills the first groove;
etching the interlayer dielectric layer, the stop layer and the first insulating layer to expose the surface of the body region around the first groove, reserving the stop layer in the first groove as a covering structure, and forming a first contact hole, wherein the first contact hole exposes part of the surface of the second polysilicon;
etching the body region around the first groove and the bottom of the first contact hole to remove the source region on the surface of the body region around the first groove and form a gate contact hole, wherein the bottom of the gate contact hole exceeds the surface of the first insulating layer;
and doping the surface of the body region around the first groove to form a contact region, wherein the doping type of the contact region is the same as that of the body region.
Further, forming a trench-gate type MOS structure in a semiconductor substrate includes:
doping the semiconductor substrate to form a body region;
etching the body region to form a first groove and a second groove;
growing a first insulating layer, a second insulating layer and a third insulating layer;
filling and etching back the first trench and the second trench with polysilicon to form first polysilicon and second polysilicon correspondingly;
doping the surface of the body region and the side face of the body region around the first groove to form a source region;
and growing a fourth insulating layer.
Further, doping the surface and the side face of the body region around the first trench to form a source region comprises:
and carrying out ion implantation on the body region, wherein the included angle between the ion incidence direction and the normal of the body region is 30-45 degrees.
Further, etching the interlayer dielectric layer, the stop layer and the first insulating layer includes:
etching the interlayer dielectric layer to expose the stop layer right above the first groove and form a second contact hole, wherein the second contact hole exposes part of the surface of the stop layer above the second polysilicon;
and etching the stop layer and the first insulating layer to expose the surface of the body region around the first groove, reserving the stop layer in the first groove as a covering structure, and forming a first contact hole.
Further, after doping the surface of the body region around the first trench, the method further includes:
sequentially depositing a barrier metal layer and a front metal layer on the surface of the whole device;
and etching the front metal layer and the barrier metal layer to form a first electrode structure and a second electrode structure, wherein the first electrode structure at least covers the covering structure, the source region and the contact region, and the second electrode structure at least fills the gate contact hole.
Further, the preparation method further comprises the following steps:
thinning the semiconductor substrate;
and depositing a back metal layer on the back of the thinned semiconductor substrate.
According to a second aspect of embodiments of the present application, there is provided a trench-gate power device, comprising:
a semiconductor substrate;
the body region extends into the semiconductor substrate from the surface of the semiconductor substrate and comprises a first region and a second region, and a first insulating layer is arranged on the surface of the second region;
the first groove penetrates through the first region and extends into the semiconductor substrate, a second insulating layer is arranged on the inner wall of the first groove, the second insulating layer exceeds the surface of the first region, first polycrystalline silicon, a fourth insulating layer and a covering structure are sequentially arranged in the first groove from bottom to top, the surface of the fourth insulating layer is lower than the surface of the first region, a source region is arranged on the side face of a body region around the first groove, the doping type of the source region is opposite to that of the body region, a contact region is arranged on the surface of the body region around the first groove, and the doping type of the contact region is the same as that of the body region;
the second groove penetrates through the first insulating layer and the second area in sequence and extends into the semiconductor substrate, the width of the second groove is larger than that of the first groove, a third insulating layer is arranged on the inner wall of the second groove, second polycrystalline silicon is filled in the second groove, the second polycrystalline silicon covers part of the surface of the first insulating layer, and the horizontal projection of the second groove falls into the horizontal projection of the second polycrystalline silicon;
the stop layer and the interlayer dielectric layer are sequentially arranged on the surface of the second polycrystalline silicon;
and the bottom of the grid contact hole is higher than the surface of the first insulating layer.
Further, the surface of the first area is lower than the surface of the second area, and the surface of the covering structure and the surface of the second area are in the same plane.
Further, the ratio of the height of the covering structure beyond the surface of the first area to the width of the source region is 1: 1-10: 1.
further, the trench gate power device further includes:
the first electrode structure at least covers the covering structure, the source region and the contact region, the first electrode structure comprises a first barrier metal layer and a first front metal layer, the first barrier metal layer is positioned on the surface of the covering structure, the surface of the source region and the surface of the contact region, and the first front metal layer is positioned on the surface of the first barrier metal layer;
and the second electrode structure at least fills the grid contact hole and comprises a second barrier metal layer and a second front metal layer, wherein the second barrier metal layer is positioned on the inner wall of the grid contact hole, and the second front metal layer is positioned on the surface of the second barrier metal layer.
By using the trench gate power device and the manufacturing method thereof provided by the embodiment of the application, the stop layer in the first trench in the main cell region is reserved as the covering structure, and the source region is formed on the side surface of the body region around the first trench, so that the body region around the first trench can be connected with the front metal layer not through a plurality of small-sized contact holes, but the leading-out of the electrode is realized by uniformly manufacturing the conductive layer. Because small-sized contact holes do not need to be manufactured independently, the harsh requirements of device preparation on high-end semiconductor equipment, particularly high-precision photoetching machines, are reduced, or the dependence on the high-precision photoetching machines is reduced. Moreover, the process requirement of the large-size contact hole on the metalized filling hole is reduced, and high-cost manufacturing processes such as metal plugs, CMP planarization and the like are not needed; and the reliability of a single large-sized contact hole is much higher than that of a plurality of small-sized contact holes. Therefore, the trench gate power device and the preparation method thereof provided in the embodiment of the application can reduce the process control difficulty, improve the yield and reduce the manufacturing cost.
On the basis, the distance between the front metal layer and the polycrystalline silicon in the first groove is increased by reserving the stop layer in the first groove as a covering structure, so that the gate-source capacitance can be reduced, namely the input capacitance is reduced, and the switching speed of the groove gate power device can be improved. In addition, when the contact region is formed by injection, the doping concentration on the surface of the polysilicon gate can be prevented from being reduced due to the influence of inversion injection doping by utilizing the isolation effect of the covering structure, and the abnormal rise of the resistance of the gate can be further prevented, so that the performance of a device can be improved, and the stability of parameters of the device can be guaranteed. In addition, because the covering structure is higher than the source region on the side face of the body region around the first groove, when the source region is formed by injection, the shadow effect of the covering structure is utilized, the phenomenon that the doping concentration of the source region is reduced by inversion injection doping can be avoided, the abnormal rise of the source resistance is avoided, the performance of the device can be further improved, and the stability of the parameters of the device is ensured.
And when forming the second polysilicon filling the second trench, the second polysilicon covers part of the surface of the first insulating layer, i.e. the second polysilicon exceeds the surface of the second trench, so that the bottom of the gate contact hole can be arranged in the second polysilicon and exceeds the first insulating layer, and the bottom of the gate contact hole does not need to be arranged in the second trench, thereby eliminating the position relation limitation of the gate contact hole and the second trench, on one hand, increasing the overlay tolerance of the contact hole, and on the other hand, the key size of the contact hole can not be limited by the width of the second trench. The design freedom of the gate contact hole is enlarged, and the difficulty of process machining is reduced.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
fig. 1 to 13 are schematic device structures in steps of a method for manufacturing a trench gate power device according to an embodiment of the present application.
Detailed Description
In order to make the technical solutions and advantages of the embodiments of the present application clearer, the following describes exemplary embodiments of the present application in further detail with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and are not exhaustive of all the embodiments. It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.
In a first aspect, an embodiment of the present application provides a method for manufacturing a trench gate power device, where the trench gate power device may specifically be a power device such as a MOSFET and an IGBT. The preparation method of the trench gate power device comprises the following steps:
step S11, forming a trench gate MOS structure in the semiconductor substrate, the trench gate MOS structure including: a body region extending from the surface of the semiconductor substrate into the semiconductor substrate; a first trench and a second trench penetrating the body region and extending into the semiconductor substrate, the second trench having a width greater than a width of the first trench; a first insulating layer on the surface of the body region; the second insulating layer is positioned on the inner wall of the first groove; the third insulating layer is positioned on the inner wall of the second groove; first polysilicon filling the first trench, the first polysilicon surface being lower than the body surface; filling the second groove and covering the second polysilicon on the partial surface of the first insulating layer, wherein the horizontal projection of the second groove falls into the horizontal projection of the second polysilicon; the source region is positioned on the surface of the body region and on the side face of the body region around the first groove, and the doping type of the source region is opposite to that of the body region; the fourth insulating layer is positioned on the surface of the first polycrystalline silicon;
step S12, depositing a stop layer and an interlayer dielectric layer on the surface of the first insulating layer, the surface of the fourth insulating layer and the surface of the second polysilicon in sequence, wherein the stop layer completely fills the first trench;
step S13, etching the interlayer dielectric layer, the stop layer and the first insulating layer to expose the body surface around the first trench, reserving the stop layer in the first trench as a covering structure, and forming a first contact hole, wherein the first contact hole exposes part of the surface of the second polysilicon;
step S14, etching the body region around the first groove and the bottom of the first contact hole to remove the source region on the surface of the body region around the first groove and form a gate contact hole, wherein the bottom of the gate contact hole exceeds the surface of the first insulating layer;
step S15, doping the surface of the body region around the first trench to form a contact region, where the doping type of the contact region is the same as the doping type of the body region.
Fig. 1 to 13 are schematic device structure diagrams in steps of a method for manufacturing a trench gate power device according to an embodiment of the present application, and the method for manufacturing a trench gate power device according to an embodiment of the present application is described in detail with reference to fig. 1 to 13.
Referring to fig. 1, a semiconductor substrate is provided and doped to form a body region 13 extending from a surface of the semiconductor substrate into the semiconductor substrate.
The choice of semiconductor substrate is also different for different types of trench-gate power devices. If the MOSFET is prepared, an epitaxial wafer can be used as a semiconductor substrate; for the preparation of an IGBT, an epitaxial wafer or a single wafer can be used as a semiconductor substrate. Taking an epitaxial wafer as an example of a semiconductor substrate, the epitaxial wafer includes a substrate 11 and an epitaxial layer 12 on a surface of the substrate 11. The epitaxial wafer may be obtained commercially, or may be obtained by depositing the epitaxial layer 12 on the surface of the substrate 11 by a Chemical Vapor Deposition (CVD) or Physical Vapor Deposition (PVD) process.
In the embodiments of the present application, the doping types of the substrate 11 and the epitaxial layer 12 are not particularly limited. In general, if the trench gate power device is a MOSFET, the doping types of the substrate 11 and the epitaxial layer 12 are the same, for example, both the substrate 11 and the epitaxial layer 12 are doped N-type or both are doped P-type; if the trench gate power device is an IGBT, the doping types of the substrate 11 and the epitaxial layer 12 may be different, for example, the substrate 11 is doped P-type, and the epitaxial layer 12 is doped N-type. The embodiments of the present application are not limited thereto, and the doping types of the two can be controlled according to the actual device type and parameter requirements.
In trench-gate power devices, the doping concentration of the substrate 11 is typically controlled to be greater than the doping concentration of the epitaxial layer 12. The present invention is not limited thereto and the doping concentrations of both may be controlled according to the actual device type and parameter requirements.
In addition, the larger the thickness of the epitaxial layer 12, the more favorable the breakdown voltage of the device, especially in an IGBT, but the less favorable the miniaturization of the device. The thickness of the substrate 11 and the epitaxial layer 12 can be determined by those skilled in the art according to actual requirements. In this embodiment, the thickness of the epitaxial layer 12 is greater than the depth of the subsequently fabricated trench; in other embodiments, the thickness of the epitaxial layer 12 may be less than or equal to the depth of the subsequently formed trench.
The body region 13 is formed by implanting impurities into the epitaxial layer 12 and then annealing. In particular practice, the junction depth of the body region 13 is also increased by the subsequent thermal processing, so that the annealing after the ion implantation is not an essential step, and whether to perform the annealing or not and the annealing process can be adjusted according to actual process conditions. Of course, the junction depth of body region 13 should be less than the thickness of epitaxial layer 12. The doping impurities and the doping concentration used for doping the epitaxial layer 12 can be set according to actual requirements. In the practice of the present invention, P-type impurities, such as boron, on the order of E12 or more, are implanted into epitaxial layer 12 to form a P-type doped region as body region 13.
The conventional semiconductor process for manufacturing a power device with a trench gate usually performs ion implantation and annealing after the trench gate structure is manufactured to form a body region, and this process easily causes that the device performance cannot reach the expectation, which may be due to: the ion implantation for manufacturing the P-type doped region can enable the oxide layer formed on the side wall of the groove to be implanted with certain impurities, and if the impurities are not properly processed, oxide layer fixed charges can be formed, so that the gate oxide function is degraded and the channel is induced to be pre-opened; when annealing is carried out after injection, due to the existence of the oxide layer on the side wall of the groove, the PN junction surface is bent by the segregation effect, and further, electric field concentration and channel shortening are caused. In the embodiment of the present application, the body region 13 is formed by performing ion implantation before the trench gate structure is fabricated, so that the above-mentioned problem can be avoided.
Referring to fig. 2, the body region 13 is etched to form a first trench 141 and a second trench 142.
Specifically, the body region 13 includes a Main Cell (Main Cell) region and a Gate (Gate) region. A mask (not shown) is disposed on the surface of the body region 13 to define a trench formation region, and the body region 13 is anisotropically etched through a window in the mask to form a plurality of first trenches 141 in the main cell region and a plurality of second trenches 142 in the gate region. Wherein, the width of the first trench 141 is smaller than the width of the second trench 142.
In the implementation of the present application, the first trench 141 and the second trench 142 are both U-shaped trenches. The etching solution can be obtained by anisotropic etching means such as ion milling etching, plasma etching, reactive ion etching, laser ablation and the like, and is not particularly limited. The depth of the trench can be specifically adjusted by controlling the etching time and the etching rate.
Further, in order to avoid a tip problem of a subsequently formed trench gate structure, Rounding etching (Rounding Etch) may be performed on the first trench 141 and the second trench 142, so that inner walls of the first trench 141 and the second trench 142 are rounded.
The depth of the first trench 141 and the second trench 142 is greater than the junction depth of the body region 13. The depths of the first trench 141 and the second trench 142 are sufficiently increased to allow for the junction depth of the P-type doped region to be increased in a subsequent thermal process. In the present embodiment, the first trenches 141 and the second trenches 142 extend into the epitaxial layer 12 through the body region 13. In other embodiments, the depth of the first trench 141 and the second trench 142 may be set by those skilled in the art according to actual needs, for example, the bottom of the first trench 141 and the second trench 142 may reach the surface of the substrate 11 through the epitaxial layer 12 and even extend into the substrate 11.
Referring to fig. 3, an insulating layer is grown over the entire device surface and polysilicon filling is performed.
Specifically, a thermal oxidation process, a chemical vapor deposition process, or the like may be employed to grow the first insulating layer 151 on the surface of the body region 13, the second insulating layer 152 on the inner wall of the first trench 141, and the third insulating layer 153 on the inner wall of the second trench 142.
In an embodiment of the present application, the material of the insulating layer may include one of silicon oxide, silicon nitride, silicon oxynitride, and a high-K gate dielectric material. The thickness of the insulating layer can be set according to the threshold voltage requirement.
After the insulating layer is grown, the first trench 141 and the second trench 142 may be filled with polysilicon by using a CVD process, and the polysilicon may be doped by using thermal diffusion, annealing after ion implantation, or the like. The doping to the polysilicon can adopt an in-situ doping process, namely the doping is completed simultaneously in the growth process of the polysilicon. The thickness of the polysilicon may be set according to actual requirements, as long as it is ensured that the first trench 141 and the second trench 142 are completely filled. Generally, the thickness of the polysilicon needs to be no less than half the width of the widest part of the trench.
Referring to fig. 4, the polysilicon is etched back, the polysilicon in the main cell region is removed, the first polysilicon 161 partially filling the first trench 141 is formed, the polysilicon in the gate region is left partially, and the second polysilicon 162 completely filling the second trench 142 is formed.
Specifically, a photoresist layer is formed on the surface of the gate region as a mask, polysilicon etching is performed by using a dry etching process, a wet etching process, or a dry and wet combined etching process to expose the first insulating layer 151 of the main cell region, and the surface of the polysilicon in the first trench 141 is controlled to be lower than the surface of the body region 13. In the embodiment of the present application, the distance between the surface of the first polysilicon 161 and the surface of the body region 13 is greater than 1000 angstroms, and may be controlled to be about 4500 angstroms, for example. Note that, due to the presence of the second insulating layer 152, the side surfaces of the body region 13 around the first trench 141 can be protected from etching back.
Referring to fig. 5, the surface of body region 13 around first trench 141 and the side of body region 13 are doped to form source region 17.
Specifically, a photoresist layer is formed on the surface of the gate region as a mask, and ion implantation is performed on the main cell region to form the source region 17. In the embodiment of the present application, N-type impurities such as arsenic with an order of magnitude of E15 or more are implanted into the body region 13 by a large angle implantation, and an angle between an ion incident direction and a normal line of the body region 13 is 30 to 45 degrees. After the ion implantation is completed, the photoresist is removed, thereby forming source regions 17 on the surface of body region 13 around first trenches 141 and on the sides of body region 13. Note that when the trench gate power device to be formed is an IGBT, the source region 17 serves as an emitter region of the IGBT.
Referring to fig. 6, a fourth insulating layer 154 is grown on the surface of the first polysilicon 161.
Specifically, after the ion implantation is completed, annealing or silicon oxide deposition is performed to form the fourth insulating layer 154 on the surface of the first polysilicon 161, and the material of the fourth insulating layer 154 may include one of silicon oxide, silicon nitride, silicon oxynitride, and a high-K gate dielectric material.
Referring to fig. 7, a stop layer 18 and an interlevel dielectric layer 19 are sequentially deposited over the entire device surface.
Specifically, the stop layer 18 may be deposited on the surface of the first insulating layer 151, the surface of the fourth insulating layer 154, and the surface of the second polysilicon layer 162 using an LPCVD process, which is characterized by simultaneously growing thin films on the sidewalls and the bottom surface. The thickness of the stop layer 18 may be set according to actual requirements, as long as it is ensured that the first trench 141 is completely filled. Generally, the thickness of the stop layer 18 is larger than half of the maximum width of the first trench 141. In the embodiment of the present application, the material of the stop layer 18 is SiN. SiN is used as an etch stop layer to improve the tolerance of the subsequent hole etch process.
After the stop layer 18 is formed, a dielectric material that is flowable at a predetermined temperature (e.g., 800 ℃ to 1200 ℃) may be coated on the surface of the stop layer 18 by a sputtering deposition process, a chemical vapor deposition process, or a spin-on deposition process. The dielectric material may be any material capable of flowing at a certain temperature and serving as an insulating medium in the art, such as at least one of silicate glass, tetraethoxysilane, spin-on glass (SOG), and polymer material, wherein the silicate glass may include at least one of phosphosilicate glass (PSG), borosilicate glass (BSG), and borophosphosilicate glass (BPSG). By using the above dielectric material as a raw material for deposition, SiO can be formed2The layer being an interlayer dielectricLayer 19.
Referring to fig. 8, the interlayer dielectric layer 19 is etched to expose the stop layer 18 directly over the first trench 141, and a second contact hole 20 is formed, wherein the second contact hole 20 exposes a portion of the surface of the stop layer 18 over the second polysilicon 162.
Specifically, the photoresist is used as a mask, the stop layer 18 is used as an etching stop layer, the interlayer dielectric layer 19 on the surface of the main unit region and a part of the interlayer dielectric layer 19 in the gate region are fully etched, an opening with a large area is formed in the main unit region, and an opening for manufacturing a contact electrode is formed in the gate region. The opening of the main cell region exposes a portion of the stop layer 18 directly above the first trench 141 and around the surface of the body region 13, and the opening of the gate region exposes a portion of the stop layer 18 above the second polysilicon 162.
Compared with the traditional process, the etching process does not need to use a DUV mask to manufacture hundreds of thousands or even millions of independent small holes in the main unit area to manufacture the metal plug, but uses a common photoetching machine to manufacture a large-area opening in the main unit area, and does not need to consider the alignment precision too much, so that the process difficulty of the device is reduced.
Referring to fig. 9, the stop layer 18 and the first insulating layer 151 are etched to expose the surface of the body region 13 around the first trench 141, leave the stop layer 18 inside the first trench 141 as the capping structure 21, and form the first contact hole 22 at the gate region.
Specifically, the etching of the stop layer 18 is continued to remove the stop layer 18 on the surface of the main cell region, so as to expose the surface of the body region 13 around the first trench 141, and the stop layer 18 in the first trench 141 serves as the covering structure 21 to protect the underlying first polysilicon 161. In the gate region, the stop layer 18 at the bottom of the second contact hole 20 is removed by etching the bottom of the second contact hole 20, and the second polysilicon 162 at the bottom of the second contact hole 20 is exposed to form the first contact hole 22. And after the etching is finished, removing the photoresist.
Referring to fig. 10, the body region 13 around the first trench 141 and the bottom of the first contact hole 22 are etched to remove the source region 17 on the surface of the body region 13 around the first trench 141 and form a gate contact hole 23, the bottom of the gate contact hole 23 exceeding the surface of the first insulating layer 151.
Specifically, the interlayer dielectric layer 19 is used as a hard mask, the body region 13 of the main cell region and the second polysilicon 162 at the bottom of the first contact hole 22 are etched, the etching depth is not less than the junction depth of the annealed source region 17, only the source region 17 on the side of the body region 13 around the first trench 141 is reserved, and the gate contact hole 23 is formed. After the etching, the surface of the first trench 141 is higher than the surface of the body region 13 around the first trench, that is, the covering structure 21 is higher than the source region 17 on the side of the body region 13; the bottom of the gate contact hole 23 is higher than the surface of the first insulating layer 151.
Referring to fig. 11, the surface of the body region 13 around the first trench 141 is doped to form a contact region 24 of the first doping type.
Specifically, the contact region 24 is located on a P-type doped region with a relatively low doping concentration, and therefore, in order to ensure ohmic contact and reduce contact resistance, boron implantation is generally performed at a dose of the order of E14. In the embodiment of the present application, the angle between the ion incident direction and the normal of the body region 13 is not less than 7 degrees, for example, a large angle ion implantation is adopted, so that the concentration of the P-type lightly doped region on the exposed sidewall of the body region 13 is supplemented. Since the second polysilicon 162 is heavily N-doped, the effect of the boron implant on the order of E14 is negligible.
In order to form a complete trench-gate power device, after forming the contact region 24, it is also necessary to fabricate an electrode structure.
Referring to fig. 12, a barrier metal layer and a front metal layer are sequentially deposited on the entire device surface, and the barrier metal layer and the front metal layer are etched to form a first electrode structure and a second electrode structure, where the second electrode structure is not in contact with the first electrode structure.
The first electrode structure covers at least the cover structure 21, the source region 17 and the contact region 24. The first electrode structure includes a first barrier metal layer 251 and a first front surface metal layer 261, the first barrier metal layer 251 is positioned on the surface of the capping structure 21, the source region 17, and the contact region 24, and the first front surface metal layer 261 is positioned on the surface of the first barrier metal layer 251. In the embodiment of the present application, the first electrode structure may also cover a portion of the surface of the interlayer dielectric layer 19.
The second electrode structure fills at least the gate contact hole 23. The second electrode structure includes a second barrier metal layer 252 and a second front metal layer 262, the second barrier metal layer 252 is located on the inner wall of the gate contact hole 23, and the second front metal layer 262 is located on the surface of the second barrier metal layer 252. In the embodiment of the present application, the second electrode structure may also cover a portion of the surface of the interlayer dielectric layer 19.
In the embodiment of the present application, the material of the first barrier metal layer 251 and the material of the second barrier metal layer 252 may adopt a combination of Ti and TiN. Wherein, Ti can form metal silicide with Si to reduce contact resistance, and TiN can block sharp pricks caused by alloy process.
When the formed trench gate power device is an MOSFET, the electrode structures formed on the front surface are a source electrode and a grid electrode; when the formed trench gate power device is an IGBT, the electrode structures formed on the front surface are an emitter and a gate. And after the patterning of the front metallization is finished, alloy treatment is carried out, a passivation layer covering the surface of the device can be manufactured according to the requirement, and the process for manufacturing the passivation layer is a conventional process and is not repeated.
Referring to fig. 13, when the trench gate power device formed is a MOSFET, after forming an electrode structure on the front surface, the substrate 11 may be thinned, and a back metal layer 27 may be deposited on the back surface of the substrate 11, where the back metal layer 27 serves as a drain.
When the trench gate power device is formed as an IGBT, after an electrode structure is formed on the front surface, the substrate 11 is thinned, a PN junction is formed in the substrate 11, and finally, a back metal layer 27 is deposited on the back surface of the substrate 11, and the back metal layer 27 serves as a collector.
By using the preparation method of the trench gate power device provided by the embodiment of the present application, the stop layer in the first trench 141 is reserved as the covering structure 21, and the source region 17 is formed on the side surface of the body region 13 around the first trench 141, so that the body region 13 around the first trench 141 can be connected with the front metal layer without a plurality of small-sized contact holes, and the extraction of the electrode is realized by uniformly manufacturing the conductive layer.
Because small-sized contact holes do not need to be manufactured independently, the harsh requirements of device preparation on high-end semiconductor equipment, particularly high-precision photoetching machines, are reduced, or the dependence on the high-precision photoetching machines is reduced. For example, a trench gate power device having a trench gate is manufactured by a conventional semiconductor process, and if the size of a contact hole is 350nm to 250nm, a DUV-KrF lithography machine is generally used, and the wavelength of a light source is 248 nm; if the size of the contact hole is 250nm to 180nm, a DUV-ArF lithography machine is generally used, and the wavelength of the light source is 193 nm. By adopting the preparation method of the trench gate power device provided by the embodiment of the application, only an i-Line photoetching machine is needed, the light source wavelength is 365nm, and the size of the processing key feature is more than 0.4 mu m.
Moreover, the process requirement of the large-size contact hole on the metalized filling hole is reduced, and high-cost manufacturing processes such as metal plugs, CMP planarization and the like are not needed; furthermore, the reliability of a single large-sized contact hole is much higher than that of a plurality of small-sized contact holes. Therefore, the preparation method of the trench gate power device provided by the embodiment of the application can reduce the process control difficulty, improve the yield and reduce the manufacturing cost.
Further, the front metal layer and the first polysilicon 161 are equivalent to two plates of a capacitor, and when the connection mode of the source is changed, the distance between the source and the first polysilicon 161 is inevitably shortened, which may cause the increase of the gate-source parasitic capacitance. In the embodiment of the present invention, the stop layer in the first trench 141 is reserved as the capping structure 21, so that the distance between the two plates of the capacitor is increased in a phase-change manner, and the gate-source parasitic capacitance is reduced. The trench gate power device is mostly applied as a switch, and for a switching element, the size of the capacitor directly affects the switching speed. Because the input capacitance of the device is the sum of the grid-source capacitance and the grid-drain capacitance, the grid-drain capacitance cannot be changed in the embodiment of the application, the input capacitance is reduced by reducing the grid-source capacitance, and the switching speed of the device is further improved.
In addition, when the contact region 24 is formed by implantation, the isolation effect of the capping structure 21 can prevent the doping concentration on the surface of the polysilicon gate (i.e., the first polysilicon 161) from being reduced due to the influence of the inversion implantation doping, thereby preventing the gate resistance from being abnormally increased, and thus improving the device performance and ensuring the stability of the device parameters.
Moreover, since the covering structure 21 is higher than the source region 17 on the side surface of the body region 13 around the first trench 141, when the contact region 24 is formed by implantation, the shadow effect of the covering structure 21 can be used to prevent the doping concentration of the source region 17 from being reduced by the inversion implantation doping, thereby preventing the abnormal rise of the source resistance, further improving the performance of the device, and ensuring the stability of the device parameters. Through further research and practice, the height a of the capping structure 21 above the surface of the source region 17 is preferably greater than or equal to the width b of the source region 17 (as shown in fig. 10), but if the capping structure 21 is too high above the surface of the source region 17, the shadow effect is too significant, which results in discontinuity of the contact region 24, resulting in increased contact resistance and impaired device performance. Therefore, in the implementation of the present application, the ratio of the height a of the cover structure 21 beyond the surface of the source region 17 to the width b of the source region 17 is generally controlled to be 1: 1-10: 1 to optimize device performance.
In addition, when the second polysilicon 162 filling the second trench 142 is formed, the second polysilicon 162 covers a part of the surface of the first insulating layer 151, that is, the second polysilicon 162 exceeds the surface of the second trench 142, so that the bottom of the gate contact hole 23 can be disposed in the second polysilicon 162 and exceeds the first insulating layer 151 without disposing the bottom of the gate contact hole 23 in the second trench 142, thereby eliminating the position relationship limitation between the gate contact hole 23 and the second trench 142, on one hand, increasing the overlay tolerance of the contact hole, and on the other hand, the critical dimension of the contact hole can be not limited by the width of the second trench 142. The degree of freedom in designing the gate contact hole 23 is enlarged while the difficulty in process is reduced.
In a second aspect, embodiments of the present application provide a trench gate power device, which may be a power device having a trench gate, such as a MOSFET and an IGBT. Fig. 13 is a schematic structural diagram of a trench gate power device provided in an embodiment of the present application, where the trench gate power device includes:
a semiconductor substrate;
a body region 13 extending from the surface of the semiconductor substrate into the semiconductor substrate, the body region 13 including a first region and a second region, the surface of the second region being provided with a first insulating layer 151;
a first trench penetrating through the first region and extending into the semiconductor substrate, wherein a second insulating layer 152 is arranged on the inner wall of the first trench, the second insulating layer 152 exceeds the surface of the first region, first polysilicon 161, a fourth insulating layer 154 and a covering structure 21 are sequentially arranged in the first trench from bottom to top, the surface of the fourth insulating layer 154 is lower than the surface of the first region, a source region 17 is arranged on the side surface of a body region 13 around the first trench, the doping type of the source region 17 is opposite to that of the body region 13, a contact region 24 is arranged on the surface of the body region 13 around the first trench, and the doping type of the contact region 24 is the same as that of the body region 13;
a second groove sequentially penetrates through the first insulating layer 151 and the second region and extends into the semiconductor substrate, the width of the second groove is larger than that of the first groove, a third insulating layer 153 is arranged on the inner wall of the second groove, second polycrystalline silicon 162 is filled in the second groove, the second polycrystalline silicon 162 covers part of the surface of the first insulating layer 151, and the horizontal projection of the second groove falls into the horizontal projection of the second polycrystalline silicon 162;
the stop layer 18 and the interlayer dielectric layer 19 are sequentially arranged on the surface of the second polysilicon 162;
through the interlevel dielectric layer 18 and the stop layer 19 in that order and extending into the gate contact opening 23 in the second polysilicon 162 beyond the first insulating layer 151.
Specifically, different types of trench gate power devices correspond to different semiconductor substrates. If the trench gate power device provided by the embodiment of the application is the MOSFET, the semiconductor substrate can be an epitaxial wafer; if the trench gate power device provided in the embodiment of the present application is an IGBT, the semiconductor substrate may be an epitaxial wafer or a single wafer. Taking an epitaxial wafer as an example of a semiconductor substrate, the epitaxial wafer includes a substrate 11 and an epitaxial layer 12 on a surface of the substrate 11. The epitaxial wafer may be obtained commercially, or may be obtained by depositing the epitaxial layer 12 on the surface of the substrate 11 by using a chemical vapor deposition process, a physical vapor deposition process, or the like.
In the embodiments of the present application, the doping types of the substrate 11 and the epitaxial layer 12 are not particularly limited. In general, if the trench gate power device is a MOSFET, the doping types of the substrate 11 and the epitaxial layer 12 are the same, for example, both the substrate 11 and the epitaxial layer 12 are doped N-type or both are doped P-type; if the trench gate power device is an IGBT, the doping types of the substrate 11 and the epitaxial layer 12 may be different, for example, the substrate 11 is doped P-type, and the epitaxial layer 12 is doped N-type. The embodiments of the present application are not limited thereto, and the doping types of the two can be controlled according to the actual device type and parameter requirements.
In trench-gate power devices, the doping concentration of the substrate 11 is typically controlled to be greater than the doping concentration of the epitaxial layer 12. The present invention is not limited thereto and the doping concentrations of both may be controlled according to the actual device type and parameter requirements.
In addition, the larger the thickness of the epitaxial layer 12, the more favorable the breakdown voltage of the device, especially in an IGBT, but the less favorable the miniaturization of the device. The thickness of the substrate 11 and the epitaxial layer 12 can be determined by those skilled in the art according to actual requirements. In this embodiment, the thickness of the epitaxial layer 12 is greater than the depth of the trench; in other embodiments, the thickness of the epitaxial layer 12 may also be less than or equal to the trench depth.
The doping type and doping concentration of the body region 13 can be set according to actual requirements. In the embodiment of the present application, the body region 13 is doped P-type. The junction depth of the body region 13 can be set according to actual requirements, as long as the junction depth of the body region 13 is ensured to be smaller than the thickness of the epitaxial layer 12. The first region of the body region 13 is a main cell region, the second region of the body region 13 is a gate region, and the surface of the first region is lower than the surface of the second region.
The first trench is a trench of the main cell region, and the second trench is a trench of the gate region. In the present embodiment, the depth of the first and second trenches is greater than the junction depth of the body region 13, i.e. the first and second trenches extend through the body region 13 into the epitaxial layer 12. Of course, the embodiments of the present application do not limit this, and those skilled in the art may make other settings on the depths of the first trench and the second trench according to actual needs, for example, the bottoms of the first trench and the second trench may reach the surface of the substrate 11 through the epitaxial layer 12, and even extend into the substrate 11. Further, the bottoms of the first groove and the second groove are of smooth structures.
In the embodiment, the material of the first insulating layer 151, the material of the second insulating layer 152, the material of the third insulating layer 153, the material of the fourth insulating layer 154, and the material of the fourth insulating layer 154 may be the same, and may be selected from one of silicon oxide, silicon nitride, silicon oxynitride, and a high-K gate dielectric material, for example.
In the embodiment of the present application, the material of the capping structure 21 and the material of the stop layer 18 may be the same, and may be SiN, for example. The height of the covering structure 21 can be set according to actual requirements, and in the embodiment of the present application, the surface of the covering structure 21 and the surface of the second area are in the same plane. Further, the ratio of the height of the cover structure 21 beyond the surface of the first region to the width of the source region 17 is 1: 1-10: 1.
in the embodiment of the present application, the material of the interlayer dielectric layer 19 may be SiO2。
Further, the trench gate power device provided in the embodiment of the present application further includes: a first electrode structure covering at least the cover structure 21, the source region 17 and the contact region 22, the first electrode structure including a first barrier metal layer 251 and a first front metal layer 261, the first barrier metal layer 251 being located on a surface of the cover structure 21, a surface of the source region 17 and a surface of the contact region 24, the first front metal layer 261 being located on a surface of the first barrier metal layer 251; and a second electrode structure filling at least the gate contact hole 23, the second electrode structure including a second barrier metal layer 252 and a second front metal layer 262, the second barrier metal layer 252 being located on an inner wall of the gate contact hole 23, and the second front metal layer 262 being located on a surface of the second barrier metal layer 252.
Specifically, if the trench gate power device provided in the embodiment of the present application is a MOSFET, the first electrode structure and the second electrode structure are a source and a gate, respectively; if the trench gate power device provided in the embodiment of the present application is an IGBT, the first electrode structure and the second electrode structure are an emitter and a gate, respectively. In the embodiment of the present application, the first barrier metal layer 251 and the second barrier metal layer 252 employ a combination of Ti and TiN.
Further, the trench gate power device provided in the embodiment of the present application further includes: and a back metal layer 27 on the back surface of the semiconductor substrate. If the trench gate power device provided by the embodiment of the application is a MOSFET, the back metal layer 27 serves as a drain; if the trench gate power device provided in the embodiment of the present application is an IGBT, the back metal layer 27 serves as a collector. In addition, for the IGBT, the device structure thereof further includes a PN junction located in the semiconductor substrate.
While the preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all alterations and modifications as fall within the scope of the application.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.
Claims (10)
1. A preparation method of a trench gate power device is characterized by comprising the following steps:
forming a trench-gate MOS structure in a semiconductor substrate, the trench-gate MOS structure comprising: a body region extending from the semiconductor substrate surface into the semiconductor substrate; a first trench and a second trench penetrating the body region and extending into the semiconductor substrate, the second trench having a width greater than a width of the first trench; a first insulating layer located on the surface of the body region; the second insulating layer is positioned on the inner wall of the first groove; the third insulating layer is positioned on the inner wall of the second groove; a first polysilicon filling the first trench, the first polysilicon surface being lower than the body region surface; the second polycrystalline silicon fills the second groove and covers part of the surface of the first insulating layer, and the horizontal projection of the second groove falls into the horizontal projection of the second polycrystalline silicon; the source region is positioned on the surface of the body region and on the side face of the body region around the first trench, and the doping type of the source region is opposite to that of the body region; a fourth insulating layer on the surface of the first polysilicon;
sequentially depositing a stop layer and an interlayer dielectric layer on the surface of the first insulating layer, the surface of the fourth insulating layer and the surface of the second polycrystalline silicon, wherein the stop layer completely fills the first groove;
etching the interlayer dielectric layer, the stop layer and the first insulating layer to expose the body area surface around the first groove, reserving the stop layer in the first groove as a covering structure, and forming a first contact hole, wherein the first contact hole exposes part of the surface of the second polysilicon;
etching the body region around the first groove and the bottom of the first contact hole to remove the source region on the surface of the body region around the first groove and form a gate contact hole, wherein the bottom of the gate contact hole exceeds the surface of the first insulating layer;
and doping the surface of the body region around the first groove to form a contact region, wherein the doping type of the contact region is the same as that of the body region.
2. The method of claim 1, wherein forming a trench-gate MOS structure in a semiconductor substrate comprises:
doping the semiconductor substrate to form the body region;
etching the body region to form the first trench and the second trench;
growing the first insulating layer, the second insulating layer, and the third insulating layer;
filling and etching back the first trench and the second trench with polysilicon to form the first polysilicon and the second polysilicon correspondingly;
doping the surface and the side face of the body region around the first groove to form the source region;
growing the fourth insulating layer.
3. The method of claim 2, wherein doping the body surface and the body side around the first trench to form the source region comprises:
and carrying out ion implantation on the body region, wherein an included angle between the ion incidence direction and the normal of the body region is 30-45 degrees.
4. The method according to claim 1, wherein etching the interlayer dielectric layer, the stop layer, and the first insulating layer comprises:
etching the interlayer dielectric layer to expose the stop layer positioned right above the first groove and form a second contact hole, wherein the second contact hole exposes part of the surface of the stop layer positioned above the second polycrystalline silicon;
and etching the stop layer and the first insulating layer to expose the surface of the body region around the first groove, reserving the stop layer in the first groove as the covering structure, and forming the first contact hole.
5. The method according to any one of claims 1 to 4, further comprising, after doping the surface of the body region around the first trench:
sequentially depositing a barrier metal layer and a front metal layer on the surface of the whole device;
and etching the front metal layer and the barrier metal layer to form a first electrode structure and a second electrode structure, wherein the first electrode structure at least covers the covering structure, the source region and the contact region, and the second electrode structure at least fills the gate contact hole.
6. The method of manufacturing according to claim 5, further comprising:
thinning the semiconductor substrate;
and depositing a back metal layer on the back of the thinned semiconductor substrate.
7. A trench-gate power device, comprising:
a semiconductor substrate;
the body region extends into the semiconductor substrate from the surface of the semiconductor substrate and comprises a first region and a second region, and a first insulating layer is arranged on the surface of the second region;
a first trench penetrating through the first region and extending into the semiconductor substrate, wherein a second insulating layer is arranged on the inner wall of the first trench, the second insulating layer exceeds the surface of the first region, first polycrystalline silicon, a fourth insulating layer and a covering structure are sequentially arranged in the first trench from bottom to top, the surface of the fourth insulating layer is lower than the surface of the first region, a source region is arranged on the side surface of a body region around the first trench, the doping type of the source region is opposite to that of the body region, a contact region is arranged on the surface of the body region around the first trench, and the doping type of the contact region is the same as that of the body region;
a second groove sequentially penetrates through the first insulating layer and the second region and extends into the semiconductor substrate, the width of the second groove is larger than that of the first groove, a third insulating layer is arranged on the inner wall of the second groove, second polycrystalline silicon is filled in the second groove, the second polycrystalline silicon covers part of the surface of the first insulating layer, and the horizontal projection of the second groove falls into the horizontal projection of the second polycrystalline silicon;
the stop layer and the interlayer dielectric layer are sequentially arranged on the surface of the second polycrystalline silicon;
and the bottom of the grid contact hole is higher than the surface of the first insulating layer.
8. The trench-gate power device of claim 7, wherein the first region surface is lower than the second region surface, and wherein the surface of the capping structure and the second region surface are in the same plane.
9. The trench-gate power device of claim 7 or 8, wherein a ratio of a height of the cover structure beyond the surface of the first region to a width of the source region is 1: 1-10: 1.
10. the trench-gate power device of claim 7, further comprising:
a first electrode structure at least covering the cover structure, the source region and the contact region, the first electrode structure including a first barrier metal layer and a first front metal layer, the first barrier metal layer being located on a surface of the cover structure, a surface of the source region and a surface of the contact region, the first front metal layer being located on a surface of the first barrier metal layer;
and the second electrode structure at least fills the grid contact hole, and comprises a second barrier metal layer and a second front metal layer, wherein the second barrier metal layer is positioned on the inner wall of the grid contact hole, and the second front metal layer is positioned on the surface of the second barrier metal layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011638560.1A CN112838007B (en) | 2020-12-31 | 2020-12-31 | Trench gate power device and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011638560.1A CN112838007B (en) | 2020-12-31 | 2020-12-31 | Trench gate power device and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112838007A true CN112838007A (en) | 2021-05-25 |
| CN112838007B CN112838007B (en) | 2022-07-05 |
Family
ID=75926758
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011638560.1A Active CN112838007B (en) | 2020-12-31 | 2020-12-31 | Trench gate power device and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112838007B (en) |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1445861A (en) * | 2002-03-19 | 2003-10-01 | 因芬尼昂技术股份公司 | Electric crystal permutation with bucking electrodes and minor brake pole-draw pole capacitor out of active array |
| CN101866923A (en) * | 2010-05-18 | 2010-10-20 | 苏州硅能半导体科技股份有限公司 | Three-layer light cover groove MOS device and manufacture method |
| CN104617045A (en) * | 2015-01-19 | 2015-05-13 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of trench gate power device |
| CN107527944A (en) * | 2017-07-28 | 2017-12-29 | 上海华虹宏力半导体制造有限公司 | Groove power MOSFET and its manufacture method |
| CN107871787A (en) * | 2017-10-11 | 2018-04-03 | 矽力杰半导体技术(杭州)有限公司 | A kind of manufacture groove MOSFET method |
| CN108962989A (en) * | 2017-05-23 | 2018-12-07 | 中航（重庆）微电子有限公司 | A kind of groove type MOS device and its manufacturing method |
| CN110429129A (en) * | 2019-08-08 | 2019-11-08 | 南京芯长征科技有限公司 | High pressure trench-type power semiconductor device and preparation method |
| US20200395468A1 (en) * | 2019-06-17 | 2020-12-17 | Semiconductor Components Industries, Llc | Method of forming a semiconductor device |
-
2020
- 2020-12-31 CN CN202011638560.1A patent/CN112838007B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1445861A (en) * | 2002-03-19 | 2003-10-01 | 因芬尼昂技术股份公司 | Electric crystal permutation with bucking electrodes and minor brake pole-draw pole capacitor out of active array |
| CN101866923A (en) * | 2010-05-18 | 2010-10-20 | 苏州硅能半导体科技股份有限公司 | Three-layer light cover groove MOS device and manufacture method |
| CN104617045A (en) * | 2015-01-19 | 2015-05-13 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of trench gate power device |
| CN108962989A (en) * | 2017-05-23 | 2018-12-07 | 中航（重庆）微电子有限公司 | A kind of groove type MOS device and its manufacturing method |
| CN107527944A (en) * | 2017-07-28 | 2017-12-29 | 上海华虹宏力半导体制造有限公司 | Groove power MOSFET and its manufacture method |
| CN107871787A (en) * | 2017-10-11 | 2018-04-03 | 矽力杰半导体技术(杭州)有限公司 | A kind of manufacture groove MOSFET method |
| US20200395468A1 (en) * | 2019-06-17 | 2020-12-17 | Semiconductor Components Industries, Llc | Method of forming a semiconductor device |
| CN110429129A (en) * | 2019-08-08 | 2019-11-08 | 南京芯长征科技有限公司 | High pressure trench-type power semiconductor device and preparation method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112838007B (en) | 2022-07-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6337262B1 (en) | Self aligned T-top gate process integration | |
| US6144065A (en) | MOS gated device with self aligned cells | |
| US20200220007A1 (en) | Schottky power mosfet | |
| EP1610372B1 (en) | Fabrication method of a self aligned contact in a semiconductor device | |
| US8497551B2 (en) | Self-aligned contact for trench MOSFET | |
| US7799642B2 (en) | Trench MOSFET and method of manufacture utilizing two masks | |
| KR101430824B1 (en) | Vertical power mosfet and methods of forming the same | |
| US7687352B2 (en) | Trench MOSFET and method of manufacture utilizing four masks | |
| JP2010500765A (en) | JFET with built-in back gate in either SOI or bulk silicon | |
| US20090014787A1 (en) | Multi-Layer Semiconductor Structure and Manufacturing Method Thereof | |
| US20090085099A1 (en) | Trench mosfet and method of manufacture utilizing three masks | |
| SG188697A1 (en) | Trench transistor | |
| CN112820645B (en) | Power semiconductor device and preparation method thereof | |
| US8492221B2 (en) | Method for fabricating power semiconductor device with super junction structure | |
| JP3965027B2 (en) | Method for manufacturing trench gate type MIS device having thick polysilicon insulating layer at bottom of trench | |
| WO2020198738A1 (en) | Extended drain mos with dual well isolation | |
| CN111508843A (en) | Semiconductor device and method of forming the same | |
| CN112133750B (en) | Deep trench power device and preparation method thereof | |
| CN213816159U (en) | Power semiconductor device | |
| CN109119473B (en) | Transistor and manufacturing method thereof | |
| CN101807546B (en) | Trench type metal-oxide semiconductor device and manufacture method thereof | |
| CN112838007B (en) | Trench gate power device and preparation method thereof | |
| CN213816161U (en) | Semiconductor device with groove type grid | |
| CN106057681B (en) | Groove power device and manufacturing method | |
| CN112530867B (en) | Trench type field effect transistor structure and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |