CN112837618B - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
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- CN112837618B CN112837618B CN202110034393.8A CN202110034393A CN112837618B CN 112837618 B CN112837618 B CN 112837618B CN 202110034393 A CN202110034393 A CN 202110034393A CN 112837618 B CN112837618 B CN 112837618B
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- 239000000758 substrate Substances 0.000 claims abstract description 54
- 239000000463 material Substances 0.000 claims description 11
- 238000003491 array Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 89
- 238000000034 method Methods 0.000 description 22
- 238000010586 diagram Methods 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 5
- 230000000052 comparative effect Effects 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 4
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 230000002146 bilateral effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
Abstract
The application discloses a display panel and a display device. A display panel having a display area and a non-display area distributed at least partially around the display area, the display panel comprising: a substrate; a first fixed voltage signal line on the substrate and located in a non-display region of at least one side of the display region in a first direction, the first fixed voltage signal line extending in a second direction intersecting the first direction, the first fixed voltage signal line including a first section and a second section connected to each other; and one end of the second fixed voltage signal wire is connected with the joint of the first section and the second section, and the other end of the second fixed voltage signal wire is electrically connected with the power end of the display panel. According to the embodiment of the application, the brightness uniformity of the display panel can be improved.
Description
Technical Field
The application relates to the technical field of display, in particular to a display panel and a display device.
Background
With the continuous update of display panel technology, display panels are gradually developing towards light and thin, high screen occupation ratio and ultra-narrow frame. The display panel generally comprises a display area and a non-display area positioned on the periphery of the display area, the non-display area is used for arranging signal lines, the display area of the display panel is continuously increased, the space of the non-display area is continuously extruded and reduced, and the space which can be reserved for the signal lines to pass through in the non-display area is further narrow, so that under the condition, the resistance of the signal lines is excessively large, and the brightness of the whole display panel is inconsistent.
In the prior art, the brightness is usually compensated by using a sub-circuit built by a thin film transistor in the pixel, and the pixel structure and the driving mode of the method are complex, so that more unnecessary troubles are brought to the manufacturing process.
Disclosure of Invention
The embodiment of the application provides a display panel and a display device, which can improve the brightness uniformity of the display panel.
In a first aspect, embodiments of the present application provide a display panel having a display region and a non-display region distributed around at least a portion of the display region, the display panel comprising: a substrate; a first fixed voltage signal line on the substrate and located in a non-display region of at least one side of the display region in a first direction, the first fixed voltage signal line extending in a second direction intersecting the first direction, the first fixed voltage signal line including a first section and a second section connected to each other; and one end of the second fixed voltage signal wire is connected with the connecting part of the first section and the second section, and the other end of the second fixed voltage signal wire is electrically connected with the power end of the display panel.
In a possible implementation manner of the first aspect, the first fixed voltage signal line further includes a connection structure, the first segment and the second segment are connected by the connection structure, and the first segment, the second segment and the connection structure are an integral structure.
In a possible implementation manner of the first aspect, the lengths of the first section and the third section in the second direction are equal and greater than the length of the second section in the second direction;
the first and third sections have equal widths in the first direction and are smaller than the second section.
In a possible implementation manner of the first aspect, the first fixed voltage signal line and the second fixed voltage signal line are located in different conductive layers or in the same conductive layer.
In a possible implementation manner of the first aspect, the display panel further includes:
the light-emitting elements are positioned on the substrate, the plurality of light-emitting element arrays are distributed in the display area, and each light-emitting element comprises a first electrode, a light-emitting layer and a second electrode which are stacked;
and/or reference voltage signal lines on the substrate, wherein the plurality of reference voltage signal lines are positioned in the display area, extend along the first direction and are distributed at intervals in the second direction;
wherein the first fixed voltage signal line is electrically connected with at least one of the second electrode and the reference voltage signal line.
In a possible implementation manner of the first aspect, the first fixed voltage signal line is electrically connected to the second electrode, the first fixed voltage signal line is located on a side of the second fixed voltage signal line facing away from the substrate, and a front projection of the first fixed voltage signal line on the substrate overlaps a front projection of the second fixed voltage signal line on the substrate.
In a possible implementation manner of the first aspect, the display area is provided with a first fixed voltage signal line and a second fixed voltage signal line on two sides of the first direction, and the second electrode is electrically connected with the first fixed voltage signal line on two sides of the first direction.
In a possible implementation manner of the first aspect, a length of the second fixed voltage signal line in the second direction is smaller than a length of the first fixed voltage signal line in the second direction.
In a possible implementation manner of the first aspect, the display panel further includes a third fixed voltage signal line, the first fixed voltage signal line is electrically connected to the second electrode through the third fixed voltage signal line, and the first fixed voltage signal line and the third fixed voltage signal line are located in different conductive layers.
In a possible implementation manner of the first aspect, the third fixed voltage signal line is located on a side of the first fixed voltage signal line facing away from the substrate.
In a possible implementation manner of the first aspect, the orthographic projection of the first fixed voltage signal line on the substrate overlaps with the orthographic projection of the third fixed voltage signal line on the substrate.
In a possible implementation manner of the first aspect, the third fixed voltage signal line is disposed in the same layer as the first electrode, and the third fixed voltage signal line is made of the same material as the first electrode.
In a possible implementation manner of the first aspect, a length of the third fixed voltage signal line in the second direction is equal to a length of the first fixed voltage signal line in the second direction.
In a possible implementation manner of the first aspect, the first fixed voltage signal line is connected to the third fixed voltage signal line through a first channel, the third fixed voltage signal line is connected to the second electrode through a second channel, and a front projection of at least one of the first channel and the second channel on the substrate is in a shape of a bar.
In a possible implementation manner of the first aspect, the display panel further includes a driving device layer, the first fixed voltage signal line and the second fixed voltage signal line are both disposed on the driving device layer, and the light emitting element is located on a side of the driving device layer facing away from the substrate;
the driving device layer includes a transistor including a gate, a source, and a drain, the second fixed voltage signal line is disposed in the same layer as the source and the drain of the transistor, and the second fixed voltage signal line is of the same material as the source and the drain of the transistor.
In a possible implementation manner of the first aspect, the first fixed voltage signal line is located between the source and the drain of the transistor and the first electrode.
In a possible implementation manner of the first aspect, the first fixed voltage signal line is electrically connected to the reference voltage signal line, and the first fixed voltage signal line and the second fixed voltage signal line are located on the same conductive layer.
In a possible implementation manner of the first aspect, the first fixed voltage signal line, the second fixed voltage signal line and the reference voltage signal line are located on the same conductive layer.
In a possible implementation manner of the first aspect, the first fixed voltage signal line, the second fixed voltage signal line and the reference voltage signal line are made of the same material.
In a possible implementation manner of the first aspect, the display area is provided with a first fixed voltage signal line and a second fixed voltage signal line on two sides of the first direction, and each reference voltage signal line is connected with the first fixed voltage signal line on two sides of the first direction.
In a second aspect, embodiments of the present application further provide a display device, which includes a display panel according to any one of the embodiments of the first aspect.
According to the display panel and the display device provided by the embodiment of the application, the first fixed voltage signal line comprises the first section and the second section which are connected with each other, one end of the second fixed voltage signal line is connected with the connecting part of the first section and the second section, the other end of the second fixed voltage signal line is electrically connected with the power end of the display panel, and the first fixed voltage signal line is divided into two parallel resistors by being electrically connected with the power end through the connecting part of the first section and the second section.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings, in which like or similar reference characters designate the same or similar features, and which are not to scale.
FIG. 1 is a schematic top view of a display panel according to one embodiment of the present application;
FIG. 2 shows a schematic top view of a display panel of a comparative example;
FIG. 3 shows a schematic diagram of an equivalent circuit of FIG. 2;
FIG. 4 shows a schematic diagram of an equivalent circuit of FIG. 1;
FIG. 5 is a schematic top view of a display panel according to another embodiment of the present disclosure;
FIG. 6 shows an exemplary schematic cross-sectional view in the direction A-A of FIG. 5;
FIG. 7 shows a schematic diagram of one current flow path of FIG. 6;
FIG. 8 is a schematic top view of a display panel according to another embodiment of the present disclosure;
FIG. 9 shows an exemplary schematic cross-sectional view in the direction B-B of FIG. 8;
fig. 10 shows a schematic top view of a display device according to an embodiment of the present application.
Detailed Description
Features and exemplary embodiments of various aspects of the present application are described in detail below to make the objects, technical solutions and advantages of the present application more apparent, and to further describe the present application in conjunction with the accompanying drawings and the detailed embodiments. It should be understood that the specific embodiments described herein are merely configured to explain the present application and are not configured to limit the present application. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by showing examples of the present application.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.
It will be understood that when a layer, an area, or a structure is described as being "on" or "over" another layer, another area, it can be referred to as being directly on the other layer, another area, or another layer or area can be included between the layer and the other layer, another area. And if the component is turned over, that layer, one region, will be "under" or "beneath" the other layer, another region.
The embodiment of the application provides a display panel and a display device, and various embodiments of the display panel and the display device will be described below with reference to the accompanying drawings.
The display panel provided in the embodiments of the present application may be an organic light emitting diode (Organic Light Emitting Diode, OLED) display panel, which is not limited in this application.
Fig. 1 shows a schematic top view of a display panel according to an embodiment of the present application. Fig. 2 shows a schematic cross-sectional view in the direction A-A of fig. 1 of an example. Referring to fig. 1 and 2, a display panel 100 according to an embodiment of the present disclosure has a display area AA and a non-display area NA. The non-display area NA is disposed around at least part of the display area AA. The display area AA of the display panel 100 is exemplarily illustrated as a regular rectangle in fig. 1. In other optional embodiments of the present application, the display area AA of the display panel 100 may also be configured as a special shape. For example, four corners of the display area AA may be provided in a circular arc shape, and four corners of the non-display area NA of the display panel 100 may be provided in a circular arc shape.
The display panel 100 provided in the embodiment of the present application may include a substrate 10 and first and second fixed voltage signal lines 21 and 22 positioned at one side of the substrate 10. The substrate 10 may be a flexible substrate or a rigid substrate, for example, and is not limited in this application.
The first fixed voltage signal line 21 may be located in the non-display area NA of at least one side of the display area AA in the first direction X. In fig. 1, it is exemplarily shown that the non-display areas NA on both sides of the display area AA are provided with the first fixed voltage signal lines 21 in the first direction X, and the second fixed voltage signal lines 22 are connected to the first fixed voltage signal lines 21, it will be understood that in the case that the non-display areas NA on both sides of the display area AA are provided with the first fixed voltage signal lines 21 in the first direction X, the non-display areas NA on both sides of the display area AA are also provided with the second fixed voltage signal lines 22 in the first direction X.
The first fixed voltage signal line 21 extends in a second direction Y intersecting the first direction X. For example, the first direction X and the second direction Y may be perpendicular. The first direction X may be a row direction and the second direction Y may be a column direction. The first fixed voltage signal line 21 includes a first section 211 and a second section 213 connected to each other, and the connection between the first section 211 and the second section 213 is M. One end of the second fixed voltage signal line 22 is connected to the junction M of the first segment 211 and the second segment 213, and the other end is connected to a power source terminal (not shown) of the display panel 100. In addition, the second fixed voltage signal line 22 also extends in the second direction Y. The display panel 100 may include a bonding area TA, and a power terminal of the display panel 100 may be disposed in the bonding area TA.
In this embodiment, since one end of the second fixed voltage signal line 22 is connected to the connection M of the first segment 211 and the second segment 213, that is, the electrical connection to the power source terminal of the display panel 100 is implemented at approximately the middle position of the first fixed voltage signal line 21.
In order to more clearly illustrate the technical effects of the embodiments of the present application, fig. 2 shows a schematic top view of a display panel of a comparative example. As shown in fig. 2, the first fixed voltage signal line 21' is directly electrically connected to the power source terminal of the display panel 100 through an end portion thereof. Fig. 3 shows a schematic diagram of an equivalent circuit of fig. 2. Since the end portions of the first fixed voltage signal lines 21' are directly electrically connected to the power source terminal, one first fixed voltage signal line 21' on one side of the display area AA corresponds to one resistor, and two first fixed voltage signal lines 21' on both sides of the display area AA correspond to two parallel resistors.
Fig. 4 shows a schematic diagram of an equivalent circuit of fig. 1. Unlike the comparative example, the first fixed voltage signal line 21 in the embodiment of the present application is no longer directly electrically connected to the power supply terminal through the end thereof, but is electrically connected to the power supply terminal through the junction M of the first section 211 and the second section 213. That is, in the embodiment of the present application, one first fixed voltage signal line 21 on the side of the display area AA is divided into two parallel resistors, and by way of example, the first fixed voltage signal line 21 on the left side of the display area AA in fig. 1 is divided into a left upper resistor and a left lower resistor connected in parallel, and the first fixed voltage signal line 21 on the right side of the display area AA in fig. 1 is divided into a right upper resistor and a right lower resistor connected in parallel. Since the total resistance value after the parallel connection is smaller, compared to the comparative example, the embodiment of the present application can reduce the resistance of the first fixed voltage signal line 21, thereby reducing the voltage Drop (IR Drop) of the first fixed voltage signal line 21, and further improving the luminance uniformity.
In some alternative embodiments, as shown in fig. 5, the first fixed voltage signal line 21 further includes a connection structure 212, the first section 211 and the second section 213 are connected by the connection structure 212, and the first section 211, the second section 213 and the connection structure 212 are a unitary structure. It is understood that the connection structure 212 is the connection between the first section 211 and the second section 213. By providing the connection structure 212, the connection position of the second fixed voltage signal line 22 and the first fixed voltage signal line 21 can be accurately set, and since the first section 211, the second section 213 and the connection structure 212 are an integral structure, it is possible to form in one process, saving process steps.
In some alternative embodiments, the lengths of the first section 211 and the second section 213 in the second direction Y may be equal. That is, the connection structure 212 may be located at an intermediate position of the first fixed voltage signal line 21. Illustratively, the lengths of the first section 211 and the second section 213 in the second direction Y are equal to and greater than the length of the connection structure 212 in the second direction Y, so that the difference in pressure drop across the display panel in the second direction Y can be reduced, thereby further improving the uniformity of display brightness.
In some alternative embodiments, the widths of the first section 211 and the second section 213 in the first direction X may be equal to and smaller than the width of the connection structure 212 in the first direction X, so that the contact area between the connection structure 212 and the second fixed voltage signal line 22 may be increased, and the contact resistance between the connection structure 212 and the second fixed voltage signal line 22 may be reduced.
In some alternative embodiments, the first fixed voltage signal line 21 and the second fixed voltage signal line 22 may be located in different conductive layers. In this way, the widths of the first and second fixed voltage signal lines 21 and 22 can be set larger, thereby further reducing the voltage drops of the first and second fixed voltage signal lines 21 and 22.
In alternative embodiments, the first fixed voltage signal line 21 and the second fixed voltage signal line 22 may be located on the same conductive layer. Thus, the first fixed voltage signal line 21 and the second fixed voltage signal line 22 can be formed simultaneously in the same process step, and the process steps are saved.
Illustratively, the first and second fixed voltage signal lines 21 and 22 are used to transmit fixed voltage signals. For example, the first fixed voltage signal line 21 may be electrically connected to a cathode of a light emitting element of the display panel, and a low level signal (Vss signal) may be transmitted to the cathode through the first fixed voltage signal line 21 and the second fixed voltage signal line 22. For another example, the first fixed voltage signal line 21 may be electrically connected to a reference voltage signal line of the display panel, and a reference voltage signal (Vref signal) may be transmitted to the reference voltage signal line through the first fixed voltage signal line 21 and the second fixed voltage signal line 22, which is not limited in this application.
Fig. 6 shows a schematic cross-sectional view in the direction A-A of fig. 5 for an example. As shown in fig. 6, the display panel 100 may further include a light emitting element 30, the light emitting element 30 being located on the substrate 10. The plurality of light emitting elements 30 are distributed in the display area AA. Each light emitting element 30 includes a first electrode 31, a light emitting layer 32, and a second electrode 32, which are stacked. The first electrode 31 is located on a side of the light emitting layer 32 facing the substrate 10, and the second electrode 32 is located on a side of the light emitting layer 32 facing away from the substrate 10. The first electrode 31 may be an anode and the second electrode 33 may be a cathode. The first fixed voltage signal line 21 is electrically connected to the second electrode 33. The second electrode 33 may be a full-face electrode. The first fixed voltage signal line 21 may be electrically connected to the second electrode 33.
Fig. 7 shows a schematic diagram of the current of fig. 5. The arrows in fig. 7 show the paths of the currents. As shown in fig. 7, after the current enters the display panel, the light emitting layer 32 of the light emitting element 30 is excited to emit light, and according to the principle of minimum resistance, the current flows into the first fixed voltage signal line 21 around the display area AA through the second electrode 33, and the upper and lower currents of the first fixed voltage signal line 21 are converged at the connection structure 212 and enter the second fixed voltage signal line 22, and finally flow into the power supply terminal through the second fixed voltage signal line 22. Since the voltage drop of the first fixed voltage signal line 21 is reduced, and thus the voltage difference of the second electrode 33 supplied to each position through the first fixed voltage signal line 21 is also reduced, uniformity of display luminance is improved.
Fig. 8 is a schematic top view of a display panel according to another embodiment of the disclosure. In other alternative embodiments, as shown in fig. 8, the display panel 100 further includes reference voltage signal lines 60 on the substrate 10, and the plurality of reference voltage signal lines 60 are located in the display area AA, and the plurality of reference voltage signal lines 60 extend along the first direction X and are spaced apart in the second direction Y. The first fixed voltage signal lines 21 may be electrically connected to the respective reference voltage signal lines 60. Since the voltage drop of the first fixed voltage signal line 21 is reduced, and thus the voltage difference of the reference voltage signal lines 60 supplied to the respective positions through the first fixed voltage signal line 21 is also reduced, uniformity of display brightness is improved.
Since both the second electrode 33 and the reference voltage signal line 60 transmit negative voltages, in yet other alternative embodiments, the first fixed voltage signal line 21 may be electrically connected to both the second electrode 33 and the reference voltage signal line 60. That is, the second electrode 33 and the reference voltage signal line 60 may share one power terminal, and the number of power terminals may be reduced, thereby reducing costs.
In some alternative embodiments, referring to fig. 6, the first fixed voltage signal line 21 is electrically connected to the second electrode 33. The first fixed voltage signal line 21 and the second fixed voltage signal line 22 may be located in different conductive layers. In this way, the widths of the first and second fixed voltage signal lines 21 and 22 can be increased as much as possible while the first and second fixed voltage signal lines 21 and 22 are placed in the limited non-display area NA, so as to reduce the resistances of the first and second fixed voltage signal lines 21 and 22.
Illustratively, the first fixed voltage signal line 21 is located on a side of the second fixed voltage signal line 22 facing away from the substrate 10. The front projection of the first fixed voltage signal line 21 onto the substrate 10 overlaps the front projection of the second fixed voltage signal line 22 onto the substrate 10. That is, the first fixed voltage signal line 21 and the second fixed voltage signal line 22 are stacked in a direction perpendicular to the light emitting surface of the display panel, so that the widths of the first fixed voltage signal line 21 and the second fixed voltage signal line 22 can be increased, thereby reducing the resistances of the first fixed voltage signal line 21 and the second fixed voltage signal line 22 and reducing the voltage drops of the first fixed voltage signal line 21 and the second fixed voltage signal line 22.
In some alternative embodiments, as shown in fig. 1 or 5, the display area AA is provided with a first fixed voltage signal line 21 and a second fixed voltage signal line 22 on both sides in the first direction X, and the second electrode 33 is electrically connected to the first fixed voltage signal line 21 on both sides in the first direction X. That is, the second electrode 33 is driven in a bilateral manner, so that the difference of voltage drops of the second electrode 33 in the first direction X can be reduced, and the uniformity of display brightness can be further improved.
In some alternative embodiments, the length of the second fixed voltage signal line 22 in the second direction Y is smaller than the length of the first fixed voltage signal line 21 in the second direction Y. Since the second fixed voltage signal line 22 is connected to the connection structure 212 and the connection structure 212 is located between the first section 211 and the second section 213, it is unnecessary to set the length of the second fixed voltage signal line 22 to be equal to the length of the first fixed voltage signal line 21, so that materials can be saved and costs can be reduced.
In some alternative embodiments, referring to fig. 6, the display panel 100 may further include a third fixed voltage signal line 23, and the first fixed voltage signal line 21 is electrically connected to the second electrode 33 through the third fixed voltage signal line 23. In this embodiment, by providing the stacked fixed voltage signal lines, the first fixed voltage signal line 21 is thickened in the direction perpendicular to the light emitting surface of the display panel, so that the resistance of the first fixed voltage signal line 21 is further reduced, and the voltage drop of the first fixed voltage signal line 21 is further reduced.
Illustratively, the first fixed voltage signal line 21 and the third fixed voltage signal line 23 are located in different conductive layers. The third fixed voltage signal line 23 may be located at a side of the first fixed voltage signal line 21 facing away from the substrate 10. The front projection of the first fixed voltage signal line 21 onto the substrate 10 overlaps with the front projection of the third fixed voltage signal line 23 onto the substrate 10. That is, the first fixed voltage signal line 21 and the third fixed voltage signal line 23 are stacked in a direction perpendicular to the light emitting surface of the display panel, so that the widths of the first fixed voltage signal line 21 and the third fixed voltage signal line 23 can be increased, thereby reducing the resistances of the first fixed voltage signal line 21 and the third fixed voltage signal line 23 and reducing the voltage drops of the first fixed voltage signal line 21 and the third fixed voltage signal line 23.
In some alternative embodiments, the length of the third fixed voltage signal line 23 in the second direction Y is equal to the length of the first fixed voltage signal line 21 in the second direction Y. Since the third fixed voltage signal line 22 is connected to the second electrode 33 and the first fixed voltage signal line 21, the second electrode 33 is a planar electrode, and the lengths of the two electrodes are set equal, it is ensured that the second electrode 33 can be uniformly supplied with voltage.
In some alternative embodiments, please continue to refer to fig. 6, the first fixed voltage signal line 21 may be connected to the third fixed voltage signal line 23 through the first channel H1, the third fixed voltage signal line 23 may be connected to the second electrode 33 through the second channel H2, and the orthographic projection of at least one of the first channel H1 and the second channel H2 on the substrate 10 is in a stripe shape. The first and second channels H1 and H2 are provided as stripe-shaped channels, and the contact area between different signal lines or between the signal lines and the second electrode 33 can be increased, thereby reducing the contact resistance. In addition, the first fixed voltage signal line 21 may be connected to the second fixed voltage signal line 22 through the third channel H3. By way of example, the orthographic projection of the third channel H3 on the substrate 10 may be circular, square, rectangular, elliptical, etc., which is not limited in this application.
In some alternative embodiments, referring still to fig. 6, the display panel 100 further includes a driving device layer 20. The first fixed voltage signal line 21 and the second fixed voltage signal line 22 may be both disposed in the driving device layer 20, and the light emitting element 30 is located on a side of the driving device layer 20 facing away from the substrate 10.
The driving device layer 20 includes a transistor including an active layer B, a gate electrode G, a source electrode S, and a drain electrode D. The gate electrode G, the source electrode S, and the drain electrode D are all disposed insulated from the active layer B. The second fixed voltage signal line 22 may be disposed in the same layer as the source S and the drain D of the transistor, and the second fixed voltage signal line 22 is made of the same material as the source S and the drain D of the transistor. Thus, the second fixed voltage signal line 22, the source electrode S and the drain electrode D can be formed simultaneously in the same process step, so as to reduce the complexity of the process and the cost of the process.
In some alternative embodiments, the third fixed voltage signal line 23 may be disposed in the same layer as the first electrode 31, and the third fixed voltage signal line 23 is the same material as the first electrode 31. Thus, the third fixed voltage signal line 23 and the first electrode 31 can be formed simultaneously in the same process step, so as to reduce the complexity of the process and the cost of the process.
In some alternative embodiments, the first fixed voltage signal line 21 may be located between the source S and drain D of the transistor and the first electrode 31.
Specifically, referring to fig. 6, the driving device layer may further include a capacitor, where the capacitor may include a first electrode plate C1 and a second electrode plate C2, and the first electrode plate C1 and the second electrode plate C2 are insulated and stacked. The driving device layer 20 may include a plurality of insulating layers, and exemplary insulating layers may include a gate insulating layer 241, a capacitor insulating layer 242, an interlayer dielectric layer 243, a first insulating layer 244, and a second insulating layer 245. The gate insulating layer 241 is located between the gate electrode G and the active layer B. The first electrode plate C1 may be disposed in the same layer as the gate electrode G, and the first electrode plate C1 may be formed in the same process step as the gate electrode G using the same conductive material. The capacitor insulating layer 242 is located between the first plate C1 and the second plate C2. The interlayer dielectric layer 243 is located on a side of the capacitor insulating layer 242 facing away from the substrate 10, and the interlayer dielectric layer 243 covers the second plate C2. The source S and the drain D are located at a side of the interlayer dielectric layer 243 facing away from the substrate 10, and are connected to the active layer B through vias. The first insulating layer 244 is located on a side of the interlayer dielectric layer 243 facing away from the substrate 10, and the first insulating layer 244 covers the second fixed voltage signal line 22, the source S, and the drain D. The first fixed voltage signal line 21 is located on a side of the first insulating layer 244 facing away from the substrate 10. The second insulating layer 245 is located on a side of the first insulating layer 244 facing away from the substrate 10, and the second insulating layer 245 covers the first fixed voltage signal line 21. It is understood that the first section 211 and the second section 213 of the first fixed voltage signal line 21 may be disposed insulated from the second fixed voltage signal line 22 by the first insulating layer 244, the first insulating layer 244 is provided with the third channel H3, and the connection structure 212 of the first fixed voltage signal line 21 is connected to the second fixed voltage signal line 22 through the third channel H3. Illustratively, the orthographic projections of the third channel H3, the connection structure 212, and the second fixed voltage signal line 22 on the substrate 10 may overlap.
The display panel may further include a buffer layer 11, a pixel definition layer 40, and an encapsulation layer 50. The buffer layer 11 is located between the driving device layer 20 and the substrate 10. The buffer layer 11 may be an inorganic layer to prevent external moisture from penetrating into the active layer of the transistor. The pixel defining layer 40 and each light emitting element 30 are located on a side of the second insulating layer 245 facing away from the substrate 10. The pixel defining layer 40 defines a plurality of openings K, the openings K are disposed in one-to-one correspondence with the light emitting elements 30, the openings K leak out of the first electrode 31, and the light emitting layer 32 is disposed in the openings. The encapsulation layer 50 is located on a side of each light emitting element 30 facing away from the substrate 10, and covers the pixel defining layer 40. The encapsulation layer 50 may be a thin film encapsulation layer.
The driving device layer 20 may further include a switching layer 311, the first electrode 31 being connected to the switching layer 311 through a via, the switching layer 311 being connected to the source electrode S through a via. In this way, the punching difficulty can be reduced with respect to the first electrode 31 directly connected to the source electrode S through one deep hole.
Illustratively, the switching layer 311 may be disposed on the same layer as the first fixed voltage signal line 21, and the materials of the switching layer 311 and the first fixed voltage signal line 21 may be the same and formed at the same time, so as to reduce the complexity of the process and save the cost. It should be understood that fig. 6 is only an example and is not intended to limit the present application.
Fig. 9 shows a schematic cross-sectional view in the direction B-B of fig. 8 for an example. The same structures in fig. 9 as those in fig. 6 are denoted by the same reference numerals, and will not be described in detail herein. In some alternative embodiments, the first fixed voltage signal line 21 is electrically connected to the reference voltage signal line, and the first fixed voltage signal line 21 and the second fixed voltage signal line 22 are located on the same conductive layer. For example, the first fixed voltage signal line 21, the second fixed voltage signal line 22 and the reference voltage signal line 60 may be located on the same conductive layer, and the materials of the first fixed voltage signal line 21, the second fixed voltage signal line 22 and the reference voltage signal line 60 are the same. Thus, the first fixed voltage signal line 21, the second fixed voltage signal line 22 and the reference voltage signal line 60 can be formed simultaneously in the same process, thereby reducing the complexity of the process and the cost of the process.
For example, the first and second fixed voltage signal lines 21 and 22 and the reference voltage signal line 60 may be located at the same conductive layer as the source S and the drain D of the transistor.
In some alternative embodiments, please continue to refer to fig. 8, the display area AA is provided with a first fixed voltage signal line 21 and a second fixed voltage signal line 22 on both sides in the first direction X, and each reference voltage signal line 60 is connected to the first fixed voltage signal line 21 on both sides in the first direction X. That is, the reference voltage signal line 60 is driven in a double-sided manner, so that the voltage drop difference of the reference voltage signal line 60 in the first direction X can be reduced, and the uniformity of the display brightness can be further improved.
In addition, as shown in fig. 5, the display panel provided in the embodiment of the present application may further include an auxiliary signal line 214, where the auxiliary signal line 214 extends along the first direction X in the non-display area NA and is located at one side of the display area AA in the second direction Y. The auxiliary signal line 214 is connected to the first fixed voltage signal line 21, and the auxiliary signal line 214 and the first fixed voltage signal line 21 may be integrally formed. When the number of the first fixed voltage signal lines 21 is two, the number of the auxiliary signal lines 214 may be two, and the two auxiliary signal lines 214 are connected to the two first fixed voltage signal lines 21 in one-to-one correspondence.
Based on the same inventive concept, as shown in fig. 10, the embodiment of the present application further provides a display device. The display device includes the display panel 1000 provided in any embodiment of the present application, and may further include a backlight module and other structures, which are not described herein. In this embodiment, the display device may be a mobile phone, and in other optional embodiments of the present application, the display device may also be any device having a display function, such as a tablet computer, a notebook, or a display.
Since the display device 1000 includes the display panel 100 according to any one of the foregoing embodiments, the display device 1000 has the advantages of the display panel 100 according to any one of the foregoing embodiments, and will not be described in detail herein.
These embodiments are not all details described in detail in accordance with the embodiments described hereinabove, nor are they intended to limit the application to the specific embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various modifications as are suited to the particular use contemplated. This application is to be limited only by the claims and the full scope and equivalents thereof.
Claims (12)
1. A display panel having a display area and a non-display area distributed around at least a portion of the display area, the display panel comprising:
a substrate;
a first fixed voltage signal line on the substrate and located in a non-display region of at least one side of the display region in a first direction, the first fixed voltage signal line extending in a second direction intersecting the first direction, the first fixed voltage signal line including a first section and a second section connected to each other;
the second fixed voltage signal line is positioned on the substrate, one end of the second fixed voltage signal line is connected with the joint of the first section and the second section, and the other end of the second fixed voltage signal line is electrically connected with the power end of the display panel;
the light-emitting elements are positioned on the substrate, the light-emitting element arrays are distributed in the display area, and each light-emitting element comprises a first electrode, a light-emitting layer and a second electrode which are stacked;
the first fixed voltage signal line is electrically connected with the second electrode, the first fixed voltage signal line is electrically connected with the power supply end of the display panel through the second fixed voltage signal line, and the first fixed voltage signal line is not directly electrically connected with the power supply end through the end part of the first fixed voltage signal line;
the first fixed voltage signal line further comprises a connecting structure, the first section and the second section are connected through the connecting structure, and the widths of the first section and the second section in the first direction are equal and smaller than the widths of the connecting structure in the first direction.
2. The display panel of claim 1, wherein the first segment, the second segment, and the connecting structure are a unitary structure.
3. The display panel of claim 2, wherein the first and second segments are equal in length in the second direction and greater than the length of the connection structure in the second direction.
4. The display panel of claim 1, wherein the first fixed voltage signal line is located on a side of the second fixed voltage signal line facing away from the substrate, and wherein an orthographic projection of the first fixed voltage signal line on the substrate overlaps an orthographic projection of the second fixed voltage signal line on the substrate.
5. The display panel of claim 4, wherein a length of the second fixed voltage signal line in the second direction is less than a length of the first fixed voltage signal line in the second direction.
6. The display panel of claim 4, further comprising a third fixed voltage signal line, the first fixed voltage signal line being electrically connected to the second electrode through the third fixed voltage signal line, the third fixed voltage signal line being located on a side of the first fixed voltage signal line facing away from the substrate, and an orthographic projection of the first fixed voltage signal line on the substrate overlapping an orthographic projection of the third fixed voltage signal line on the substrate.
7. The display panel according to claim 6, wherein the third fixed voltage signal line is provided in the same layer as the first electrode, and wherein the third fixed voltage signal line is made of the same material as the first electrode.
8. The display panel according to claim 6, wherein a length of the third fixed voltage signal line in the second direction is equal to a length of the first fixed voltage signal line in the second direction.
9. The display panel according to claim 6, wherein the first fixed voltage signal line is connected to the third fixed voltage signal line through a first channel, the third fixed voltage signal line is connected to the second electrode through a second channel, and an orthographic projection of at least one of the first channel and the second channel on the substrate is in a stripe shape.
10. The display panel of any one of claims 1-8, further comprising a drive device layer, wherein the first and second fixed voltage signal lines are each disposed on the drive device layer, and wherein the light emitting element is located on a side of the drive device layer facing away from the substrate;
the driving device layer includes a transistor including a gate, a source, and a drain, the second fixed voltage signal line is disposed in the same layer as the source and the drain of the transistor, and the second fixed voltage signal line is the same material as the source and the drain of the transistor.
11. The display panel of claim 1, further comprising:
the reference voltage signal lines are positioned on the substrate, the plurality of reference voltage signal lines are positioned in the display area, extend along the first direction and are distributed at intervals in the second direction;
the first fixed voltage signal line is electrically connected with the reference voltage signal line, the first fixed voltage signal line, the second fixed voltage signal line and the reference voltage signal line are positioned on the same conductive layer, and materials of the first fixed voltage signal line, the second fixed voltage signal line and the reference voltage signal line are the same.
12. A display device comprising the display panel according to any one of claims 1 to 11.
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