CN112837256B - Circuit system and detection method for Harris corner detection - Google Patents
Circuit system and detection method for Harris corner detection Download PDFInfo
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- G06T2207/20112—Image segmentation details
- G06T2207/20164—Salient point detection; Corner detection
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Abstract
The application discloses a circuit system and a detection method for Harris corner detection, which are used for solving the problem of low management efficiency of a line cache module. The circuit system comprises: the line cache module is used for dividing the received input image by single-line image information and storing the single-line image information into a plurality of cache blocks in the line cache module; the window generation module is used for reading the cached image information in a preset mode, and carrying out storage processing of a preset format on the read or received information to obtain rectangular window data; the partial guide calculation module is used for receiving first rectangular window data corresponding to the cached image information, and carrying out parallel partial guide operation on the first rectangular window data in a row unit to obtain horizontal partial guide data and vertical partial guide data; the corner response module is used for calculating corner response values in parallel to obtain a plurality of corner response values, so that the extremum suppression module performs maximum suppression processing on second rectangular window data corresponding to the corner response values to determine corner values.
Description
Technical Field
The application relates to the technical field of circuit design, in particular to a circuit system and a detection method for Harris corner detection.
Background
In the prior art, angular point detection plays an important role in scenes related to image processing such as target recognition, target tracking and the like, and the Harris angular point detection algorithm is a signal-based point feature extraction algorithm, so that the method is superior to other angular point detection algorithms in the aspect of processing noisy images, and is widely focused by people.
However, in the existing Harris corner detection algorithm, due to the large calculation amount, a plurality of line cache units need to be set in circuit design, and as the resolution of the processed image increases, the area consumed by the line cache increases more and more, so that the management efficiency of the line cache units in the prior art is lower.
Disclosure of Invention
The embodiment of the application provides a circuit system for detecting Harris corner points and a method for detecting the corner points, which are used for solving the technical problem of low management efficiency of a line cache unit in the prior art.
In a first aspect, there is provided circuitry for Harris corner detection, the circuitry comprising: the system comprises a line cache module, a window generation module, a partial guide calculation module, a corner response module and an extremum suppression module, wherein:
the line buffer module is used for receiving an input image, dividing the input image into a plurality of buffer blocks in the line buffer module according to single-line image information and storing the single-line image information into a plurality of buffer blocks, wherein each buffer block in the plurality of buffer blocks correspondingly stores one line of image information;
the window generation module is used for reading the image information cached in the line cache module in a preset mode, and carrying out storage processing on the read or received information in a preset format to obtain rectangular window data;
the partial guide calculation module is used for receiving first rectangular window data corresponding to the cached image information, and carrying out parallel partial guide operation on the first rectangular window data in a row unit to obtain horizontal partial guide data and vertical partial guide data which are output in a parallel mode;
the corner response module is used for calculating corner response values in parallel to obtain a plurality of corner response values, so that the extremum suppression module performs maximum suppression processing on second rectangular window data corresponding to the corner response values to determine corner values.
In a possible implementation manner, the preset manner is that the window generating module reads a single line of cached images cached in the plurality of cache blocks, and simultaneously reads single line image information to be cached.
In one possible implementation, the window generation module processes the read or received information through a cascaded pipeline structure of a line number setting corresponding to the information, so as to output rectangular window data in a predetermined format.
In a possible implementation manner, the circuit system further includes a gaussian filtering module, where the gaussian filtering module is configured to perform gaussian filtering processing on third rectangular window data corresponding to the horizontal partial derivative data and the vertical partial derivative data output in a parallel manner after being processed by the partial derivative calculating module, and send the data after gaussian filtering processing to the corner response module.
In a possible implementation manner, the gaussian filtering module includes a plurality of gaussian filtering units to process the third rectangular window data in parallel.
In a second aspect, a detection method is provided and applied to a circuit system for Harris corner detection, where the circuit system includes a line buffer module, a window generation module, a bias guide calculation module, a corner response module, and an extremum suppression module, and the method includes:
receiving input image information, and caching the image information into a plurality of cache blocks in the line cache module by dividing the image information into a single line;
reading the image information cached in the line cache module in a preset mode, and carrying out storage processing of a preset format on the cached image to obtain first rectangular window data;
performing parallel partial derivative operation on the first rectangular window data in a row unit to obtain horizontal partial derivative data and vertical partial derivative data which are output in a parallel mode;
carrying out storage processing of a preset format on the horizontal partial derivative data and the vertical partial derivative data which are output in a parallel mode to obtain second rectangular window data, and calculating corner response values in parallel according to the second rectangular window data to obtain a plurality of corner response values;
and carrying out storage processing of a preset format on the plurality of corner response values to obtain third rectangular window data, and carrying out maximum value suppression processing on the third rectangular window data to determine corner values.
In a possible implementation manner, the reading the image information cached in the line cache module in a preset manner specifically includes:
and reading a single line of cached images cached in the plurality of cache blocks, and simultaneously reading single line of image information to be cached.
In one possible embodiment, the predetermined format storage process includes:
and processing the read or received information through a cascade pipeline structure with the row number set corresponding to the information so as to output rectangular window data in a preset format.
In a possible implementation manner, if the circuit system further includes a gaussian filter module, after obtaining the second rectangular window data, the method further includes:
and carrying out Gaussian filtering processing on the second rectangular window data to obtain the data after Gaussian filtering processing.
In one possible embodiment, the method further comprises:
and carrying out parallel calculation on the Gaussian filtered data to obtain a plurality of corner response values corresponding to the Gaussian filtered data.
The technical scheme provided by the embodiment of the application at least brings the following beneficial effects:
in the embodiment of the application, the line buffer module is divided into buffer blocks, and the input image information is stored into a single buffer block in a single line, so that the image information buffered in a single line can be centrally stored and managed, the management efficiency of the line buffer unit can be improved, the bias guide calculation module, the corner response module and the extremum suppression module are provided with a plurality of parallel processing subunits, and the window generation module forms a circuit system for the Harris corner detection algorithm, so that the input image is input into the circuit system for processing, the corner value is finally obtained, and the data of the line buffer module is read only once, thereby reducing the use of logic resources.
Specifically, the specific processing procedure of the corner detection method is as follows: the line buffer module is used for dividing buffer blocks, and input image information is stored in a single buffer block in a single line. Further, the window generation module reads the image information cached in the line cache module in a preset mode, and stores the cached image information in a preset format to obtain first rectangular window data; and performing partial derivative operation on the first rectangular window data by the partial derivative calculation module to obtain horizontal partial derivative data and vertical partial derivative data which are output in a parallel mode, so that the window generation module processes the horizontal partial derivative data and the vertical partial derivative data which are output in the parallel mode to obtain second rectangular window data, the corner response module calculates and obtains a plurality of corner response values on the second rectangular window data, and the extremum suppression module processes the processed plurality of corner response values to obtain corner values.
That is, in the embodiment of the present application, since the cache blocks in the line cache module are centrally stored and managed, and the offset calculation module, the corner response module, and the extremum suppression module are provided with a plurality of parallel processing subunits, the number of line cache units can be effectively reduced, and particularly when a high-resolution image is processed, there is a large area advantage, that is, no line cache unit is required to be added, so that corner detection can be rapidly implemented.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application and do not constitute an undue limitation on the application.
FIG. 1 is a schematic diagram of a prior art circuit caching system;
FIG. 2 is a schematic diagram of circuitry for a Harris corner detection algorithm, as shown in embodiments of the present application;
FIG. 3 is a schematic diagram illustrating a process of caching an image by a line caching module according to an embodiment of the present application;
fig. 4 is a schematic diagram of a window generation module processing information according to an embodiment of the present application;
FIG. 5 is another schematic diagram of circuitry for a Harris corner detection algorithm shown in an embodiment of the present application;
FIG. 6 is a schematic diagram illustrating a calculation process of a partial derivative calculation module according to an embodiment of the present application;
fig. 7 is a flow chart of a detection method according to an embodiment of the present application.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the present application more apparent, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure. Embodiments and features of embodiments in this application may be combined with each other arbitrarily without conflict. Also, while a logical order is depicted in the flowchart, in some cases, the steps depicted or described may be performed in a different order than presented herein.
The term "comprising" in the description of the present application and the claims and in the above figures, as well as any variants thereof, is intended to cover non-exclusive protection. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.
It should be noted that the terms "first," "second," and the like in the description and claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that embodiments of the present application described herein may be implemented in sequences other than those illustrated or otherwise described herein. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present application as detailed in the accompanying claims.
As described above, the Harris corner detection in the prior art requires a plurality of line buffer units in circuit design because of its algorithm characteristics, and the area consumed by line buffer increases with the increase of the resolution of the processed image.
Specifically, referring to fig. 1, in the prior art, the setting of the line buffer unit is a distributed setting, and the existing window generator can only read the information of the 3 line buffer, and after performing the partial derivative calculation on the information of the 3 line buffer, the data after the partial derivative calculation is further required to be stored in the line buffer module of the distributed storage, and then the window generator reads the information again, and performs the subsequent processing, so that the management efficiency of the line buffer is lower, and more circuit area is required.
In view of this, the application provides a circuit system for Harris corner detection algorithm, through the system can be aimed at Harris algorithm characteristic, provides novel inside line buffer memory module and is about to input image and carry out centralized buffer memory, combines multirow window generation module and parallel circuit design again, can effectively reduce the quantity of line buffer memory unit to improve the management efficiency of line buffer memory unit.
The following describes the technical scheme provided by the embodiment of the application with reference to the attached drawings.
Referring to fig. 2, an embodiment of the present application provides a circuit system for Harris corner detection algorithm, and a structural block diagram of the circuit system is shown in fig. 2.
Referring to fig. 2, the circuit system includes a line buffer module, a window generation module, a partial derivative calculation module, a corner response module, a gaussian filter module, and an extremum suppression module.
In this embodiment of the present application, a line buffer module is configured to receive an input image, divide the input image with single line image information, and store the divided image in a plurality of buffer blocks in the line buffer module, where each buffer block in the plurality of buffer blocks correspondingly stores a line of image information; the window generation module is used for reading the image information cached in the line cache module in a preset mode, and carrying out storage processing on the read or received information in a preset format to obtain rectangular window data; the partial guide calculation module is used for receiving first rectangular window data corresponding to the cached image information, and carrying out parallel partial guide operation on the first rectangular window data in a row unit to obtain horizontal partial guide data and vertical partial guide data which are output in a parallel mode; the corner response module is used for calculating corner response values in parallel to obtain a plurality of corner response values, so that the extremum suppression module performs maximum suppression processing on second rectangular window data corresponding to the corner response values to determine corner values.
Further, the circuit system in the application further comprises a gaussian filtering module, wherein the gaussian filtering module is used for performing gaussian filtering processing on the third rectangular window data corresponding to the horizontal partial derivative data and the vertical partial derivative data which are processed by the partial derivative calculating module and output in a parallel mode, and sending the data after gaussian filtering processing to the corner response module.
In this embodiment of the present application, the line buffer module includes a read-write control unit and a buffer unit including a plurality of buffer blocks, and each buffer block may correspond to buffer line map information. In a specific implementation, the cache unit may use SRAM (static random access memory ), for example, the cache unit is composed of six SRAMs, and of course, the cache unit may also be composed of seven SRAMs, which is not limited in the embodiment of the present application.
In this embodiment, when the read-write control unit in the line buffer module performs read-write control on the buffer units in the line buffer module, when the input image buffer unit is not fully written with the buffer blocks, the read-write control unit may sequentially write the image buffer units into the buffer blocks of the buffer units according to the single-line division sequence of the input image until the buffer blocks of the buffer units are fully written. When the buffer block of the buffer unit is full, if a new line of data is input, the read-write control module can read the multiple lines of image data buffered in the buffer block, read the new line of data at the same time, and output the read data to the window generation module at the same time, meanwhile, the new line of data can be written into the first buffer block, in this way, the next acquired multiple lines of image information can be made to comprise the new line of data, so that the buffer processing of the whole frame of image is completed.
Referring to fig. 3, taking a buffer unit consisting of six buffer blocks as an example, a schematic diagram of buffered information of a line buffer module in the embodiment of the present application is provided, and in a specific implementation process, a read-write control unit in the line buffer module performs read-write control on the buffer unit in the line buffer module, and when the buffer unit is not full of six lines of data, the read-write control unit sequentially writes the read-write control information into the buffer unit according to a single line division sequence of an input image until the buffer unit is full of six lines of data. When the buffer unit is full of six lines of data, namely, can be correspondingly understood as LineN-n+5 in fig. 3, wherein N is a positive integer greater than or equal to 1, when linen+6 data is input, the read-write control module can read LineN-n+ 5 data, output seven lines of data of LineN-n+ 6 to the window generation module according to columns, and at the same time, write linen+6 data into a buffer block which is originally written with LineN image information, namely, when linen+1-n+ 6 data is read, complete linen+1-n+ 6 data can be obtained, and then input images are sequentially buffered in such a way, so that the buffer processing of the input whole frame of images can be completed.
In this embodiment of the present application, after the buffer blocks included in the buffer units in the line buffer module are buffered by the input image, the window generating module may read a single line of buffer images buffered in a plurality of buffer blocks and simultaneously read single line image information to be buffered, and specifically, the predetermined line number corresponds to the number of buffer blocks in the line buffer module, for example, may simultaneously read six lines of buffer images by columns and simultaneously read data of a seventh line of buffer image.
In this embodiment of the present application, when the window generating module reads the image information, a specific processing manner may be to process the read image information through a cascaded pipeline structure set by a line number corresponding to the image information, so as to output rectangular window data in a predetermined format. In a specific implementation process, when the window generation module reads seven rows of image information, a cascade pipeline structure is adopted in a register corresponding to each row, and data of a 7*3 window can be output in each clock cycle. Specifically, referring to fig. 4, fig. 4 is a schematic diagram of information processing performed by the window generating module in the embodiment of the present application.
In a specific implementation process, after the window generation module receives the horizontal partial guide data and the vertical partial guide data input by the partial guide calculation module, if the partial guide calculation module includes five parallel partial guide calculation units, the window generation module may store five-line data into the register array, and each line of corresponding registers adopts a cascaded pipeline structure, and each clock cycle outputs data of 5*3 windows.
In a specific implementation process, after the window generating module receives the data sent by the corner response module, if the corner response module includes three corner response operation processing units, the window generating module may store the received three rows of information into the register array, where the registers corresponding to each row adopt a cascaded pipeline structure, and output the data of the 3*3 window in each clock cycle.
It should be noted that, in the embodiment of the present application, the window generating module may be understood as a window generator, and the pipeline structure and the specific processing manner adopted by the registers of each row in the window generating module that are in cascade connection may be understood as the same or similar manner, and reference may be made to the schematic diagram of fig. 4, which is not repeated herein.
For the sake of understanding the circuit system provided in the present application, a specific example is adopted to explain the following, referring to fig. 5, specifically, for example, harris corner detection of 3*3 input templates may be taken, when the input image L is written into the line buffer module in a line manner, and six SRAMs are set in the line buffer module in total.
When six lines of images are cached in the line caching module, the window generator 1 in the window generating module may read the six lines of images by columns and read data of a seventh line adjacent to the sixth line at the same time. Then, the window generator 1 outputs the seven read lines of images to the partial conductance calculation module according to a 7*3 rectangular window after storing the seven read lines of images by an internal 7*3 register array.
In a specific implementation process, the partial derivative calculation module adopts a pipeline design, and can calculate the partial derivative Ix in the X direction and the partial derivative Iy in the Y direction on input 7*3 data. The specific processing procedure may be shown in fig. 6, where the partial derivative calculation module may be divided into 5 parallel partial derivative calculation units (i.e. the partial derivative calculation unit 1, the partial derivative calculation unit 2, the partial derivative calculation unit 3, the partial derivative calculation unit 4, and the partial derivative calculation unit 5 in fig. 6), calculate partial derivatives of 5 3*3 arrays, and output Ix and Iy of 5 rows of images in parallel, i.e. ix_0/iy_0 in fig. 6; ix_1/Iy_1; ix_2/Iy_2; ix_3/Iy_3; ix_4/Iy_4.
Further, the window generator 2 in the window generating module may receive the 5 lines of data output by the partial derivative calculating module, and convert the data into the rectangular window data of 5*3, so as to output the data to the gaussian filtering module, where the gaussian filtering module longitudinally divides the input 5*3 window into 3 3*3 to perform gaussian filtering processing, and specifically, the gaussian filtering module may set three gaussian filtering units, so as to process the data in parallel, and finally output three lines of gaussian filtered data (such as Ix 2/Iy 2/Ixy 2 in fig. 5).
Then the corner response module can calculate the response R of the corner for three rows of data, input the R values of the three rows of data into the window generator 3 in the window generation module after parallel calculation, then can generate the R rectangular window of 3*3, calculate the maximum value of the corner by the extremum suppression module, and finally calculate the corner and output.
The window generation module, the partial guide calculation module, the Gaussian filter module, the corner response module and the extremum suppression module in the circuit system provided by the application all adopt pipeline design, and the partial guide calculation module, the Gaussian filter module and the corner response module all adopt parallel design, so that data of multiple rows can be calculated and output simultaneously.
The line cache module provided by the application is used for carrying out centralized management on the cache units, and combining the multi-line window generation module, the parallel partial guide calculation module, the Gaussian filter module and the corner response module, the minimum number of the line cache units can be realized, and then the management efficiency of the line cache units can be improved.
In addition, as shown in multiple tests of the applicant of the present application, taking a corner detection window of 3x3 as an example, harris corner detection can be achieved only by using 6 lines of input image buffer units, compared with a distributed line buffer unit design, such as the structural design of fig. 1, that is, 9 line buffer units are needed in the prior art, and the line buffer module provided in the embodiment of the present application can reduce 3 line buffer units. The area effect of the line cache units is particularly obvious in images with larger resolution, such as 1080p high-definition images, each cache unit needs to store 1920 image pixels, and the method provided by the application only uses 6 SRAM (static random Access memory) with corresponding size as the line cache unit, so that 3 SRAM with the same size can be saved compared with the prior art, the cost can be saved, and the management of the line cache units can be improved.
Based on the same inventive concept, the application also provides a detection method applied to the aforementioned circuit system for the Harris corner detection algorithm, wherein the circuit system comprises a line buffer module, a window generation module, a bias guide calculation module, a corner response module and an extremum suppression module, and the method is shown in fig. 7, and is specifically described as follows.
Step 701: receiving input image information, caching the image information into a plurality of cache blocks in a line cache module by dividing the image information into a single line;
step 702: reading the image information cached in the line cache module in a preset mode, and carrying out storage processing of a preset format on the cached image to obtain first rectangular window data;
step 703: performing parallel partial derivative operation on the first rectangular window data in a row unit to obtain horizontal partial derivative data and vertical partial derivative data which are output in a parallel mode;
step 704: storing the horizontal partial derivative data and the vertical partial derivative data which are output in a parallel mode in a preset format to obtain second rectangular window data, and calculating corner response values in parallel according to the second rectangular window data to obtain a plurality of corner response values;
step 705: and carrying out storage processing on the plurality of corner response values in a preset format to obtain third rectangular window data, and carrying out maximum value suppression processing on the third rectangular window data to determine corner values.
In a possible implementation manner, the reading the image information cached in the line cache module in a preset manner specifically includes:
and reading a single line of cached images cached in the plurality of cache blocks, and simultaneously reading single line of image information to be cached.
In one possible embodiment, the predetermined format storage process includes:
and processing the read or received information through a cascade pipeline structure with the row number set corresponding to the information so as to output rectangular window data in a preset format.
In a possible implementation manner, if the circuit system further includes a gaussian filter module, after obtaining the second rectangular window data, the method further includes:
and carrying out Gaussian filtering processing on the second rectangular window data to obtain the data after Gaussian filtering processing.
In one possible embodiment, the method further comprises:
and carrying out parallel calculation on the Gaussian filtered data to obtain a plurality of corner response values corresponding to the Gaussian filtered data.
It will be apparent to those skilled in the art that embodiments of the present disclosure may be provided as a method, system, or computer program product. Accordingly, the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present disclosure may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, magnetic disk storage, optical storage, and the like) having computer-usable program code embodied therein.
The present disclosure is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the disclosure. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims and the equivalents thereof, the present application is intended to cover such modifications and variations.
Claims (10)
1. Circuitry for Harris corner detection algorithm, the circuitry comprising: the system comprises a line cache module, a window generation module, a partial guide calculation module, a corner response module and an extremum suppression module, wherein:
the line buffer module is used for receiving an input image, dividing the input image into a plurality of buffer blocks in the line buffer module according to single-line image information, and storing the single-line image information into a plurality of buffer blocks, wherein each buffer block in the plurality of buffer blocks correspondingly stores one line of image information;
the window generation module is used for reading the image information cached in the line cache module in a preset mode, and carrying out storage processing on the read or received information in a preset format to obtain rectangular window data;
the partial guide calculation module is used for receiving first rectangular window data obtained by the window generation module through carrying out storage processing on the cached image information in a preset format, carrying out parallel partial guide operation on the first rectangular window data in a row unit to obtain horizontal partial guide data and vertical partial guide data which are output in a parallel mode, and inputting the horizontal partial guide data and the vertical partial guide data which are output in the parallel mode into the window generation module;
the corner response module is used for calculating corner response values in parallel according to the second rectangular window data to obtain a plurality of corner response values; inputting the plurality of corner response values to the window generation module; the second rectangular window data are obtained by the window generation module through carrying out storage processing on the horizontal partial derivative data and the vertical partial derivative data which are output in a parallel mode in a preset format;
the extremum suppression module is used for receiving third rectangular window data obtained by the window generation module through carrying out storage processing of a preset format on the plurality of corner response values, and carrying out maximum suppression processing on the third rectangular window data so as to determine corner values.
2. The circuit system of claim 1, wherein the preset manner is that the window generation module reads a single line of buffered images buffered in the plurality of buffered blocks and simultaneously reads single line image information to be buffered.
3. The circuit system of claim 1, wherein the window generation module processes the read or received information through a cascaded pipeline structure of line numbers corresponding to the information to output rectangular window data in a predetermined format.
4. The circuitry of claim 1, further comprising a gaussian filter module configured to perform gaussian filter processing on the second rectangular window data and send the gaussian filtered data to the corner response module.
5. The circuitry of claim 4, wherein the gaussian filter module comprises a plurality of gaussian filter units to process the second rectangular window data in parallel.
6. A detection method, characterized in that it is applied to a circuit system for Harris corner detection algorithm, the circuit system includes a line buffer module, a window generation module, a bias guide calculation module, a corner response module, and an extremum suppression module, the method includes:
the line cache module receives input image information, divides the image information into a plurality of cache blocks in the line cache module according to single-line image information and stores the single-line image information;
the window generation module reads the image information cached in the line cache module in a preset mode, and stores the cached image information in a preset format to obtain first rectangular window data;
the partial derivative calculation module carries out parallel partial derivative operation on the first rectangular window data in a row unit to obtain horizontal partial derivative data and vertical partial derivative data which are output in a parallel mode, and the horizontal partial derivative data and the vertical partial derivative data which are output in the parallel mode are input into the window generation module;
the window generation module performs storage processing of a preset format on the horizontal partial derivative data and the vertical partial derivative data which are output in a parallel mode to obtain second rectangular window data;
the corner response module calculates corner response values in parallel according to the second rectangular window data, obtains a plurality of corner response values, and inputs the corner response values to the window generation module;
the window generation module stores the plurality of corner response values in a preset format to obtain third rectangular window data;
and the extremum suppression module performs maximum suppression processing on the third rectangular window data to determine corner values.
7. The method of claim 6, wherein the window generating module reads the image information cached in the line caching module in a preset manner, and specifically includes:
and the window generation module reads the single-line cached images cached in the plurality of cached blocks and simultaneously reads the single-line image information to be cached.
8. The method of claim 6, wherein the window generation module performs a predetermined format storage process comprising:
and the window generation module processes the read or received information through a cascade pipeline structure arranged according to the line number corresponding to the information so as to output rectangular window data in a preset format.
9. The method of claim 6, wherein after obtaining the second rectangular window data if the circuitry further includes a gaussian filter module, the method further comprises:
and carrying out Gaussian filtering processing on the second rectangular window data to obtain the data after Gaussian filtering processing.
10. The method of claim 9, wherein the method further comprises:
and carrying out parallel calculation on the Gaussian filtered data to obtain a plurality of corner response values corresponding to the Gaussian filtered data.
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