CN112821961B

CN112821961B - Underwater electric field communication system

Info

Publication number: CN112821961B
Application number: CN202011607733.3A
Authority: CN
Inventors: 胡桥; 余雷; 续丹; 赵振轶; 冯兴龙; 孙帅帅
Original assignee: Xian Jiaotong University
Current assignee: Xian Jiaotong University
Priority date: 2020-12-29
Filing date: 2020-12-29
Publication date: 2022-07-12
Anticipated expiration: 2040-12-29
Also published as: CN112821961A

Abstract

The invention discloses an underwater electric field communication system, which adopts a transmitting circuit, a receiving circuit and a logic controller to transmit and receive signals, and is used for outputting a path of PWM wave carrier signal and a path of UART serial port transmitting signal to a water channel through the transmitting circuit and amplifying the output signal; the receiving circuit is used for receiving signals from a water channel, amplifying the received signals and transmitting the signals to the logic controller, the receiving circuit forwards and backwards puts weak signals with wide dynamic range to the logic controller, the weak signals are input to the logic controller for digital filtering through a linear accumulation average digital filtering method, then signal restoration and restoration are carried out through a shaping method, the restored signals are normalized to obtain original binary baseband signals, the original binary baseband signals are fed back to the transmitting circuit for motion control, and the communication capacity of the underwater communication system is improved.

Description

Underwater electric field communication system

Technical Field

The invention relates to the field of underwater electric field communication, in particular to an underwater electric field communication system.

Background

Many mineral resources and abundant biological resources are stored in the ocean, and the ocean has huge economic benefit value for the development of the human society. Until now, mankind has used various tools to search for oceans, but still only one tenth of the ocean resources of the earth have been searched, and most of the ocean resources are unknown. Underwater communication is particularly important.

Because the underwater signal attenuation is serious and the position of the underwater robot changes in real time, the underwater communication signal is weak, the dynamic change range is wide, and the magnitude order of the fourth power of ten can be reached. Therefore, it is urgently needed to develop a long-distance and low-bit-error-rate underwater communication system.

Disclosure of Invention

The invention aims to provide an underwater electric field communication system to overcome the defects of the prior art.

In order to achieve the purpose, the invention adopts the following technical scheme:

an underwater electric field communication system comprises a transmitting circuit, a receiving circuit and a logic controller; the transmitting circuit is used for outputting a path of PWM wave carrier signal and a path of UART serial port transmitting signal to a water channel and amplifying the output signal; the receiving circuit is used for receiving signals from a water channel and amplifying the received signals and transmitting the amplified signals to the logic controller, the logic controller is used for carrying out digital filtering on the amplified signals through a linear accumulation average digital filtering method, then carrying out signal restoration and restoration through a shaping method, carrying out normalization processing on the restored signals to obtain original binary baseband signals, and feeding back the original binary baseband signals to the transmitting circuit.

Furthermore, the transmitting circuit comprises a transmitting controller, a modulating circuit, a power amplifying circuit and a transmitting electrode which are connected in sequence; the transmitting controller is used for outputting a path of PWM wave carrier signal and a path of UART serial port transmitting signal to the modulating circuit; the modulation circuit modulates the UART signal by an amplitude-frequency modulation method and inputs the UART signal to the power amplification circuit; the power amplifying circuit amplifies the current and the voltage of the input modulation signal and then sends the amplified current and voltage to the transmitting electrode; the transmitting electrode sends the received amplified signal to the water channel in the form of a pulsed electric field.

Further, the receiving circuit comprises a receiving electrode, an amplifying circuit and an AD conversion circuit which are connected in sequence; the receiving electrode is used for receiving pulse electromotive force in the water channel and transmitting the pulse electromotive force to the amplifying circuit, the received pulse electromotive force is amplified in the amplifying circuit to reach the minimum identification voltage of the AD converting circuit, and the AD converting circuit converts the received amplified signal into digital quantity to be input to the logic controller.

Further, the amplifying circuit comprises a preceding stage amplifying circuit and a secondary stage amplifying circuit, wherein the preceding stage amplifying circuit amplifies a weak signal sensed by the receiving electrode to reach the minimum identification voltage of the AD conversion circuit; the second-stage amplifying circuit is connected with the logic controller and the AD conversion circuit, and the second-stage amplifying circuit amplifies the output voltage of the first-stage amplifying circuit to the same range through the control of the logic controller and then transmits the amplified voltage to the AD conversion circuit.

Further, the logic controller is used for receiving the digital signal output by the AD conversion circuit, compiling corresponding amplification factors and judging whether the amplitude of the input voltage of the AD conversion circuit meets the requirement, and if not, amplifying the digital signal through the secondary amplification circuit; and restoring and repairing the received signal by adopting a parallel linear accumulation average digital filtering method and a shaping method for the signal meeting the requirement.

Furthermore, the logic controller comprises an amplification factor control module, a linear accumulation module, a shaping module and an envelope demodulation module, wherein the digital signal output by the AD conversion circuit is transmitted to the amplification factor control module, the amplification factor control module is connected to the secondary amplification circuit, the secondary amplification circuit is connected to the shaping module, and the shaping module is connected to the envelope demodulation module.

Furthermore, the compiling envelope module comprises a low-pass filter module, a judgment output module and a baseband signal module which are connected in sequence, the judgment output module is connected with a bit synchronization pulse module, and the shaping module is connected with the low-pass filter module.

Furthermore, the pre-amplifier circuit comprises a pre-operational amplifier, the same-direction input end of the pre-operational amplifier is a Signal input end Signal _ IN, the reverse input end of the pre-operational amplifier is grounded, the external resistor of the pre-operational amplifier is connected with an adjustable resistor R10, the positive power supply electrode of the pre-operational amplifier is connected with one end of a capacitor C24, the other end of the capacitor C24 is grounded, the negative power supply electrode of the pre-operational amplifier is connected with one end of a capacitor C27, and the other end of the capacitor C27 is connected with the external capacitor of the pre-operational amplifier.

Further, the secondary amplifying circuit comprises two cascaded secondary amplifiers, a voltage output end PGA _ IN of the primary amplifying circuit is connected with an input end of one of the secondary amplifiers, the other secondary amplifier is a voltage output end PGA _ OUT of the secondary amplifying circuit, a voltage end of one of the secondary amplifiers is connected with a capacitor C23 and a capacitor C22 IN series, one end of a capacitor C22 is connected with a-VCC end and a DIGITAL end of one of the secondary amplifiers and then grounded, the other end of the capacitor C22 is connected with one end of a capacitor C23 and a VREF end of one of the secondary amplifiers, and the other end of a capacitor C23 is connected with + VCC of one of the secondary amplifiers; one secondary amplifier is connected with a 12V power supply through-VCC and + VCC; the voltage end of the other secondary amplifier is connected with a capacitor C25 and a capacitor C26 in series, one end of a capacitor C26 is connected with the-VCC end of the other secondary amplifier and then grounded, the other end of a capacitor C26 is connected with one end of a capacitor C25 and the VREF end of the other secondary amplifier, and the other end of a capacitor C25 is connected with the + VCC and VREF ends of the other secondary amplifier.

Further, the circuit of the emission controller includes a resistor R7, a resistor R8, an NPN transistor Q1, a PNP transistor Q2, an NPN transistor Q3, and a capacitor C30, wherein one end of the resistor R7 is connected to a base of the NPN transistor Q3, a base of the NPN transistor Q1 and a base of the PNP transistor Q2 are connected to a collector of the NPN transistor Q3, one end of the resistor R8 is connected to a collector of the NPN transistor Q3, the other end of the resistor R8 is connected to a power supply and a collector of the NPN transistor Q1, an emitter of the NPN transistor Q1 and an emitter of the PNP transistor Q2 are connected to an emission anode electrode plate of the emission electrode, and a collector of the PNP transistor Q2 and an emitter of the NPN transistor Q3 are connected to a ground line and to an emission cathode electrode plate of the emission electrode.

Compared with the prior art, the invention has the following beneficial technical effects:

the invention relates to an underwater electric field communication system, which adopts a transmitting circuit, a receiving circuit and a logic controller to transmit and receive signals, and is used for outputting a path of PWM wave carrier signal and a path of UART serial port transmitting signal to a water channel through the transmitting circuit and amplifying the output signal; the receiving circuit is used for receiving signals from a water channel, amplifying the received signals and transmitting the amplified signals to the logic controller, the receiving circuit forwards the weak signals with wide dynamic range, then inputting the weak signals into the logic controller, performing digital filtering on the amplified signals through a linear accumulation average digital filtering method, then performing signal restoration and restoration through a shaping method, performing normalization processing on the restored signals to obtain original binary baseband signals, feeding the original binary baseband signals back to the transmitting circuit for motion control, and effectively improving the communication capacity of the underwater communication system.

Furthermore, through a pulse square wave modulation mode, electronic noise which interferes with cable signals and reduces signal integrity can be greatly reduced, most of underwater acoustic noise can be avoided by using underwater electric field communication, and the signal to noise ratio of underwater communication is favorably improved.

Furthermore, the power amplification circuit adopts NPN and PNP triodes to build a half-bridge amplification circuit, and the voltage difference between the electrode plates is amplified to 12V, so that the emission current of an underwater electric field is increased, and the electric field communication distance is greatly increased.

Furthermore, the pre-stage amplifying circuit amplifies the input weak high-frequency pulse signal, and can obtain extremely small zero drift, thereby perfectly avoiding the distortion after passing through the subsequent amplifying circuit.

Furthermore, the secondary amplifying circuit can use the FPGA to carry out multiple control on the programmable logic amplifier, the amplification factor can be adjusted between 1 and 8000 times, and the voltage is amplified to the same order of magnitude, so that the voltage with the difference of 8000 times in a large range is identified, and the remote large-span dynamic movement between the receiving and transmitting equipment in the communication process can be self-adapted.

Drawings

Fig. 1 is a block diagram of an underwater electric field communication system in an embodiment of the present invention.

Fig. 2 is a circuit diagram of a preceding stage amplification circuit of the underwater electric field communication system in the embodiment of the invention.

Fig. 3 is a secondary amplification circuit diagram of the underwater electric field communication system in the embodiment of the invention.

Fig. 4 is an AD conversion circuit diagram of the underwater electric field communication system in the embodiment of the present invention.

Fig. 5 is a transmission circuit diagram of the underwater electric field communication system in the embodiment of the invention.

In the figure, 1, a transmission controller; 2. a modulation circuit; 3. a power amplification circuit; 4. an emitter electrode; 5. a receiving electrode; 6. a pre-amplifier circuit; 7. a secondary amplification circuit; 8. an AD conversion circuit; 9. a logic controller; 10. a UART serial port communication circuit; 11. an SDRAM storage circuit; 12. a power-down storage module; 13. a JTAG interface; 14. a power management circuit; 15. a clock circuit; 16. a magnification control module; 17. a linear accumulation module; 18. a shaping module; 19. an envelope demodulation module; 20. a low pass filter module; 21. a decision output module; 22. a bit synchronization pulse module; 23. and a baseband signal module.

Detailed Description

The invention is described in further detail below with reference to the accompanying drawings:

the invention is described in detail below with reference to the figures and specific embodiments. The present embodiment is implemented on the premise of the technical solution of the present invention, and a detailed implementation manner and a specific operation process are given, but the scope of the present invention is not limited to the following embodiments.

As shown in fig. 1, an underwater electric field communication system includes a transmitting circuit, a receiving circuit, and a logic controller 9; the transmitting circuit is used for outputting a path of PWM wave carrier signal and a path of UART serial port transmitting signal to a water channel and amplifying the output signal; the receiving circuit is used for receiving signals from the water channel, amplifying the received signals and transmitting the amplified signals to the logic controller 9, the logic controller 9 is used for carrying out digital filtering on the amplified signals through a linear accumulation average digital filtering method, then carrying out signal restoration and restoration through a shaping method, carrying out normalization processing on the restored signals to obtain original binary baseband signals, and feeding the original binary baseband signals back to the transmitting circuit.

The transmitting circuit comprises a transmitting controller 1, a modulating circuit 2, a power amplifying circuit 3 and a transmitting electrode 4 which are connected in sequence; the transmitting controller 1 is used for outputting a path of PWM wave carrier signal and a path of UART serial port transmitting signal to the modulating circuit 2; the modulation circuit 2 modulates the UART signal by an amplitude-frequency modulation method and inputs the UART signal to the power amplification circuit 3; the power amplifying circuit 3 amplifies the current and voltage of the input modulation signal and sends the amplified current and voltage to the transmitting electrode 4; the transmitting electrode 4 sends the received amplified signal in the form of a pulsed electric field into the water channel.

The transmission controller 1 adopts an STM32 controller, the modulation circuit 2 is an ASK modulation circuit, and the logic controller 9 adopts an FPGA logic controller. The emitter electrode 4 includes an emitter cathode electrode plate and an emitter anode electrode plate.

The receiving circuit comprises a receiving electrode 5, an amplifying circuit and an AD conversion circuit 8 which are connected in sequence; the receiving electrode 5 is used for receiving the pulse electromotive force in the water channel and transmitting the pulse electromotive force to the amplifying circuit, the received pulse electromotive force is amplified in the amplifying circuit to reach the minimum identification voltage of the AD converting circuit 8, and the AD converting circuit 8 converts the received and amplified signal into a digital quantity to be input to the logic controller 9.

The amplifying circuit comprises a preceding stage amplifying circuit 6 and a secondary stage amplifying circuit 7, wherein the preceding stage amplifying circuit 6 amplifies a weak signal induced by the receiving electrode 5 to reach the minimum identification voltage of the AD conversion circuit 8; the secondary amplifying circuit 7 is connected with the logic controller 9 and the AD conversion circuit 8, the secondary amplifying circuit 7 amplifies the output voltage of the front stage amplifying circuit 6 to the same range under the control of the logic controller 9, and then transmits the amplified voltage to the AD conversion circuit 8; specifically, the AD conversion circuit 8 converts the analog voltage amplified by the secondary amplification circuit 7 into a digital value, and inputs the digital value into the logic controller 9;

the logic controller 9 is configured to receive the 16-bit digital signal output by the AD conversion circuit 8, compile a corresponding amplification factor, and determine whether the amplitude of the input voltage of the AD conversion circuit 8 meets the requirement, and if not, implement an adaptive amplification function through the amplification factor of the secondary amplification circuit 7; and restoring and repairing the received signal by adopting a parallel linear accumulation average digital filtering method and a shaping method for the signal meeting the requirement.

The logic controller 9 comprises an amplification factor control module 16, a linear accumulation module 17, a shaping module 18 and an envelope demodulation module 19, wherein digital signals output by the AD conversion circuit 8 are transmitted to the amplification factor control module 16, the amplification factor control module 16 is connected to the secondary amplification circuit 7, if the amplification factor of the received digital signals meets the requirement, the digital signals output by the AD conversion circuit 8 are transmitted to the linear accumulation module 17, the digital signals are processed by a linear accumulation average digital filtering method in the linear accumulation module 17 and then transmitted to the shaping module 18, and the shaping module 18 is used for shaping to realize the restoration and restoration of the signals; and transmits the restored and repaired signal to the compiling envelope module 19, and the compiling envelope module 19 performs normalization processing on the restored and repaired signal to obtain an original binary baseband signal.

The compiling envelope module 19 includes a low pass filter module 20, a decision output module 21, a bit synchronization pulse module 22 and a baseband signal module 23, the shaping module 18 is connected to the low pass filter module 20, the restored signal is filtered by the low pass filter module 20, signal normalization processing is performed by the decision output module 21 and the bit synchronization pulse module 22, the baseband signal module 23 is connected to the transmitting controller 1 through the UART serial port communication circuit 10, the normalized data is transmitted to the transmitting controller 1 through the baseband signal module 23 and the UART serial port communication circuit 10, and the transmitting controller 1 performs corresponding motion control.

The logic controller 9 is further connected with an SDRAM memory circuit 11, a power-down memory module 12, a JTAG interface 13, a power management circuit 14 and a clock circuit 15, the SDRAM memory circuit 11 is used for storing digital signals after AD conversion, the JTAG interface 13 is used for providing an interface, the power management circuit 14 is used for providing power, and the clock circuit 15 is used for providing timing information.

As shown IN fig. 2, the pre-amplifier circuit includes a pre-operational amplifier, a Signal input terminal Signal _ IN is a same-direction input terminal of the pre-operational amplifier, a reverse input terminal of the pre-operational amplifier is grounded, an external resistor of the pre-operational amplifier is connected with an adjustable resistor R10, a power supply positive terminal of the pre-operational amplifier is connected with one end of a capacitor C24, the other end of the capacitor C24 is grounded, a power supply negative terminal of the pre-operational amplifier is connected with one end of a capacitor C27, the other end of the capacitor C27 is connected with an external capacitor terminal of the pre-operational amplifier, and an output terminal PGA _ IN of the pre-amplifier circuit; the preceding operational amplifier is preferably an INA128PAG4 instrumentation amplifier with a low zero drift of 50uV less than the minimum identification voltage of the AD conversion circuit 8; as shown IN fig. 2, the Signal input terminal Signal _ IN is connected to the pin 3 of the preceding stage amplifier circuit, the pin 2 of the preceding stage amplifier circuit, one end of the capacitor C24, one end of the capacitor C27 are connected to ground, the other end of the capacitor C27 is connected to the negative pole of the power supply, the other end of the capacitor C24 is connected to the positive pole of the power supply, a 5V power supply is used, the two ends of the adjusting resistor R10 are connected to the pins 1 and 8 of the preceding stage operational amplifier respectively, and the amplification factor of the circuit can be changed by adjusting the resistance value of the resistor R10.

As shown IN fig. 3, the secondary amplifying circuit includes two secondary amplifiers, the secondary amplifier is a programmable gain amplifier, a voltage output terminal PGA _ IN of the pre-stage amplifying circuit is connected to an input terminal of one of the secondary amplifiers, the two secondary amplifiers are cascaded, and the other secondary amplifier is a voltage output terminal PGA _ OUT of the secondary amplifying circuit; the voltage end of one secondary amplifier is connected with a capacitor C23 and a capacitor C22 in series, one end of a capacitor C22 is connected with the-VCC end and the DIGITAL end of one secondary amplifier and then grounded, the other end of a capacitor C22 is connected with one end of a capacitor C23 and the VREF end of one secondary amplifier, and the other end of a capacitor C23 is connected with the + VCC of one secondary amplifier; one secondary amplifier is connected with a 12V power supply through-VCC and + VCC; the voltage end of the other secondary amplifier is connected with a capacitor C25 and a capacitor C26 in series, one end of a capacitor C26 is connected with the-VCC end of the other secondary amplifier and then grounded, the other end of a capacitor C26 is connected with one end of a capacitor C25 and the VREF end of the other secondary amplifier, and the other end of a capacitor C25 is connected with the + VCC and VREF ends of the other secondary amplifier; the two secondary amplifiers adopt a two-piece cascade connection mode of PGA202KP and PGA203KP, so that the amplification factor with wide dynamic range of 1-8000 times is achieved, and the voltage with large dynamic change range caused by sudden distance change between underwater vehicles is adapted. The two secondary amplifier amplification factor control ends PGA _ a0, PGA _ a1, PGA _ a2, and PGA _ A3 are respectively connected to an IO port of the logic controller 9, and by changing the levels of the four ports, real-time control of the secondary amplification circuit 7 factors is achieved.

As shown in fig. 4, the AD conversion circuit ADC conversion chip, the secondary amplifier voltage output terminal, a capacitor C17, a capacitor C18, a capacitor C19, a capacitor C20, a capacitor C21, a resistor R5, and an ADC output port; the ADC conversion chip is an ADS8411, 16-bit single-end AD conversion chip, the precision can reach 62.5uV and can reach 4V at most, a large voltage identification range is achieved, and R5 zero ohm resistors are used for being connected in series with a digital ground and an analog ground.

As shown in fig. 5, the PWM carrier signal and the baseband signal output by the transmission controller pass through the ASK modulation circuit 2, the circuit uses a resistor R6 to be connected in parallel with a diode D1 to output a modulated pulse square wave, and then the modulated pulse square wave is rectified by an SN74LS04NSR not gate to output a perfect pulse square wave, and then the modulated pulse square wave is output through the power amplification circuit 3; the transmitting circuit diagram specifically comprises a resistor R7, a resistor R8, an NPN triode Q1, a PNP triode Q2, an NPN triode Q3 and a capacitor C30, wherein one end of the resistor R7 is connected with the base of the NPN triode Q3, the base of the NPN triode Q1 and the base of the PNP triode Q2 are connected with the collector of the NPN triode Q3, one end of the resistor R8 is connected with the collector of the NPN triode Q3, the other end of the resistor R8 is connected with a power supply and the collector of the NPN triode Q1 and an external boosting power supply, the emitter of the NPN triode Q1 and the emitter of the PNP triode Q2 are connected with an emitting anode electrode plate (such as a P7 interface 1 in FIG. 5), and the collector of the PNP triode Q2 and the emitter of the NPN triode Q3 are connected with an emitting cathode electrode plate (such as a P7 interface 2 in FIG. 5). When the base electrode of the NPN triode Q3 inputs high level 3.3V, the NPN triode Q3 is conducted, the collector electrode of the NPN triode Q3 is low level and is connected with the base electrode of the PNP triode Q2 and approximately equals to the collector electrode voltage of the PNP triode Q2, so the PNP triode Q2 is in a saturation region, the PNP triode Q2 is conducted, the NPN triode Q1 is cut off, and the transmitting anode electrode plate is low level; when the base electrode of the NPN triode Q3 inputs low level 0V, the NPN triode Q3 is cut off, the collector voltage of the NPN triode Q3 is 12V, the collector voltage is connected with the base electrode of the NPN triode Q1 and is approximately equal to the collector level of the NPN triode Q1, so the NPN triode Q1 is in a saturation region, the NPN triode Q1 is conducted, the PNP triode Q2 is cut off, the emitting anode electrode plate is high level 12V, and the two electrode plates are placed in water to generate large current, so that a pulsating electric field is generated. The NPN triode Q1 and the NPN triode Q3 both adopt a high-power Darlington NPN triode TIP 122G; the PNP transistor Q2 employs a high power darlington PNP transistor TIP 127G.

According to the invention, through a pulse square wave modulation mode, the electronic noise which interferes the cable signal and reduces the signal integrity can be greatly reduced, and the underwater electric field communication can be used for avoiding most of the acoustic noise existing underwater, so that the signal to noise ratio of the underwater communication can be improved; the power amplification circuit adopts high-power Darlington NPN and PNP triodes, a half-bridge amplification circuit is built, the pressure difference between the electrode plates is amplified to 12V, the underwater electric field emission current is further improved, and the electric field communication distance is greatly increased. The pre-stage amplifying circuit amplifies the input weak high-frequency pulse signal, and can obtain extremely small zero drift, thereby perfectly avoiding the distortion after passing through the subsequent amplifying circuit; the secondary amplification circuit may use an FPGA to multiply the programmable logic amplifier.

Claims

1. An underwater electric field communication system, comprising a transmitting circuit, a receiving circuit and a logic controller (9); the transmitting circuit is used for outputting a path of PWM wave carrier signal and a path of UART serial port transmitting signal to a water channel and amplifying the output signal; the receiving circuit is used for receiving signals from a water channel and amplifying the received signals and transmitting the amplified signals to the logic controller (9), the logic controller (9) is used for carrying out digital filtering on the amplified signals through a linear accumulation average digital filtering method, then carrying out signal restoration and restoration through a shaping method, carrying out normalization processing on the restored and restored signals to obtain original binary baseband signals, and feeding back the original binary baseband signals to the transmitting circuit; the transmitting circuit comprises a transmitting controller (1), a modulating circuit (2), a power amplifying circuit (3) and a transmitting electrode (4) which are connected in sequence; the transmitting controller (1) is used for outputting a path of PWM wave carrier signal and a path of UART serial port transmitting signal to the modulating circuit (2); the modulation circuit (2) modulates the UART signals by an amplitude-frequency modulation method and then inputs the UART signals to the power amplification circuit (3); the power amplifying circuit (3) amplifies the current and the voltage of the input modulation signal and then sends the amplified current and voltage to the transmitting electrode (4); the transmitting electrode (4) sends the received amplified signal to a water channel in the form of a pulse electric field; the receiving circuit comprises a receiving electrode (5), an amplifying circuit and an AD conversion circuit (8) which are connected in sequence; the receiving electrode (5) is used for receiving pulse electromotive force in a water channel and transmitting the pulse electromotive force to the amplifying circuit, the received pulse electromotive force is amplified in the amplifying circuit to reach the minimum identification voltage of the AD conversion circuit (8), the AD conversion circuit (8) converts the received and amplified signals into digital quantity and inputs the digital quantity to the logic controller (9), the amplifying circuit comprises a preceding stage amplifying circuit (6) and a secondary stage amplifying circuit (7), and the preceding stage amplifying circuit (6) amplifies weak signals sensed by the receiving electrode (5) to reach the minimum identification voltage of the AD conversion circuit (8); the secondary amplifying circuit (7) is connected to the logic controller (9) and the AD conversion circuit (8), the secondary amplifying circuit (7) amplifies the output voltage of the pre-stage amplifying circuit (6) to the same range under the control of the logic controller (9) and then transmits the amplified voltage to the AD conversion circuit (8), the logic controller (9) is used for receiving the digital signal output by the AD conversion circuit (8) and compiling corresponding amplification factors to judge whether the amplitude of the input voltage of the AD conversion circuit (8) meets the requirement, and if the amplitude does not meet the requirement, the amplification factors are amplified through the secondary amplifying circuit (7); the method comprises the steps that a parallel linear accumulation average digital filtering method and a parallel shaping method are adopted for signals meeting requirements to restore and repair received signals, a logic controller (9) comprises an amplification factor control module (16), a linear accumulation module (17), a shaping module (18) and an envelope demodulation module (19), digital signals output by an AD conversion circuit (8) are transmitted to the amplification factor control module (16), the amplification factor control module (16) is connected to a secondary amplification circuit (7), the linear accumulation module (17) is connected to the shaping module (18), the shaping module (18) is connected to the envelope demodulation module (19), the envelope demodulation module (19) comprises a low-pass filter module (20), a judgment output module (21) and a baseband signal module (23) which are sequentially connected, the judgment output module (21) is connected with a bit synchronization pulse module (22), the shaping module (18) is connected to the low-pass filter module (20).

2. The underwater electric field communication system of claim 1, wherein the pre-amplifier circuit comprises a pre-operational amplifier, a Signal input terminal Signal _ IN is a same-direction input terminal of the pre-operational amplifier, a reverse input terminal of the pre-operational amplifier is grounded, an external resistor of the pre-operational amplifier is connected with an adjustable resistor R10, a power supply positive terminal of the pre-operational amplifier is connected with one end of a capacitor C24, the other end of the capacitor C24 is grounded, a power supply negative terminal of the pre-operational amplifier is connected with one end of a capacitor C27, and the other end of the capacitor C27 is connected with an external capacitor of the pre-operational amplifier.

3. The underwater electric field communication system according to claim 1, wherein the secondary amplifying circuit comprises two cascaded secondary amplifiers, a voltage output end PGA _ IN of the primary amplifying circuit is connected with an input end of one of the secondary amplifiers, the other secondary amplifier is a voltage output end PGA _ OUT of the secondary amplifying circuit, a voltage end of one of the secondary amplifiers is connected with a capacitor C23 and a capacitor C22 IN series, one end of the capacitor C22 is connected with a-VCC end and a DIGITAL end of one of the secondary amplifiers and then grounded, the other end of the capacitor C22 is connected with one end of a capacitor C23 and a VREF end of one of the secondary amplifiers, and the other end of the capacitor C23 is connected with + VCC of one of the secondary amplifiers; one secondary amplifier is connected with a 12V power supply through-VCC and + VCC; the voltage end of the other secondary amplifier is connected with a capacitor C25 and a capacitor C26 in series, one end of a capacitor C26 is connected with the-VCC end of the other secondary amplifier and then grounded, the other end of a capacitor C26 is connected with one end of a capacitor C25 and the VREF end of the other secondary amplifier, and the other end of a capacitor C25 is connected with the + VCC and VREF ends of the other secondary amplifier.

4. An underwater electric field communication system as claimed in claim 1, wherein the circuit of the transmission controller includes a resistor R7, a resistor R8, an NPN transistor Q1, a PNP transistor Q2, an NPN transistor Q3, and a capacitor C30, wherein one end of the resistor R7 is connected to the base of the NPN transistor Q3, the base of the NPN transistor Q1 and the base of the PNP transistor Q2 are connected to the collector of the NPN transistor Q3, one end of the resistor R8 is connected to the collector of the NPN transistor Q3, the other end of the resistor R8 is connected to the power supply and the collector of the NPN transistor Q1, the emitter of the NPN transistor Q1 and the emitter of the PNP transistor Q2 are connected to the transmitting anode electrode plate of the transmitting electrode, and the emitters of the PNP transistor Q2 and the NPN transistor Q3 are connected to the ground line and to the transmitting cathode electrode plate of the transmitting electrode.