CN112820726A - Chip packaging structure and preparation method thereof - Google Patents
Chip packaging structure and preparation method thereof Download PDFInfo
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- CN112820726A CN112820726A CN202110407132.6A CN202110407132A CN112820726A CN 112820726 A CN112820726 A CN 112820726A CN 202110407132 A CN202110407132 A CN 202110407132A CN 112820726 A CN112820726 A CN 112820726A
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- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0233—Structure of the redistribution layers
- H01L2224/02331—Multilayer structure
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0233—Structure of the redistribution layers
- H01L2224/02333—Structure of the redistribution layers being a bump
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02381—Side view
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Abstract
The embodiment of the invention provides a chip packaging structure and a preparation method thereof, relating to the technical field of chip packaging, the chip packaging structure comprises a medium layer and a chip packaging module arranged on the medium layer, wherein the chip packaging module comprises a plurality of first storage chips, a logic chip, at least one first heat dissipation block, at least one second heat dissipation block and a plastic packaging layer, the plurality of first storage chips are arranged on the medium layer in a stacking mode, the first heat dissipation block is arranged on the medium layer, the logic chip is arranged on the first heat dissipation block, the second heat dissipation block is arranged on the logic chip, and extends to the surface of the plastic package layer, compared with the prior art, the invention can ensure good heat dissipation effect of the logic chip by arranging the first heat dissipation block and the second heat dissipation block, meanwhile, the stacking of a plurality of chips is realized through the laminated structure of the first storage chip, so that the stacking quantity is increased, and the good heat dissipation effect is ensured.
Description
Technical Field
The invention relates to the technical field of chip packaging, in particular to a chip packaging structure and a preparation method of the chip packaging structure.
Background
With the rapid development of the semiconductor industry, electronic products are miniaturized more and more thinly to meet the requirements of users and the product performance and memory are higher and higher, so that a semiconductor packaging structure adopts a multiple chip stacking (Stack-Die or FOW film mounting) technology to Stack two or more chips in a single packaging structure, thereby realizing the reduction of the packaging volume of the product and the improvement of the product performance. Such stacked products (memory card/storage card) usually have 2 types of chips, a memory storage chip and a control chip, and are packaged in the same substrate unit by stacking, for example: the NAND product requires a large enough product capacity and a large number of stacked layers, and the memory card performance is limited by the number of memory chips and the size of the stacked structure. With the conventional stacked structure, as the number of memory chips increases, the size of the product is larger, and the size of the molding layer is larger, resulting in poorer heat dissipation performance.
Disclosure of Invention
The object of the present invention includes, for example, providing a chip package structure and a method of manufacturing the chip package structure, which can secure a heat dissipation effect while increasing the number of stacks.
Embodiments of the invention may be implemented as follows:
in a first aspect, the present invention provides a chip package structure, including:
a dielectric layer;
the chip packaging module is arranged on the medium layer and comprises a plurality of first storage chips, a logic chip, at least one first radiating block, at least one second radiating block and a plastic packaging layer, the first storage chips are stacked and arranged on the medium layer, the first radiating block is arranged on the medium layer, the logic chip is arranged on the first radiating block and is positioned on one side of the first storage chips, the second radiating block is arranged on the logic chip, the plastic packaging layer is coated on the logic chip, the first radiating block, the second radiating block and the plurality of first storage chips, and the second radiating block extends to the surface of the plastic packaging layer.
In an optional embodiment, a first heat dissipation glue layer is disposed between the first heat dissipation block and the lower side surface of the logic chip, and a second heat dissipation glue layer is disposed between the second heat dissipation block and the upper side surface of the logic chip.
In an optional embodiment, the chip package structure further includes a heat dissipation plate attached to the molding layer, and the heat dissipation plate is connected to the second heat dissipation block.
In an optional embodiment, a third heat dissipation adhesive layer is disposed between the heat dissipation plate and the plastic package layer, and the third heat dissipation adhesive layer extends to a position between the second heat dissipation block and the heat dissipation plate.
In an optional implementation mode, a first electrical connection column is further arranged in the plastic package layer, the first electrical connection column is located between the first storage chips and the logic chip and connected with the dielectric layer, each first conductive layer is arranged on the upper side or the lower side of each first storage chip and connected with the first electrical connection column, and the logic chip is connected with one of the first conductive layers.
In an optional embodiment, a first conductive bump is disposed on an upper side or a lower side of the first memory chip, and the first conductive layer is disposed corresponding to the first conductive bump and connected to the first conductive bump.
In an optional implementation manner, the chip package structure further includes a plurality of second memory chips stacked on the dielectric layer, and the plurality of second memory chips are disposed on a side of the logic chip away from the plurality of first memory chips.
In an optional embodiment, a second electrical connection column is further arranged in the plastic package layer, the second electrical connection column is located between the plurality of second storage chips and the logic chip and connected with the dielectric layer, a second conductive layer is arranged on the upper side or the lower side of each second storage chip, the plurality of second conductive layers are connected with the second electrical connection columns, and the logic chip is connected with one of the second conductive layers.
In an optional embodiment, a second conductive bump is disposed on an upper side or a lower side of each second memory chip, and the second conductive layer is disposed corresponding to the second conductive bump and connected to the second conductive bump.
In an optional embodiment, a first connection pad and a second connection pad are disposed on the dielectric layer, the first electrical connection pad is connected to the first connection pad and electrically connected to the dielectric layer through the first connection pad, and the second electrical connection pad is connected to the second connection pad and electrically connected to the dielectric layer through the second connection pad.
In a second aspect, the present invention provides a method for preparing a chip package structure, for preparing the chip package structure according to the foregoing embodiments, including:
preparing a chip packaging module on a carrier;
arranging a dielectric layer at the bottom side of the chip packaging module;
wherein, the encapsulation module includes a plurality of first memory chip, logic chip, at least one first radiating block, at least one second radiating block and plastic-sealed layer, and is a plurality of the range upon range of setting of first memory chip is in on the dielectric layer, first radiating block sets up on the dielectric layer, logic chip sets up on the first radiating block, and it is a plurality of to be located one side of first memory chip, the second radiating block sets up on the logic chip, the plastic-sealed layer cladding is in logic chip first radiating block second radiating block and a plurality of outside the first memory chip, just the second radiating block extends to the surface of plastic-sealed layer.
The beneficial effects of the embodiment of the invention include, for example:
according to the chip packaging structure provided by the embodiment of the invention, the plurality of first storage chips are stacked on the dielectric layer, the first heat dissipation block is arranged on the dielectric layer, the logic chip is arranged on the first heat dissipation block, the second heat dissipation block is arranged on the logic chip and extends to the surface of the plastic packaging layer, and the heat generated by the logic chip positioned in the middle position can be conducted to the dielectric layer and then conducted to the outside through the dielectric layer by arranging the first heat dissipation block, so that the heat dissipation is realized. Through setting up the second radiating block, can be with the heat conduction to the plastic envelope layer outside that the logic chip that is located the intermediate position produced, realize the heat dissipation, a plurality of first memory chip range upon range of settings simultaneously realizes that the chip piles up. Compared with the prior art, the logic chip heat dissipation device has the advantages that the first heat dissipation block and the second heat dissipation block are arranged, so that a good heat dissipation effect of the logic chip can be guaranteed, meanwhile, the stacking of a plurality of chips is realized through the laminated structure of the first storage chip, the stacking number is increased, and meanwhile, the good heat dissipation effect is guaranteed.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a schematic diagram of a chip package structure according to a first embodiment of the invention;
fig. 2 is a schematic diagram of a chip package structure according to a second embodiment of the invention;
fig. 3 to 9 are process flow diagrams of a method for manufacturing a chip package structure according to a third embodiment of the invention.
Icon: 100-chip package structure; 110-chip package module; 111-a first memory chip; 1111-a first conductive bump; 113-a logic chip; 1131 — a third conductive bump; 115-a first heatslug; 1151-a first thermal adhesive layer; 117-second heatslug; 1171-a second heat-dissipating glue layer; 118-a plastic packaging layer; 119-a second memory chip; 1191-second conductive bump; 130-a dielectric layer; 131-a first splice tray; 133-a second land; 150-a first electrical connection post; 151-first conductive layer; 170-a second electrical connection post; 171-a second conductive layer; 190-a heat sink plate; 191-a third heat dissipation glue layer; 200-carrier.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. indicate an orientation or a positional relationship based on that shown in the drawings or that the product of the present invention is used as it is, this is only for convenience of description and simplification of the description, and it does not indicate or imply that the device or the element referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present invention.
Furthermore, the appearances of the terms "first," "second," and the like, if any, are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
As disclosed in the background art, in the conventional stacked structure, as the number of memory chips increases, the size of the product is larger, which results in the thicker thickness of the plastic package layer, while the logic chip is usually located in the middle or bottom of the plastic package layer, and the logic chip generates a large amount of heat during operation. Meanwhile, the existing laminated structure usually adopts a routing mode to realize the electric connection between the memory chip and the logic chip, and usually routes the memory chip and the logic chip to the substrate, and the routing range is larger and larger along with the increase of the number of stacked layers due to the electric connection mode, the packaging size is also larger and larger, and the miniaturization of the product is not facilitated. And routing technology is complicated, and the process step is many, has reduced preparation efficiency, and along with piling up the increase of the number of layers, the routing also becomes more unstable, appears bridging or disconnected risk easily, influences product quality.
In order to solve the above problems, the present invention provides a novel chip package structure and a method for manufacturing the same, and it should be noted that, in a non-conflicting manner, features in the embodiments of the present invention may be combined with each other.
First embodiment
Referring to fig. 1, an embodiment of the present invention provides a chip package structure 100, which has a good heat dissipation effect, and meanwhile, a stacking structure of a first storage chip 111 is used to stack a plurality of chips, so that a good heat dissipation effect is ensured while the number of stacked chips is increased.
The chip package structure 100 provided in this embodiment includes a dielectric layer 130 and a chip package module 110 disposed on the dielectric layer 130, wherein the chip package module 110 may be prepared in advance, and the dielectric layer 130 is formed at the bottom of the prepared chip package module 110, or the chip package module 110 is attached to the dielectric layer 130 prepared in advance.
The chip package module 110 includes a logic chip 113, a plurality of first memory chips 111, at least one first heat dissipation block 115, at least one second heat dissipation block 117, and a molding layer 118, wherein the plurality of first memory chips 111 are stacked on the dielectric layer 130, the first heat dissipation block 115 is disposed on the dielectric layer 130, the logic chip 113 is disposed on the first heat dissipation block 115 and is located at one side of the plurality of first memory chips 111, the second heat dissipation block 117 is disposed on the logic chip 113, the molding layer 118 covers the logic chip 113, the first heat dissipation block 115, the second heat dissipation block 117, and the plurality of first memory chips 111, and the second heat dissipation block 117 extends to the surface of the molding layer 118.
In this embodiment, the first heat dissipation block 115 and the second heat dissipation block 117 are both metal heat dissipation blocks, and the heat conduction efficiency is high. Specifically, the first heat dissipation block 115 and the second heat dissipation block 117 are both copper blocks, the first heat dissipation block 115 can dissipate heat from the lower side of the logic chip 113, and the second heat dissipation block 117 can dissipate heat from the upper side of the logic chip 113.
In this embodiment, the first memory chip 111 has 4 layers, the logic chip 113 is disposed in the middle of the molding layer 118, the upper side of the logic chip 113 is provided with two second heat dissipation blocks 117, the two second heat dissipation blocks 117 are stacked and bonded by a heat dissipation adhesive, the two second heat dissipation blocks 117 extend from the molding layer 118, the lower side of the logic chip 113 is provided with one first heat dissipation block 115, and the one first heat dissipation block 115 is attached to the surface of the dielectric layer 130. The heat can be conducted to the outer side of the plastic package layer 118 through the two second heat dissipation blocks 117 on the upper side, so that heat dissipation is realized, and the heat can be conducted to the dielectric layer 130 through the first heat dissipation block 115 on the lower side, and conducted to the outside through the dielectric layer 130, so that heat dissipation is realized.
In the present embodiment, a first heat dissipation adhesive layer 1151 is disposed between the first heat dissipation block 115 and the lower surface of the logic chip 113, and a second heat dissipation adhesive layer 1171 is disposed between the second heat dissipation block 117 and the upper surface of the logic chip 113. Specifically, the first heat dissipation block 115 and the lower surface of the logic chip 113 are connected by a heat dissipation paste, and the second heat dissipation block 117 and the upper surface of the logic chip 113 are connected by a heat dissipation paste. In addition, two adjacent second heat dissipation blocks 117 may be connected by heat dissipation glue.
It should be noted that, in the present embodiment, the first heat dissipation block 115 can implement conduction of heat generated by the logic chip 113 to the dielectric layer 130 and to an external space. Meanwhile, the first heat dissipation block 115 can also realize a supporting function, so that the logic chip 113 is borne, and the structural stability of the packaging structure is ensured.
Further, the chip package structure 100 further includes a heat dissipation plate 190 attached to the molding layer 118, and the heat dissipation plate 190 is connected to the second heat dissipation block 117. Specifically, the heat dissipation plate 190 is attached to the upper surface of the plastic package layer 118 and connected to the second heat dissipation block 117, so that heat conducted from the second heat dissipation block 117 can be uniformly conducted to the outside, and the heat dissipation effect is further ensured.
In this embodiment, a third heat dissipation adhesive layer 191 is disposed between the heat dissipation plate 190 and the molding layer 118, and the third heat dissipation adhesive layer 191 extends to a position between the second heat dissipation block 117 and the heat dissipation plate 190. Specifically, the third heat dissipation adhesive layer 191 is coated on the bottom surface of the heat dissipation plate 190 and is adhered to the molding layer 118 and the second heat dissipation block 117.
It should be noted that, in this embodiment, the heat dissipation plate 190 and the second heat dissipation block 117 form a T-shaped heat dissipation structure, the problem of warpage of the package structure can be solved through the T-shaped heat dissipation structure, specifically, the heat dissipation plate 190 is attached to the upper side surface of the plastic package layer 118, and the shape of the heat dissipation plate 190 is matched with the shape of the plastic package layer 118, so as to prevent the warpage of the plastic package layer 118, meanwhile, the T-shaped structure can also play a role in supporting, thereby effectively solving the problem that the warpage stress of the plastic package layer 118 directly acts on the chip under the action of thermal expansion and cold contraction and the action of moisture absorption expansion, thereby buffering the stress, and the heat dissipation plate 190 directly conducts the heat of the plastic package body and the second heat dissipation block 117.
In this embodiment, the bottom of the heat dissipation plate 190 has heat dissipation glue, wherein the heat dissipation plate 190 can be made of ceramic sheet, metal sheet, or the like to achieve heat dissipation effect, preferably a copper plate is attached to the upper surface of the plastic package layer 118, and is bonded to the plastic package layer 118 and the second heat dissipation block 117.
In this embodiment, a first electrical connection post 150 is further disposed in the molding compound layer 118, the first electrical connection post 150 is located between the plurality of first memory chips 111 and the logic chip 113 and connected to the dielectric layer 130, a first conductive layer 151 is disposed on an upper side or a lower side of each first memory chip 111, the plurality of first conductive layers 151 are all connected to the first electrical connection post 150, and the logic chip 113 is connected to one of the first conductive layers 151. Specifically, the first electrical connection post 150 is formed by filling a conductive material after laser grooving, and the first electrical connection post 150 extends downward to the dielectric layer 130 and is electrically connected to the dielectric layer 130, so that the plurality of first memory chips 111 and the logic chip 113 can be electrically connected to the dielectric layer 130 through the first conductive layer 151 and the first electrical connection post 150, and the logic chip 113 and the first memory chip 111 can also be electrically connected to each other.
In this embodiment, a first conductive bump 1111 is disposed on an upper side or a lower side of the first memory chip 111, and the first conductive layer 151 is disposed corresponding to the first conductive bump 1111 and connected to the first conductive bump 1111. Specifically, the first conductive bump 1111 is disposed on the lower side of the first memory chip 111 located at the bottom layer and electrically connected to the first electrical connection stud 150 through the first conductive layer 151 on the bottom side, and the first conductive bumps 1111 are disposed on the upper sides of the remaining first memory chips 111 and electrically connected to the first electrical connection stud 150 through the first conductive layer 151 on the upper side.
Further, the chip package module 110 may further include a plurality of second memory chips 119 stacked on the dielectric layer 130, where the plurality of second memory chips 119 are disposed on a side of the logic chip 113 away from the plurality of first memory chips 111. Specifically, the plurality of first memory chips 111 are stacked and form a first stacked structure, the plurality of second memory chips 119 are stacked and form a second stacked structure, the first stacked structure and the second stacked structure are symmetrically disposed on the dielectric layer 130, and the logic chip 113 is disposed between the first stacked structure and the second stacked structure.
In this embodiment, a second electrical connection pillar 170 is further disposed in the molding compound layer 118, the second electrical connection pillar 170 is located between the plurality of second memory chips 119 and the logic chip 113 and connected to the dielectric layer 130, a second conductive layer 171 is disposed on the upper side or the lower side of each second memory chip 119, the plurality of second conductive layers 171 are all connected to the second electrical connection pillar 170, and the logic chip 113 is connected to one of the second conductive layers 171. Specifically, the second electrical connection column 170 is formed by filling a conductive material after laser grooving, and the second electrical connection column 170 extends downward to the dielectric layer 130 and is electrically connected to the dielectric layer 130, so that the plurality of second memory chips 119 and the logic chip 113 can be electrically connected to the dielectric layer 130 through the second electrical connection column 170, and the logic chip 113 and the second memory chip 119 are electrically connected to each other.
In this embodiment, a second conductive bump 1191 is disposed on the upper side or the lower side of each second memory chip 119, and the second conductive layer 171 is disposed corresponding to the second conductive bump 1191 and connected to the second conductive bump 1191. Specifically, the second conductive bumps 1191 are disposed on the lower side of the second memory chip 119 located on the bottom layer, and are electrically connected to the second cell connection post through the second conductive layer 171 on the bottom side, and the second conductive bumps 1191 are disposed on the upper sides of the remaining second memory chips 119 and are electrically connected to the second electrical connection post 170 through the second conductive layer 171 on the upper side.
In this embodiment, the logic chip 113 is a front-mounted chip, the upper surface of the logic chip 113 is provided with at least two third conductive bumps 1131, at least one of the third conductive bumps 1131 is electrically connected to the first electrical connection stud 150 through the adjacent first conductive layer 151, and at least one of the third conductive bumps 1131 is electrically connected to the second electrical connection stud 170 through the adjacent second conductive layer 171.
In this embodiment, the first memory chip 111 and the second memory chip 119 located at the uppermost layer both adopt a positive attachment structure, that is, the first conductive bump 1111 located on the first memory chip 111 located at the uppermost layer is located on the upper surface thereof, so that the first conductive layer 151 is disposed on the upper side of the first memory chip 111 located at the uppermost layer; the second conductive bumps 1191 on the second memory chip 119 of the uppermost layer are positioned on the upper surface thereof such that the second conductive layer 171 is disposed on the upper side of the second memory chip 119 of the uppermost layer.
In this embodiment, the dielectric layer 130 is provided with a first land 131 and a second land 133, the first electrical connection post 150 is connected to the first land 131 and electrically connected to the dielectric layer 130 through the first land 131, and the second electrical connection post 170 is connected to the second land 133 and electrically connected to the dielectric layer 130 through the second land 133.
In summary, in the chip package structure 100 provided in this embodiment, the plurality of first memory chips 111 and the plurality of second memory chips 119 are stacked on the dielectric layer 130, the first heat dissipation block 115 is disposed on the dielectric layer 130, the logic chip 113 is disposed on the first heat dissipation block 115, the second heat dissipation block 117 is disposed on the logic chip 113 and extends to the surface of the plastic package layer 118, and by disposing the first heat dissipation block 115, heat generated by the logic chip 113 located in the middle position can be conducted to the dielectric layer 130 and then conducted to the outside through the dielectric layer 130, so as to achieve heat dissipation. By arranging the second heat dissipation block 117, heat generated by the logic chip 113 located in the middle position can be conducted to the outer side of the plastic packaging layer 118, so that heat dissipation is realized, and meanwhile, the plurality of first memory chips 111 are arranged in a stacked mode, so that chip stacking is realized. And through setting up heating panel 190 to form T font heat radiation structure with second radiating block 117, further improve the radiating effect, and can prevent that plastic-sealed layer 118 from taking place the warpage phenomenon, play the cushioning effect simultaneously, prevent that plastic-sealed layer 118 from directly acting on the surface of logic chip 113 when warping, further guaranteed the structural stability of product.
Second embodiment
Referring to fig. 2, the basic structure and principle of the chip package structure 100 and the technical effects thereof are the same as those of the first embodiment, and for the sake of brief description, reference may be made to corresponding contents of the first embodiment for the sake of brevity.
In this embodiment, the chip package structure 100 includes a dielectric layer 130 and a chip package module 110 disposed on the dielectric layer 130, wherein the chip package module 110 may be prepared in advance, and the dielectric layer 130 is formed at the bottom of the prepared chip package module 110, or the chip package module 110 is attached to the dielectric layer 130 prepared in advance. The chip package module 110 includes a plurality of first memory chips 111, a plurality of second memory chips 119, a logic chip 113, at least one first heat dissipation block 115, at least one second heat dissipation block 117, a molding compound layer 118 and a heat dissipation plate 190, wherein the plurality of first memory chips 111 are stacked on the dielectric layer 130, the first heat dissipation block 115 is disposed on the dielectric layer 130, the logic chip 113 is disposed on the first heat dissipation block 115 and is located at one side of the plurality of first memory chips 111, the second heat dissipation block 117 is disposed on the logic chip 113, the molding compound layer 118 is wrapped outside the logic chip 113, the first heat dissipation block 115, the second heat dissipation block 117 and the plurality of first memory chips 111, and the second heat dissipation block 117 extends to the surface of the molding compound layer 118. The plurality of second memory chips 119 are disposed on one side of the logic chip 113 away from the plurality of first memory chips 111, a second electrical connection column 170 is further disposed in the plastic package layer 118, the second electrical connection column 170 is disposed between the plurality of second memory chips 119 and the logic chip 113 and connected to the dielectric layer 130, a second conductive layer 171 is disposed on an upper side or a lower side of each second memory chip 119, the plurality of second conductive layers 171 are all connected to the second electrical connection column 170, and the logic chip 113 is connected to one of the second conductive layers 171. The heat dissipation plate 190 is attached to the molding layer 118 and connected to the second heat dissipation block 117.
In this embodiment, the first memory chip 111 and the second memory chip 119 on the top layer are both flip-chip structures, that is, the first conductive bump 1111 on the first memory chip 111 on the top layer is located on the bottom side thereof, and is electrically connected to the first electrical connection pillar 150 by sharing the same first conductive layer 151 with the first memory chip 111 on the second top layer. The second conductive bumps 1191 on the top second memory chip 119 are on the bottom side thereof and electrically connected to the second electrical connection studs 170 by sharing the same second conductive layer 171 with the second memory chip 119 on the next top layer.
It should be noted that in this embodiment, the first memory chip 111 and the second memory chip 119 in the top layer and the bottom layer are both flip-chip structures, and the remaining first memory chip 111 and the remaining second memory chip 119 are both normal-mounted structures, and this arrangement can save the arrangement of the first conductive layer 151 and the second conductive layer 171, and simplify the manufacturing process.
Third embodiment
The present embodiment provides a method for manufacturing a chip package structure 100, which is used to manufacture the chip package structure 100 provided in the first embodiment or the second embodiment.
The preparation method comprises the following steps:
s1: the chip package module 110 is prepared on the carrier 200.
Specifically, the chip package module 110 is prepared by using the carrier 200, the chip package module 110 is molded on the carrier 200, finally the carrier 200 is removed, and the dielectric layer 130 is formed on the bottom side of the molded chip package module 110, or the chip package module 110 is attached to the dielectric layer 130 prepared in advance. The carrier 200 may be made of glass, silicon oxide, metal, or the like, and the chip package module 110 is manufactured by the carrier 200, so that the warpage problem during the manufacturing process can be eliminated, and the structural stability of the chip package module 110 can be ensured.
The chip package module 110 includes a plurality of first memory chips 111, a plurality of second memory chips 119, a logic chip 113, at least one first heat dissipation block 115, at least one second heat dissipation block 117, a molding compound layer 118 and a heat dissipation plate 190, wherein the plurality of first memory chips 111 are stacked on the dielectric layer 130, the first heat dissipation block 115 is disposed on the dielectric layer 130, the logic chip 113 is disposed on the first heat dissipation block 115 and is located at one side of the plurality of first memory chips 111, the second heat dissipation block 117 is disposed on the logic chip 113, the molding compound layer 118 is wrapped outside the logic chip 113, the first heat dissipation block 115, the second heat dissipation block 117 and the plurality of first memory chips 111, and the second heat dissipation block 117 extends to the surface of the molding compound layer 118. The plurality of second memory chips 119 are disposed on one side of the logic chip 113 away from the plurality of first memory chips 111, a second electrical connection column 170 is further disposed in the plastic package layer 118, the second electrical connection column 170 is disposed between the plurality of second memory chips 119 and the logic chip 113 and connected to the dielectric layer 130, a second conductive layer 171 is disposed on an upper side or a lower side of each second memory chip 119, the plurality of second conductive layers 171 are all connected to the second electrical connection column 170, and the logic chip 113 is connected to one of the second conductive layers 171. The heat dissipation plate 190 is attached to the molding layer 118 and connected to the second heat dissipation block 117.
In this embodiment, when actually preparing the chip package module 110, the step S1 specifically includes the following steps:
step 1, referring to fig. 3, a carrier 200 is coated with a UV glue layer on its surface, and the carrier 200 is used to eliminate the warpage problem in the process. The first memory chip 111 and the second memory chip 119 are flip-chip mounted on the UV adhesive layer, that is, the first conductive bump 1111 on the first memory chip 111 is disposed downward, the second conductive bump 1191 on the second memory chip 119 is disposed downward, and then the first heat dissipation block 115 is attached to the UV adhesive layer to form a bottom layer structure.
The UV glue layer is a light-sensitive layer, and the material of the UV glue layer can be eliminated by irradiating UV light (ultraviolet light), so as to perform a separation function, and the UV glue layer can be made of one or more of but not limited to adhesive glue, epoxy resin and polyimide through UV curing or thermosetting, and is used as a separation layer between the chip packaging module 110 and the chip packaging module formed later.
Step 2, referring to fig. 4, the first memory chip 111 is mounted on the first memory chip 111 again, the second memory chip 119 is mounted on the second memory chip 119 again, and the logic chip 113 is mounted on the first heat sink 115, wherein the first memory chip 111 and the second memory chip 119 mounted again are both front-mounted chips, such that the first conductive bump 1111 on the first memory chip 111 faces upward and is disposed opposite to the first memory chip 111 on the bottom layer, and the second conductive bump 1191 on the second memory chip 119 faces upward and is disposed opposite to the second memory chip 119 on the bottom layer. The logic chip 113 is also a normal chip, and the third conductive bump 1131 on the logic chip 113 is disposed upward.
After the first storage chip 111 and the second storage chip 119 on the second layer are mounted, an intermediate plastic package body is formed on the UV adhesive layer by printing liquid plastic package materials again, the mounted structure is subjected to plastic package protection by solidifying the plastic package materials, and then the first storage chip 111, the second storage chip 119 and the logic chip 113 on the second layer are exposed by utilizing a grinding process. Wherein the plastic packaging material can be epoxy resin, silicon oxide and the like.
Step 3, referring to fig. 5, wiring is performed on the upper side surfaces of the first memory chip 111 and the second memory chip 119, specifically, patterning can be achieved through exposure and development, a first conductive layer 151 and a second conductive layer 171 are formed, then, a laser hole forming process is used for forming holes in the first conductive layer 151 and the second conductive layer 171, the holes extend downwards to the UV glue layer, conductive glue is filled into the holes, and after curing through baking, the first electrical connection column 150 and the second electrical connection column 170 are formed, wherein the conductive glue can be conductive silver glue or conductive paste, and the like, and the material of the conductive glue needs to meet the conductive property.
In step 4, referring to fig. 6, the first memory chip 111 is mounted again on the first memory chip 111, the second memory chip 119 is mounted again on the second memory chip 119, and then the second heat slug 117 is mounted on the logic chip 113. Forming an intermediate plastic package body on the second layer by solidifying the plastic package material, protecting the mounted structure, exposing the first memory chip 111, the second memory chip 119 and the second heat dissipation block 117 by using a grinding process again, and preparing a first conductive layer 151, a first electrical connection column 150, a second conductive layer 171 and a second electrical connection column 170, wherein the symmetrical first heat dissipation block 115 and the second heat dissipation block 117 can perform the up-and-down heat dissipation function of the logic chip 113. Meanwhile, the second heat dissipation block 117 can also play a supporting role, and the problem that the plastic package layer 118 in the existing packaging laminated structure has the defects that the stress generated by warping is directly applied to the chip to cause the crack of the stacked chip structure under the thermal expansion and cold contraction action and the moisture absorption expansion action is solved.
Step 5, referring to fig. 7, the first memory chip 111, the second memory chip 119, and the second heat dissipation block 117 are repeatedly mounted. And when the chip package structure 100 provided as the first embodiment is prepared, the first memory chip 111 and the second memory chip 119 on the top side are both arranged in a normal manner, and when the chip package structure 100 provided as the second embodiment is prepared, the first memory chip 111 and the second memory chip 119 on the top side are both arranged in a flip manner, which is illustrated here by taking the first embodiment as an example. After mounting, the molding compound is cured, and finally the molding layer 118 encapsulating the mounting structure is formed.
Step 6, referring to fig. 8, the heat dissipation plate 190 is attached, the bottom of the heat dissipation plate 190 is coated with heat dissipation glue and attached to the top surface of the plastic package layer 118 and the surface of the second heat dissipation block 117, so that a T-shaped heat dissipation structure is formed, the heat dissipation effect is further improved, meanwhile, the plastic package layer 118 is prevented from warping, and the structural stability of the chip packaging module 110 is further ensured. Wherein, the bottom of the radiating fin is coated with radiating glue, so that heat is conducted to the radiating fin to realize heat dissipation. The radiating fins can be made of ceramic plates, metal plates and other materials for realizing the radiating effect and the supporting effect, wherein the radiating glue can be high-heat-conductivity silver glue, high-heat-conductivity copper paste and the like. Finally, characters are engraved on the surface of the heat dissipation plate 190.
Step 7, referring to fig. 9, the bottom is cured by UV or thermal curing, the UV glue layer is removed, so that the carrier 200 is separated from the package structure, the first memory chip 111 and the second memory chip 119 at the bottom are exposed, and the first electrical connection post 150 and the second electrical connection post 170 are exposed at the same time, wherein the first conductive bump 1111 on the first memory chip 111 at the bottom is located at the bottom side, the second conductive bump 1191 on the second memory chip 119 at the bottom is located at the bottom side, then wiring is performed at the bottom to form the first conductive layer 151 and the second conductive layer 171, the first conductive bump 1111 at the bottom side is electrically connected to the first electrical connection post 150 through the first conductive layer 151, and the second conductive bump 1191 at the bottom side is electrically connected to the second electrical connection post 170 through the second conductive layer 171, and the chip package module 110 is formed.
After the chip packaging module 110 is formed, step S2 needs to be performed.
S2: a dielectric layer 130 is disposed on the bottom side of the chip package module 110.
Specifically, referring to fig. 1, a dielectric material is filled on the bottom side of the chip package module 110 to make the surface thereof flat, and a dielectric layer 130 is formed, then the bottom side of the dielectric layer 130 is subjected to ball mounting by using a ball mounting process, and finally, the product is cut into single pieces by using a cutting method, thereby completing the whole process.
In summary, in the method for manufacturing the chip structure provided in this embodiment, the plurality of first memory chips 111 and the plurality of second memory chips 119 are stacked on the dielectric layer 130, the first heat dissipation block 115 is disposed on the dielectric layer 130, the logic chip 113 is disposed on the first heat dissipation block 115, the second heat dissipation block 117 is disposed on the logic chip 113 and extends to the surface of the plastic package layer 118, and by disposing the first heat dissipation block 115, heat generated by the logic chip 113 located in the middle position can be conducted to the dielectric layer 130 and then conducted to the outside through the dielectric layer 130, so as to achieve heat dissipation. By arranging the second heat dissipation block 117, heat generated by the logic chip 113 located in the middle position can be conducted to the outer side of the plastic packaging layer 118, so that heat dissipation is realized, and meanwhile, the plurality of first memory chips 111 are arranged in a stacked mode, so that chip stacking is realized. And through setting up heating panel 190 to form T font heat radiation structure with second radiating block 117, further improve the radiating effect, and can prevent that plastic-sealed layer 118 from taking place the warpage phenomenon, play the cushioning effect simultaneously, prevent that plastic-sealed layer 118 from directly acting on the surface of logic chip 113 when warping, further guaranteed the structural stability of product.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (11)
1. A chip package structure, comprising:
a dielectric layer;
the chip packaging module is arranged on the medium layer and comprises a logic chip, a plastic packaging layer, at least one first radiating block, at least one second radiating block and a plurality of first storage chips, the first storage chips are stacked on the medium layer, the first radiating block is arranged on the medium layer, the logic chip is arranged on the first radiating block and is positioned on one side of the first storage chips, the second radiating block is arranged on the logic chip, the plastic packaging layer is coated on the logic chip, the first radiating block, the second radiating block and the plurality of first storage chips, and the second radiating block extends to the surface of the plastic packaging layer.
2. The chip package structure according to claim 1, wherein a first heat dissipation adhesive layer is disposed between the first heat slug and the lower surface of the logic chip, and a second heat dissipation adhesive layer is disposed between the second heat slug and the upper surface of the logic chip.
3. The chip package structure according to claim 1, further comprising a heat dissipation plate attached to the molding layer, wherein the heat dissipation plate is connected to the second heat slug.
4. The chip package structure according to claim 3, wherein a third thermal adhesive layer is disposed between the thermal plate and the molding layer, and the third thermal adhesive layer extends to a position between the second heat slug and the thermal plate.
5. The chip packaging structure according to any one of claims 1 to 3, wherein a first electrical connection post is further disposed in the plastic package layer, the first electrical connection post is located between the plurality of first memory chips and the logic chip and connected to the dielectric layer, a first conductive layer is disposed on an upper side or a lower side of each of the first memory chips, the plurality of first conductive layers are connected to the first electrical connection post, and the logic chip is connected to one of the first conductive layers.
6. The chip package structure according to claim 5, wherein a first conductive bump is disposed on an upper side or a lower side of the first memory chip, and the first conductive layer is disposed corresponding to the first conductive bump and connected to the first conductive bump.
7. The chip package structure according to claim 5, wherein the chip package module further comprises a plurality of second memory chips stacked on the dielectric layer, and the plurality of second memory chips are disposed on a side of the logic chip away from the plurality of first memory chips.
8. The chip package structure according to claim 7, wherein a second electrical connection post is further disposed in the plastic package layer, the second electrical connection post is located between the plurality of second memory chips and the logic chip and connected to the dielectric layer, a second conductive layer is disposed on an upper side or a lower side of each of the second memory chips, the plurality of second conductive layers are connected to the second electrical connection post, and the logic chip is connected to one of the second conductive layers.
9. The chip package structure according to claim 8, wherein a second conductive bump is disposed on an upper side or a lower side of each of the second memory chips, and the second conductive layer is disposed corresponding to and connected to the second conductive bump.
10. The chip package structure according to claim 9, wherein a first land and a second land are disposed on the dielectric layer, the first electrical connection post is connected to the first land and electrically connected to the dielectric layer through the first land, and the second electrical connection post is connected to the second land and electrically connected to the dielectric layer through the second land.
11. A method for manufacturing a chip package structure according to claim 1, comprising:
preparing a chip packaging module on a carrier;
arranging a dielectric layer at the bottom side of the chip packaging module;
wherein, the chip package module includes a plurality of first memory chip, logic chip, at least one first radiating block, at least one second radiating block and plastic-sealed layer, and is a plurality of the range upon range of setting of first memory chip is in on the dielectric layer, first radiating block sets up on the dielectric layer, logic chip sets up on the first radiating block to it is a plurality of to be located one side of first memory chip, the second radiating block sets up on the logic chip, the plastic-sealed layer cladding is in logic chip first radiating block second radiating block and a plurality of outside the first memory chip, just the second radiating block extends to the surface of plastic-sealed layer.
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