CN112802838B - Broadband ESD protection circuit - Google Patents
Broadband ESD protection circuit Download PDFInfo
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- CN112802838B CN112802838B CN202011610151.0A CN202011610151A CN112802838B CN 112802838 B CN112802838 B CN 112802838B CN 202011610151 A CN202011610151 A CN 202011610151A CN 112802838 B CN112802838 B CN 112802838B
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- H—ELECTRICITY
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
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Abstract
The invention discloses a broadband ESD protection circuit, which comprises an on-chip multilayer inductor, an ESD device, an impedance matching resistor, a circuit input port and a circuit output port; the on-chip multilayer inductor is of a three-dimensional multilayer spiral structure, the number of layers is 2 or more, and the number of turns of each layer of metal coil is 1 or 2; the top, bottom and middle parts of the on-chip multi-layer inductor form an inductor top layer port, an inductor bottom layer port and an inductor middle port respectively; the top-layer port of the inductor is electrically connected with the circuit input port, the bottom-layer port of the inductor is electrically connected with the impedance matching resistor, and the middle-layer port of the inductor is electrically connected with the circuit output port; at least one of the inductance top layer port, the inductance bottom layer port, and the inductance middle port is connected with an ESD device electrically connected to the power supply terminal VDD and an ESD device connected to the ground terminal GND. The invention can obtain better broadband characteristics and simultaneously maintain good ESD protection performance.
Description
Technical Field
The invention relates to the field of design of integrated circuit chip ESD protection circuits, in particular to a broadband ESD protection circuit which fuses multiple layers of inductors on a chip and can be applied to high-speed or radio frequency integrated circuits.
Background
Electrostatic discharge (ESD) has become a serious problem affecting the reliability of integrated circuits, and all chips must be designed with protection circuitry to mitigate the ESD hazard. In high speed and radio frequency integrated circuits, ESD protection designs face greater challenges, such as introducing additional parasitic capacitance, noise, etc. from the ESD protection devices, which can cause degradation in core circuit performance. On one hand, the smaller the area of the ESD protection device is, the smaller the parasitic capacitance is introduced; on the other hand, the larger the area of the ESD protection device is, the larger the capability of bearing ESD current is, so that the improvement of ESD robustness and the reduction of the influence of the protection device are often contradictory.
Fig. 1 is a conventional ESD protection circuit using diodes as protection devices, which is composed of a pair of diodes connected to a power supply terminal VDD and a ground terminal GND, respectively, and can provide positive and negative ESD current discharge paths. Normally, the diode is in a closed state, and normal operation of the circuit is not affected. When the port is impacted by ESD, ESD current may bleed through the diode to VDD and GND, protecting the core circuitry. For low frequency circuits, the parasitic capacitance of the diode, etc. is negligible, while for high speed or radio frequency circuits, the parasitic capacitance of the diode will greatly affect the quality of the port signal.
Aiming at the problem that the parasitic effect of the ESD device affects the signal quality, the fusion of the on-chip inductor is one of the feasible solutions, and the on-chip inductor can partially relieve the influence of the parasitic capacitance of the ESD device, so that the signal quality can be improved. Fig. 2 is an ESD protection circuit using on-chip inductance that can cancel the effect of parasitic capacitance to some extent. Key problems with using on-chip inductance are: firstly, the ESD protection performance is not obviously reduced after the on-chip inductor is introduced; secondly, the circuit bandwidth can not be obviously improved after the on-chip inductor is introduced; third, the use of on-chip inductors will occupy more chip area, and if there are more chip ports, the problem of the on-chip inductors occupying more chip area is more pronounced. Therefore, the design of a broadband ESD protection circuit requires a compromise between ESD protection effect and broadband performance, while effectively reducing the area.
Disclosure of Invention
The invention aims to provide a broadband ESD protection circuit applied to a high-speed and radio frequency integrated circuit, which adopts the following technical scheme:
a wideband ESD protection circuit, the wideband ESD protection circuit comprising: an on-chip multilayer inductor, an ESD device, an impedance matching resistor, a circuit input port and a circuit output port;
the on-chip multilayer inductor is of a three-dimensional multilayer spiral structure, the number of layers is 2 or more, and the number of turns of each layer of metal coil is 1 or 2;
the top, bottom and middle of the on-chip multilayer inductor are respectively provided with an inductor top layer port, an inductor bottom layer port and an inductor middle port;
the top-layer port of the inductor is connected with the input port of the circuit;
the inductance bottom layer port is connected with one end of the impedance matching resistor;
the inductance intermediate port is connected with the circuit output port;
the ESD device specifically comprises: a third ESD device and a fourth ESD device;
one end of the third ESD device is connected with the power supply end VDD, and the other end of the third ESD device is connected with the circuit output port;
one end of the fourth ESD device is connected with the ground end GND, and the other end of the fourth ESD device is connected with the circuit output port;
alternatively, the ESD device specifically includes: a first ESD device, a second ESD device, a fifth ESD device, a sixth ESD device;
one end of the first ESD device is connected with a power supply end VDD, and the other end of the first ESD device is connected with the circuit input port;
one end of the second ESD device is connected with the ground end GND, and the other end of the second ESD device is connected with the circuit input port;
one end of the fifth ESD device is connected with the power supply end VDD, and the other end of the fifth ESD device is connected with one end of the impedance matching resistor;
one end of the sixth ESD device is connected with the ground end GND, and the other end of the sixth ESD device is connected with one end of the impedance matching resistor;
alternatively, the ESD device specifically includes: a first ESD device, a second ESD device, a third ESD device, a fourth ESD device, a fifth ESD device, a sixth ESD device;
one end of the first ESD device is connected with a power supply end VDD, and the other end of the first ESD device is connected with the circuit input port;
one end of the second ESD device is connected with the ground end GND, and the other end of the second ESD device is connected with the circuit input port;
one end of the third ESD device is connected with the power supply end VDD, and the other end of the third ESD device is connected with the circuit output port;
one end of the fourth ESD device is connected with the ground end GND, and the other end of the fourth ESD device is connected with the circuit output port;
one end of the fifth ESD device is connected with the power supply end VDD, and the other end of the fifth ESD device is connected with one end of the impedance matching resistor;
one end of the sixth ESD device is connected with the ground end GND, and the other end of the sixth ESD device is connected with one end of the impedance matching resistor;
the other end of the impedance matching resistor is connected with a grounding end GND or a power supply end VDD.
Further improvement, each layer of metal coil of the on-chip multilayer inductor is square, polygonal or circular in shape;
further improvements include the ESD device being a diode, bipolar transistor, junction field effect transistor, MOS field effect transistor or thyristor;
further improvements are made to adjust the ESD protection performance and circuit broadband characteristics of the circuit by adjusting the arrangement, size and size ratio of the first ESD device, the second ESD device, the third ESD device, the fourth ESD device, the fifth ESD device and the sixth ESD device.
Compared with the prior art, the technical scheme of the invention has the following characteristics:
firstly, the technical scheme uses the on-chip multilayer inductor, and the area of the on-chip multilayer inductor is greatly reduced compared with the on-chip plane inductor due to the three-dimensional structure of the on-chip multilayer inductor; the technical scheme can obtain better broadband characteristics, and simultaneously maintain good ESD protection performance;
secondly, the ESD device in the technical scheme can adopt a diode, a bipolar triode, a junction field effect transistor, a MOS field effect transistor or a thyristor;
third, by adjusting the ESD device settings of the inductor top port 108, bottom port 109, and intermediate port 110, and the dimensional ratios between the ESD devices, the ESD protection performance and circuit broadband characteristics of the circuit can be further optimized.
Drawings
Fig. 1: conventional ESD protection circuits in the prior art that employ diode devices;
fig. 2: an ESD protection circuit adopting on-chip planar inductance in the prior art;
fig. 3: the broadband ESD protection circuit structure schematic diagram of the invention;
fig. 4: schematic diagram of embodiment 1 implemented according to the present invention;
fig. 5: schematic diagram of embodiment 2 implemented according to the present invention;
fig. 6: schematic diagram of embodiment 3 implemented according to the present invention;
fig. 7: embodiment 4 implemented according to the invention is schematic.
[ reference numerals description ]
101: an on-chip multilayer inductor;
102a: a first ESD device;
102b: a second ESD device;
103a: a third ESD device;
103b: a fourth ESD device;
104a: a fifth ESD device;
104b: a sixth ESD device;
105: an impedance matching resistor;
106: a circuit input port;
107: a circuit output port;
108: an inductance top layer port;
109: an inductance bottom layer port;
110: an inductive intermediate port.
Detailed description of the preferred embodiments
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. These embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
Example 1
As shown in fig. 4, includes: an on-chip multilayer inductor 101, a first ESD device 102a, a second ESD device 102b, a third ESD device 103a, a fourth ESD device 103b, a fifth ESD device 104a, a sixth ESD device 104b, an impedance matching resistor 105, a circuit input port 106, and a circuit output port 107.
The number of layers of the on-chip multilayer inductor 101 is 5, and the number of turns of each layer of metal coil is 1.
The first ESD device 102a, the second ESD device 102b, the third ESD device 103a, the fourth ESD device 103b, the fifth ESD device 104a, and the sixth ESD device 104b are diodes.
The impedance matching resistor 105 is 50 ohms, and one end thereof is connected to the ground GND.
Example 2
As shown in fig. 5, includes: an on-chip multilayer inductor 101, a first ESD device 102a, a second ESD device 102b, a fifth ESD device 104a, a sixth ESD device 104b, an impedance matching resistor 105, a circuit input port 106, and a circuit output port 107.
The number of layers of the on-chip multilayer inductor 101 is 5, and the number of turns of each layer of metal coil is 1.
The first ESD device 102a, the second ESD device 102b, the fifth ESD device 104a, and the sixth ESD device 104b are diodes.
The impedance matching resistor 105 is 50 ohms, and one end thereof is connected to the power supply terminal VDD.
Example 3
As shown in fig. 6, includes: an on-chip multilayer inductor 101, a third ESD device 103a, a fourth ESD device 103b, an impedance matching resistor 105, a circuit input port 106, and a circuit output port 107.
The number of layers of the on-chip multilayer inductor 101 is 3, and the number of turns of each layer of metal coil is 1.
The third ESD device 103a and the fourth ESD device 103b are diodes.
The impedance matching resistor 105 is 50 ohms, and one end thereof is connected to the ground GND.
Example 4
As shown in fig. 7, includes: an on-chip multilayer inductor 101, a first ESD device 102a, a second ESD device 102b, a third ESD device 103a, a fourth ESD device 103b, a fifth ESD device 104a, a sixth ESD device 104b, an impedance matching resistor 105, a circuit input port 106, and a circuit output port 107.
The number of layers of the on-chip multilayer inductor 101 is 5, and the number of turns of each layer of metal coil is 1.
The first ESD device 102a, the third ESD device 103a, and the fifth ESD device 104a are P-type MOS field effect transistors; the second ESD device 102b, the fourth ESD device 103b, and the sixth ESD device 104b are N-type MOS field effect transistors; .
The impedance matching resistor 105 is 50 ohms, and one end thereof is connected to the ground GND.
In the description of the present invention, it should be understood that the terms "first," "second," "third," "fourth," "fifth," "sixth" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "first", "second", "third", "fourth", "fifth" and "sixth" may explicitly or implicitly include one or more such feature.
In the description of the present specification, the terms "one embodiment," "some embodiments," "examples," "particular examples," or "some examples," etc., refer to particular features, structures, materials, or characteristics described in connection with the embodiment or example as being included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
While embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that alterations, modifications, substitutions and variations may be made in the above embodiments by those skilled in the art within the scope of the invention.
Claims (2)
1. A broadband ESD protection circuit, comprising: an on-chip multilayer inductor (101), an ESD device, an impedance matching resistor (105), a circuit input port (106), and a circuit output port (107);
the on-chip multilayer inductor (101) is of a three-dimensional multilayer spiral structure, the number of layers is 2 or more, and the number of turns of each layer of metal coil is 1 or 2;
the top, bottom and middle parts of the on-chip multilayer inductor (101) are respectively provided with an inductor top layer port (108), an inductor bottom layer port (109) and an inductor middle port (110);
the inductance top layer port (108) is connected with the path input port (106);
the inductance bottom layer port (109) is connected with one end of the impedance matching resistor (105);
-said inductive intermediate port (110) is connected to said circuit output port (107);
the ESD device specifically comprises: a third ESD device (103 a) and a fourth ESD device (103 b);
one end of the third ESD device (103 a) is connected with a power supply end VDD, and the other end of the third ESD device is connected with the circuit output port (107);
one end of the fourth ESD device (103 b) is connected with the ground end GND, and the other end of the fourth ESD device is connected with the circuit output port (107);
alternatively, the ESD device specifically includes: a first ESD device (102 a), a second ESD device (102 b), a fifth ESD device (104 a), a sixth ESD device (104 b);
one end of the first ESD device (102 a) is connected with a power supply end VDD, and the other end of the first ESD device is connected with the circuit input port (106);
one end of the second ESD device (102 b) is connected with a ground end GND, and the other end of the second ESD device is connected with the circuit input port (106);
one end of the fifth ESD device (104 a) is connected with a power supply end VDD, and the other end of the fifth ESD device is connected with one end of the impedance matching resistor (105);
one end of the sixth ESD device (104 b) is connected with the ground end GND, and the other end of the sixth ESD device is connected with one end of the impedance matching resistor (105);
alternatively, the ESD device specifically includes: a first ESD device (102 a), a second ESD device (102 b), a third ESD device (103 a), a fourth ESD device (103 b), a fifth ESD device (104 a), a sixth ESD device (104 b);
one end of the first ESD device (102 a) is connected with a power supply end VDD, and the other end of the first ESD device is connected with the circuit input port (106);
one end of the second ESD device (102 b) is connected with a ground end GND, and the other end of the second ESD device is connected with the circuit input port (106);
one end of the third ESD device (103 a) is connected with a power supply end VDD, and the other end of the third ESD device is connected with the circuit output port (107);
one end of the fourth ESD device (103 b) is connected with the ground end GND, and the other end of the fourth ESD device is connected with the circuit output port (107);
one end of the fifth ESD device (104 a) is connected with a power supply end VDD, and the other end of the fifth ESD device is connected with one end of the impedance matching resistor (105);
one end of the sixth ESD device (104 b) is connected with the ground end GND, and the other end of the sixth ESD device is connected with one end of the impedance matching resistor (105);
the other end of the impedance matching resistor (105) is connected with a ground end GND or a power end VDD;
each layer of metal coil of the on-chip multilayer inductor (101) is square, polygonal or circular in shape;
the ESD device is a diode, a bipolar triode, a junction field effect transistor, a MOS field effect transistor or a thyristor.
2. The broadband ESD protection circuit of claim 1, wherein the ESD protection performance and the circuit broadband characteristics of the circuit are adjusted by adjusting the arrangement, size and size ratio of the first ESD device (102 a), the second ESD device (102 b), the third ESD device (103 a), the fourth ESD device (103 b), the fifth ESD device (104 a) and the sixth ESD device (104 b).
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011610151.0A CN112802838B (en) | 2020-12-29 | 2020-12-29 | Broadband ESD protection circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011610151.0A CN112802838B (en) | 2020-12-29 | 2020-12-29 | Broadband ESD protection circuit |
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| CN112802838A CN112802838A (en) | 2021-05-14 |
| CN112802838B true CN112802838B (en) | 2023-04-28 |
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Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6597227B1 (en) * | 2000-01-21 | 2003-07-22 | Atheros Communications, Inc. | System for providing electrostatic discharge protection for high-speed integrated circuits |
| US7265433B2 (en) * | 2005-01-13 | 2007-09-04 | International Business Machines Corporation | On-pad broadband matching network |
| US7750408B2 (en) * | 2007-03-29 | 2010-07-06 | International Business Machines Corporation | Integrated circuit structure incorporating an inductor, a conductive sheet and a protection circuit |
| GB2496713A (en) * | 2010-09-06 | 2013-05-22 | Murata Manufacturing Co | RFID module and RFID device |
| US9093977B2 (en) * | 2012-07-31 | 2015-07-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated passive device filter with fully on-chip ESD protection |
| US20190089150A1 (en) * | 2017-09-19 | 2019-03-21 | Kandou Labs, S.A. | Distributed electrostatic discharge protection for chip-to-chip communications interface |
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