CN112802838B - Broadband ESD protection circuit - Google Patents

Abstract

The invention discloses a broadband ESD protection circuit, which comprises an on-chip multilayer inductor, an ESD device, an impedance matching resistor, a circuit input port and a circuit output port; the on-chip multilayer inductor is of a three-dimensional multilayer spiral structure, the number of layers is 2 or more, and the number of turns of each layer of metal coil is 1 or 2; the top, bottom and middle parts of the on-chip multi-layer inductor form an inductor top layer port, an inductor bottom layer port and an inductor middle port respectively; the top-layer port of the inductor is electrically connected with the circuit input port, the bottom-layer port of the inductor is electrically connected with the impedance matching resistor, and the middle-layer port of the inductor is electrically connected with the circuit output port; at least one of the inductance top layer port, the inductance bottom layer port, and the inductance middle port is connected with an ESD device electrically connected to the power supply terminal VDD and an ESD device connected to the ground terminal GND. The invention can obtain better broadband characteristics and simultaneously maintain good ESD protection performance.

Description

A Broadband ESD Protection Circuit

technical field

The invention relates to the design field of integrated circuit chip ESD protection circuits, and more specifically relates to a broadband ESD protection circuit that integrates multi-layer inductors on a chip and can be applied to high-speed or radio frequency integrated circuits.

Background technique

Electrostatic discharge (ESD) has become a serious problem affecting the reliability of integrated circuits, and all chips must be designed with protective circuits to reduce the harm of ESD. In high-speed and radio frequency integrated circuits, ESD protection design faces greater challenges. For example, the introduction of additional parasitic capacitance and noise by ESD protection devices will cause degradation of core circuit performance. On the one hand, the smaller the area of the ESD protection device, the smaller the parasitic capacitance introduced; on the other hand, the larger the area of the ESD protection device, the greater the ability to withstand the ESD current, so improving ESD robustness and reducing the impact of the protection device are often contradictory of.

Figure 1 is a conventional ESD protection circuit using a diode as a protection device. It consists of a pair of diodes, which are respectively connected to the power supply terminal VDD and the ground terminal GND, which can provide positive and negative ESD current discharge paths. Normally, the diode is off and does not affect the normal operation of the circuit. When the port is impacted by ESD, the ESD current can be discharged to VDD and GND through the diode, thereby protecting the core circuit. For low-frequency circuits, the parasitic capacitance of the diode can be ignored, but for high-speed or radio frequency circuits, the parasitic capacitance of the diode will greatly affect the quality of the port signal.

For the problem that the parasitic effects of ESD devices affect the signal quality, the fusion of on-chip inductors is one of the feasible solutions. The on-chip inductors can partially alleviate the influence of the parasitic capacitance of ESD devices, thereby improving the signal quality. Figure 2 is an ESD protection circuit using on-chip inductors, which can offset the effects of parasitic capacitance to a certain extent. The key issues when using on-chip inductors are: first, will the ESD protection performance be significantly reduced after the introduction of on-chip inductors; second, can the circuit bandwidth be significantly improved after the introduction of on-chip inductors; third, using on-chip inductors will take up more Chip area, if there are many chip ports, the problem of on-chip inductors occupying chip area is more prominent. Therefore, the design of the broadband ESD protection circuit needs to compromise the ESD protection effect and the broadband performance, and at the same time needs to effectively reduce the area.

Contents of the invention

The purpose of the present invention is to provide a kind of broadband ESD protection circuit that is applied to high-speed and radio frequency integrated circuits, and the adopted technical scheme is:

A broadband ESD protection circuit, the broadband ESD protection circuit comprising: on-chip multilayer inductors, ESD devices, impedance matching resistors, circuit input ports and circuit output ports;

The on-chip multilayer inductor is a three-dimensional multilayer spiral structure, the number of layers is 2 or more layers, and the number of turns of each layer of metal coil is 1 or 2;

The top, bottom and middle of the on-chip multilayer inductor respectively have an inductor top layer port, an inductor bottom layer port and an inductor middle port;

The top layer port of the inductance is connected to the circuit input port;

The bottom port of the inductor is connected to one end of the impedance matching resistor;

The middle port of the inductor is connected to the output port of the circuit;

The ESD device specifically includes: a third ESD device and a fourth ESD device;

One end of the third ESD device is connected to the power supply terminal VDD, and the other end is connected to the output port of the circuit;

One end of the fourth ESD device is connected to the ground terminal GND, and the other end is connected to the output port of the circuit;

Alternatively, the ESD device specifically includes: a first ESD device, a second ESD device, a fifth ESD device, and a sixth ESD device;

One end of the first ESD device is connected to the power supply terminal VDD, and the other end is connected to the input port of the circuit;

One end of the second ESD device is connected to the ground terminal GND, and the other end is connected to the input port of the circuit;

One end of the fifth ESD device is connected to the power supply terminal VDD, and the other end is connected to one end of the impedance matching resistor;

One end of the sixth ESD device is connected to the ground terminal GND, and the other end is connected to one end of the impedance matching resistor;

Alternatively, the ESD device specifically includes: a first ESD device, a second ESD device, a third ESD device, a fourth ESD device, a fifth ESD device, and a sixth ESD device;

One end of the first ESD device is connected to the power supply terminal VDD, and the other end is connected to the input port of the circuit;

One end of the second ESD device is connected to the ground terminal GND, and the other end is connected to the input port of the circuit;

One end of the third ESD device is connected to the power supply terminal VDD, and the other end is connected to the output port of the circuit;

One end of the fourth ESD device is connected to the ground terminal GND, and the other end is connected to the output port of the circuit;

One end of the fifth ESD device is connected to the power supply terminal VDD, and the other end is connected to one end of the impedance matching resistor;

One end of the sixth ESD device is connected to the ground terminal GND, and the other end is connected to one end of the impedance matching resistor;

The other end of the impedance matching resistor is connected to the ground terminal GND or the power supply terminal VDD.

As a further improvement, the shape of each metal coil of the on-chip multilayer inductor is square, polygonal or circular;

As a further improvement, the ESD device is a diode, a bipolar transistor, a junction field effect transistor, a MOS field effect transistor or a thyristor;

A further improvement is to adjust the ESD protection performance of the circuit and the circuit by adjusting the setting, size and size ratio of the first ESD device, the second ESD device, the third ESD device, the fourth ESD device, the fifth ESD device and the sixth ESD device Broadband features.

The technical solution of the present invention, compared with the prior art solution, mainly has the following characteristics:

First, the technical solution uses an on-chip multi-layer inductor, which benefits from the three-dimensional structure of the on-chip multi-layer inductor, and its area is greatly reduced compared with the on-chip planar inductor; the technical solution can obtain better broadband characteristics while maintaining good Excellent ESD protection performance;

Second, the ESD device in the technical solution can adopt a diode, a bipolar triode, a junction field effect transistor, a MOS field effect transistor or a thyristor;

Thirdly, by adjusting the settings of the ESD devices at the top port 108, the bottom port 109, and the middle port 110 of the inductor, and the size ratio between the ESD devices, the ESD protection performance and the circuit broadband characteristics of the circuit can be further optimized.

Description of drawings

Figure 1: A conventional ESD protection circuit using a diode device in the prior art;

Figure 2: An ESD protection circuit using on-chip planar inductors in the prior art;

Fig. 3: Structural schematic diagram of broadband ESD protection circuit of the present invention;

Figure 4: a schematic diagram of Embodiment 1 realized according to the present invention;

Figure 5: a schematic diagram of embodiment 2 realized according to the present invention;

Figure 6: a schematic diagram of Embodiment 3 realized according to the present invention;

Fig. 7: Schematic diagram of embodiment 4 realized according to the present invention.

[Description of Reference Signs]

101: on-chip multilayer inductor;

102a: a first ESD device;

102b: a second ESD device;

103a: a third ESD device;

103b: a fourth ESD device;

104a: fifth ESD device;

104b: a sixth ESD device;

105: impedance matching resistor;

106: circuit input port;

107: circuit output port;

108: Inductor top layer port;

109: Inductor bottom port;

110: middle port of inductance.

specific implementation plan

In order to make the purpose, technical solution and advantages of the present invention more clear, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. These embodiments are provided to enable a clearer and more complete understanding of the present invention, and to fully convey the scope of the present invention to those skilled in the art.

Example 1

As shown in FIG. 4 , it includes: an on-chip multilayer inductor 101, a first ESD device 102a, a second ESD device 102b, a third ESD device 103a, a fourth ESD device 103b, a fifth ESD device 104a, a sixth ESD device 104b, Impedance matching resistor 105 , circuit input port 106 and circuit output port 107 .

The number of layers of the on-chip multilayer inductor 101 is 5, and the number of turns of each metal coil is 1.

The first ESD device 102a, the second ESD device 102b, the third ESD device 103a, the fourth ESD device 103b, the fifth ESD device 104a, and the sixth ESD device 104b are diodes.

The impedance matching resistor 105 is 50 ohms, one end of which is connected to the ground terminal GND.

Example 2

As shown in Figure 5, it includes: on-chip multilayer inductor 101, first ESD device 102a, second ESD device 102b, fifth ESD device 104a, sixth ESD device 104b, impedance matching resistor 105, circuit input port 106 and circuit output port 107.

The number of layers of the on-chip multilayer inductor 101 is 5, and the number of turns of each metal coil is 1.

The first ESD device 102a, the second ESD device 102b, the fifth ESD device 104a, and the sixth ESD device 104b are diodes.

The impedance matching resistor 105 is 50 ohms, one end of which is connected to the power supply terminal VDD.

Example 3

As shown in FIG. 6 , it includes: an on-chip multilayer inductor 101 , a third ESD device 103 a , a fourth ESD device 103 b , an impedance matching resistor 105 , a circuit input port 106 and a circuit output port 107 .

The number of layers of the on-chip multilayer inductor 101 is 3, and the number of turns of each metal coil is 1.

The third ESD device 103a and the fourth ESD device 103b are diodes.

The impedance matching resistor 105 is 50 ohms, one end of which is connected to the ground terminal GND.

Example 4

As shown in FIG. 7 , it includes: an on-chip multilayer inductor 101, a first ESD device 102a, a second ESD device 102b, a third ESD device 103a, a fourth ESD device 103b, a fifth ESD device 104a, a sixth ESD device 104b, Impedance matching resistor 105 , circuit input port 106 and circuit output port 107 .

The number of layers of the on-chip multilayer inductor 101 is 5, and the number of turns of each metal coil is 1.

The first ESD device 102a, the third ESD device 103a, and the fifth ESD device 104a are P-type MOS field effect transistors; the second ESD device 102b, the fourth ESD device 103b, and the sixth ESD device 104b are N-type MOS FET;.

The impedance matching resistor 105 is 50 ohms, one end of which is connected to the ground terminal GND.

In the description of the present invention, it should be understood that the terms "first", "second", "third", "fourth", "fifth" and "sixth" are used for descriptive purposes only, and not be understood as indicating or implying relative importance or implicitly indicating the quantity of the technical feature indicated. Thus, features defined as "first", "second", "third", "fourth", "fifth", "sixth" may expressly or implicitly include one or more of such features .

In the description of this specification, the description of the terms "one embodiment", "some embodiments", "embodiment", "example", "specific example" or "some examples" refers to the A particular feature, structure, material, or characteristic is described as included in at least one embodiment or example of the invention. In this specification, the schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the described specific features, structures, materials or characteristics may be combined in any suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine different embodiments or examples and features of different embodiments or examples described in this specification without conflicting with each other.

Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present invention, those skilled in the art can make the above-mentioned The embodiments are subject to alterations, modifications, substitutions and variations.

Claims (2)

1. A broadband ESD protection circuit is characterized in that, comprising: on-chip multilayer inductor (101), ESD device, impedance matching resistor (105), circuit input port (106) and circuit output port (107); The on-chip multilayer inductor (101) is a three-dimensional multilayer spiral structure, the number of layers is 2 or more layers, and the number of turns of each metal coil is 1 or 2; The top, bottom and middle of the on-chip multilayer inductor (101) respectively have an inductor top layer port (108), an inductor bottom layer port (109) and an inductor middle port (110); The top layer port (108) of the inductor is connected to the circuit input port (106); The inductance bottom port (109) is connected to one end of the impedance matching resistor (105); The inductance intermediate port (110) is connected to the circuit output port (107); The ESD device specifically includes: a third ESD device (103a) and a fourth ESD device (103b); One end of the third ESD device (103a) is connected to the power supply terminal VDD, and the other end is connected to the circuit output port (107); One end of the fourth ESD device (103b) is connected to the ground terminal GND, and the other end is connected to the circuit output port (107); Alternatively, the ESD device specifically includes: a first ESD device (102a), a second ESD device (102b), a fifth ESD device (104a), and a sixth ESD device (104b); One end of the first ESD device (102a) is connected to the power supply terminal VDD, and the other end is connected to the circuit input port (106); One end of the second ESD device (102b) is connected to the ground terminal GND, and the other end is connected to the circuit input port (106); One end of the fifth ESD device (104a) is connected to the power supply terminal VDD, and the other end is connected to one end of the impedance matching resistor (105); One end of the sixth ESD device (104b) is connected to the ground terminal GND, and the other end is connected to one end of the impedance matching resistor (105); Alternatively, the ESD device specifically includes: a first ESD device (102a), a second ESD device (102b), a third ESD device (103a), a fourth ESD device (103b), a fifth ESD device (104a), a sixth ESD device (104b); One end of the first ESD device (102a) is connected to the power supply terminal VDD, and the other end is connected to the circuit input port (106); One end of the second ESD device (102b) is connected to the ground terminal GND, and the other end is connected to the circuit input port (106); One end of the third ESD device (103a) is connected to the power supply terminal VDD, and the other end is connected to the circuit output port (107); One end of the fourth ESD device (103b) is connected to the ground terminal GND, and the other end is connected to the circuit output port (107); One end of the fifth ESD device (104a) is connected to the power supply terminal VDD, and the other end is connected to one end of the impedance matching resistor (105); One end of the sixth ESD device (104b) is connected to the ground terminal GND, and the other end is connected to one end of the impedance matching resistor (105); The other end of the impedance matching resistor (105) is connected to the ground terminal GND or the power supply terminal VDD; The shape of each layer of metal coil of the on-chip multilayer inductor (101) is square, polygonal or circular; The ESD device is a diode, a bipolar triode, a junction field effect transistor, a MOS field effect transistor or a thyristor. 2. A kind of broadband ESD protection circuit according to claim 1, is characterized in that, by adjusting the first ESD device (102a), the second ESD device (102b), the 3rd ESD device (103a), the 4th ESD device (103b), the arrangement, size and size ratio of the fifth ESD device (104a) and the sixth ESD device (104b) adjust the ESD protection performance and circuit broadband characteristics of the circuit.

Images