CN100442507C - A symmetrical inductance component - Google Patents
A symmetrical inductance component Download PDFInfo
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- CN100442507C CN100442507C CNB2006101672891A CN200610167289A CN100442507C CN 100442507 C CN100442507 C CN 100442507C CN B2006101672891 A CNB2006101672891 A CN B2006101672891A CN 200610167289 A CN200610167289 A CN 200610167289A CN 100442507 C CN100442507 C CN 100442507C
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Abstract
The disclosed symmetric inductance element comprises: the first and second winding parts every with three semi-cycle wire layers, and a couple part with two couple of connection layers. Wherein, every semi-cycle wire layer includes two ends, and the first end of the first semi-cycle wire layer is coupled; the first couple connection layer crossed connects the first ends of the second and third semi-cycle wire layers; and the second couple connection layer crossed connects the second ends of the first and second semi-cycle wire layers. This invention can reduce parasitic capacitance effect and improves element frequency range.
Description
Technical field
The present invention particularly operates the symmetrical inductance element of (differential operation) relevant for a kind of semiconductor device relevant for a kind of differential-type.
Background technology
Many numerals and analog component and circuit successfully apply to semiconductor integrated circuit.Above-mentioned parts have comprised passive device, for example resistance, electric capacity or inductance etc.Typical semiconductor integrated circuit comprises a silicon base.The above dielectric layer of one deck is arranged in the substrate, and the above metal level of one deck is arranged in the dielectric layer.These metal levels can form the chip built-in parts by existing manufacture of semiconductor technology, for example chip built-in inductance element (on-chip inductor).
Traditionally, the chip built-in inductance is formed in the substrate and applies to radio frequency band (radio frequency band) integrated circuit (IC) design.Please refer to Fig. 1, wherein Fig. 1 shows a known chip built-in inductance element floor map with snail structure.Chip built-in inductance element is formed in the insulating barrier 104 of a substrate 100 tops, and it comprises a spiral metal layer 103 and an internal connection-wire structure.Spiral metal layer 103 is embedded in the insulating barrier 104.Internal connection-wire structure comprises the conductive plunger 105 that embeds in the layer insulating (not illustrating) down and 109 and metal level 107 and the metal level 111 that is embedded in the insulating barrier 104.Spiral metal layer 103 by conductive plunger 105 and 109 and metal level 107 and 111 form a current path, to electrically connect with chip exterior or internal circuit.
The advantage of plane helical inductance element is and can be positioned at the integrated level that circuit element quantity that chip builds and required complicated intraconnections thereof increase circuit outward by minimizing.Moreover the plane spiral inductance can avoid chip built-in circuit and chip to build the ghost effect that joint sheet between (off-chip) circuit (bond pad) or wiring (bond wire) are produced outward.
The quality factor of above-mentioned plane spiral inductance (quality factor/Q value) are low and area is big.For the Q value of further improving inductance and reduce area, the someone proposes the inner ring and the line-spacing between the outer ring (trace space) S that increase the thickness of spiral metal layer 103 and dwindle spiral metal layer 103.
Yet increasing wireless telecommunications design uses differential circuit reducing common mode (common mode) noise, and the inductance that applies to above-mentioned differential circuit is required to be symmetrical expression and prevents that common-mode noise from producing.That is inductance is watched from arbitrary end points all has same structure.Plane spiral inductance among Fig. 1 is not to be symmetrical expression, if be applied to then effective noise insulation of differential circuit.
Summary of the invention
In view of this, the invention provides a kind of symmetrical inductance element, produce to prevent common-mode noise.Simultaneously, by changing the line-spacing of coil (coil) in the inductance, to increase inductance element available frequencies scope.
According to above-mentioned purpose, the invention provides a kind of symmetrical inductance element, comprising: insulating barrier, first winding section and second winding section and couplings.Insulating barrier is arranged in the substrate.First winding section and second winding section are symmetrically set in insulating barrier.Each winding section comprises the first half-turn shape conductor layer, the second half-turn shape conductor layer and the 3rd half-turn shape conductor layer of concentric arrangement from inside to outside.Each half-turn shape conductor layer has first end and second end, and wherein first end of the first half-turn shape conductor layer couples mutually.Couplings is arranged in the insulating barrier between first winding section and second winding section, comprising: first pair of articulamentum and second pair of articulamentum.First pair of articulamentum is cross-linked second half-turn shape conductor layer of two winding sections and first end of the 3rd half-turn shape conductor layer.Second pair of articulamentum is cross-linked first half-turn shape conductor layer of two winding sections and second end of the second half-turn shape conductor layer.Have line-spacing between the adjacent half-turn shape conductor layer in each winding section, and the line-spacing that is positioned at the outside is greater than being positioned at inboard line-spacing.
According to above-mentioned purpose, the invention provides a kind of symmetrical inductance element, comprise insulating barrier, a plurality of half-turn shape conductor layer, at least one first pair of articulamentum and at least one second pair of articulamentum, and have line-spacing between two wherein adjacent these half-turn shape conductor layers, and the line-spacing outside being positioned at is greater than being positioned at inboard line-spacing.In addition, concentric arrangement is in this insulating barrier from inside to outside for a plurality of half-turn shape conductor layers, and each half-turn shape conductor layer has first end and second end, and described first end that wherein is positioned at two the most inboard half-turn shape conductor layers couples mutually.First pair of articulamentum connects described first end of described a plurality of half-turn shape conductor layers, and second pair of articulamentum, connects described second end of described a plurality of half-turn shape conductor layers.
According to above-mentioned purpose, the invention provides a kind of symmetrical inductance element, comprise insulating barrier, first winding section, second winding section and two half-turn shape conductor layers, wherein first winding section is to place in the insulating barrier, have a plurality of conductor layers, and second winding section is to place in the insulating barrier, and is symmetrical in this first winding section, and has a plurality of conductor layers.In addition, have line-spacing between these two half-turn shape conductor layers and the winding section that is adjacent, and this line-spacing is greater than the line-spacing between two adjacent in this winding section these conductor layers.These two half-turn shape conductor layers are to place in the insulating barrier, and lay respectively at the outside of this first winding section and this second winding section, are electrically connected at this first winding section and this second winding section respectively.
Symmetrical inductance element provided by the present invention when differential wave is operated, can reduce parasitic capacitance effect, increases inductance element available frequencies scope.
Description of drawings
Fig. 1 shows known chip built-in inductance element floor map with snail structure.
Fig. 2 shows three a circles symmetry inductance element floor map according to the embodiment of the invention.
Fig. 3 shows four a circles symmetry inductance element floor map according to the embodiment of the invention.
Fig. 4 shows four a circles symmetry inductance element floor map according to the embodiment of the invention.
Fig. 5 shows four a circles symmetry inductance element floor map according to the embodiment of the invention.
Embodiment
Below cooperate Fig. 2 that the floor map of the three circles symmetry inductance element of the embodiment of the invention is described.The symmetry inductance element comprises: an insulating barrier 210, first winding section and second winding section and a couplings.Insulating barrier 210 is arranged in the substrate 200.Substrate 200 comprises a silicon base or other known semiconductor substrates.Can comprise various element in the substrate 200, for example transistor, resistance and other semiconductor elements commonly used.Moreover substrate 200 also can comprise other conductive layers (for example, copper, aluminium or its alloy) and insulating barrier (for example, silicon oxide layer, silicon nitride layer or low dielectric material layer).For simplicity of illustration, only represent with a smooth substrate herein.In addition, insulating barrier 210 can be an individual layer low dielectric material layer or a multilayered dielectric structure.In the present embodiment, insulating barrier 210 can comprise silicon oxide layer, silicon nitride layer or low dielectric material layer.
First winding section is arranged in the insulating barrier 210, and is positioned at one first side of dotted line 2.First winding section comprises the first half-turn shape conductor layer 201, the second half-turn shape conductor layer 203 and the 3rd half-turn shape conductor layer 205 of concentric arrangement from inside to outside.Second winding section is arranged in the insulating barrier 210, and is positioned at second side with respect to first side of dotted line 2.Second winding section comprises the first half-turn shape conductor layer 202, the second half-turn shape conductor layer 204 and the 3rd half-turn shape conductor layer 206 of concentric arrangement from inside to outside.Second winding section is that symmetry axis is symmetrical in first winding section with dotted line 2.
First winding section and second winding section can constitute and be roughly circle, rectangle, hexagon, octagon or polygonal profile., being simplicity of illustration herein, is to illustrate as example with octagon.Moreover the material of first winding section and second winding section can be made of copper, aluminium or its alloy.In the present embodiment, the first half-turn shape conductor layer 201, the second half-turn shape conductor layer 203 and the 3rd half-turn shape conductor layer 205 of first winding section can have identical live width W with the first half-turn shape conductor layer 202, the second half-turn shape conductor layer 204 and the 3rd half-turn shape conductor layer 206 of second winding section.
Each half-turn shape conductor layer has one first end 10 and one second end 20.In the present embodiment, first end 10 of the first half-turn shape conductor layer 202 of first end 10 of the first half-turn shape conductor layer 201 of first winding section and second winding section couples mutually.Moreover the 3rd half-turn shape conductor layer 205 of first winding section and second winding section and 206 second end 20 have one and extend laterally portion 30 and 40, in order to as signal I/O end, in order to the input differential wave.
In the present embodiment, in order to keep inductance element geometrical symmetry (geometricsymmetry), couplings is arranged in the insulating barrier 210 between first winding section and second winding section, it comprises first pair of articulamentum and second pair of articulamentum.First pair of articulamentum is cross-linked second half-turn shape conductor layer 203 of two winding sections and first end 10 of the 204 and the 3rd half-turn shape conductor layer 205 and 206.Moreover second pair of articulamentum is cross-linked first half-turn shape conductor layer 201 of two winding sections and second end 20 of the 202 and second half-turn shape conductor layer 203 and 204.For example, the first pair of articulamentum comprises that cross-over connection layer 215 on couples first end 10 of the second half-turn shape conductor layer 203 and the 3rd half-turn shape conductor layer 206, and once cross-over connection layer 217 couples first end 10 of the second half-turn shape conductor layer 204 and the 3rd half-turn shape conductor layer 205.The second pair of articulamentum comprises that cross-over connection layer 213 on couples second end 20 of the first half-turn shape conductor layer 201 and the second half-turn shape conductor layer 204, and once cross-over connection layer 211 couples second end 20 of the first half-turn shape conductor layer 202 and the second half-turn shape conductor layer 203.
Generally speaking, because adjacent metal wire winding layer (winding) is understood the signal by same phase in the inductance element of single-ended signal operation (single-ended signaloperation), so need not consider the parasitic capacitance effect (parasitic capacitance effect) between the adjacent metal wire winding layer.Therefore, the line-spacing between the metal wire winding layer must dwindle as much as possible, to improve the usefulness of inductance element.Yet, the inductance element that is different from the single-ended signal operation, wire winding layer adjacent in the inductance element of differential wave operation can be by having the signal that 180 degree differ, therefore need parasitic capacitance effect, the particularly parasitic capacitance effect that between outermost metal wire winding layer, is produced between the consideration adjacent metal wire winding layer.When the parasitic capacitance between the outermost metal wire winding layer increases, peak value quality factor frequency (peak Q-factor frequency) can descend and increase inductance deviation (inductance value deviation), thereby has limited inductance element available frequencies scope.
Therefore, in the symmetrical inductance element of present embodiment, have a line-spacing between the adjacent half-turn shape conductor layer in each winding section, and the line-spacing at least one relative outside is greater than the line-spacing of at least one relative inner.For example, the line-spacing S2 between the second half-turn shape conductor layer 203 and the 204 and the 3rd half-turn shape conductor layer 205 and 206 is greater than (that is S2＞S1), of the line-spacing S1 between the second half-turn shape conductor layer 203 and the 204 and first half-turn shape conductor layer 201 and 202.Thus,,, make symmetrical inductance element when differential wave is operated, can reduce parasitic capacitance effect, and increase inductance element available frequencies scope because outermost line-spacing S2 increases according to symmetrical inductance element of the present invention.
Below cooperate Fig. 3 that the four circles symmetry inductance element of other embodiments of the invention is described, the parts that wherein are same as among Fig. 2 are to use identical label and omit its explanation.In Fig. 3, first winding section and second winding section more comprise the 4th half-turn shape conductor layer 207 and 208, and it lays respectively at the outside of the 3rd half-turn shape conductor layer 205 and 206.Similarly, the 4th half-turn shape conductor layer 207 and 208 can have identical live width W.Moreover couplings more comprises one the 3rd pair of articulamentum, is cross-linked the 3rd half-turn shape conductor layer 205 of two winding sections and second end 20 of the 206 and the 4th half-turn shape conductor layer 207 and 208.For example, the 3rd pair of articulamentum comprises that cross-over connection layer 219 on couples second end 20 of the 3rd half-turn shape conductor layer 205 and the 4th half-turn shape conductor layer 208, and once cross-over connection layer 221 couples second end 20 of the 3rd half-turn shape conductor layer 206 and the 4th half-turn shape conductor layer 207.Moreover the 4th half-turn shape conductor layer 207 of first winding section and second winding section and 208 first end 10 have one and extend laterally portion 30 and 40, in order to as signal I/O end, in order to the input differential wave.
In the present embodiment, line-spacing from inside to outside increases gradually.For example, the line-spacing S3 between the 3rd half-turn shape conductor layer 205 and the 206 and the 4th half-turn shape conductor layer 207 and 208 is greater than the line-spacing S2 between the second half-turn shape conductor layer 203 and the 204 and the 3rd half-turn shape conductor layer 205 and 206.Moreover the line-spacing S2 between the second half-turn shape conductor layer 203 and the 204 and the 3rd half-turn shape conductor layer 205 and 206 is greater than (that is S3＞the S2＞S1), of the line-spacing S1 between the second half-turn shape conductor layer 203 and the 204 and first half-turn shape conductor layer 201 and 202.
In other embodiments, line-spacing S3 can be same as substantially line-spacing S2 and greater than line-spacing S1 (that is, and S3=S2＞S1), as shown in Figure 4.Again, in other embodiments, line-spacing S2 can be same as substantially line-spacing S1 and less than line-spacing S3 (that is, and S3＞S2=S1), as shown in Figure 5.Thus,, make symmetrical inductance element when differential wave is operated, can reduce parasitic capacitance effect, and increase inductance element available frequencies scope because the adjacent wire winding layer of outermost has maximum line-spacing.In addition, those skilled in the art can recognize easily that the present invention applies to also have identical advantage in the above symmetrical inductance element of other four circles.
The above only is preferred embodiment of the present invention; so it is not in order to limit scope of the present invention; any personnel that are familiar with this technology; without departing from the spirit and scope of the present invention; can do further improvement and variation on this basis, so the scope that claims were defined that protection scope of the present invention is worked as with the application is as the criterion.
Being simply described as follows of symbol in the accompanying drawing:
100: substrate
103: the spiral metal layer
104: insulating barrier
105,109: conductive plunger
107,111: metal level
S: line-spacing
2: dotted line
10: the first ends
20: the second ends
30,40: extend laterally portion
200: substrate
201,202: the first half-turn shape conductor layers
203,204: the second half-turn shape conductor layers
205,206: the three half-turn shape conductor layers
207,208: the four half-turn shape conductor layers
210: insulating barrier
211,217,221: following cross-over connection layer
213,215,219: go up the cross-over connection layer
S1, S2, S3: line-spacing
W: live width
Claims (10)
1. symmetrical inductance element, described symmetrical inductance element comprises:
Insulating barrier is arranged in the substrate; It is characterized in that,
First winding section and second winding section, be symmetrically set in this insulating barrier, each winding section comprises the first half-turn shape conductor layer, the second half-turn shape conductor layer and the 3rd half-turn shape conductor layer of concentric arrangement from inside to outside, and each half-turn shape conductor layer has one first end and one second end, and described first end of the wherein said first half-turn shape conductor layer couples mutually; And
Couplings is arranged in this insulating barrier between this first winding section and this second winding section, comprising:
First pair of articulamentum is cross-linked this second half-turn shape conductor layer of two winding sections and described first end of the 3rd half-turn shape conductor layer; And
Second pair of articulamentum is cross-linked described second end of this first half-turn shape conductor layers of two winding sections and this second half figure conductor layers;
Wherein have line-spacing between the adjacent described half-turn shape conductor layer in each described winding section, and the line-spacing that is positioned at the outside is greater than being positioned at inboard line-spacing.
2. symmetrical inductance element according to claim 1, it is characterized in that, described first winding section and second winding section comprise that more the 4th half-turn shape conductor layer is positioned at the outside of the 3rd half-turn shape conductor layer, and this couplings more comprises the 3rd pair of articulamentum, is cross-linked the 3rd half-turn shape conductor layer of two winding sections and described second end of the 4 half figure conductor layer.
3. symmetrical inductance element according to claim 2, it is characterized in that, line-spacing between the 4th half-turn shape conductor layer and the 3rd half-turn shape conductor layer is same as the line-spacing between the 3rd half-turn shape conductor layer and this second half-turn shape conductor layer, and greater than the line-spacing between this second half figure conductor layer and this first half-turn shape conductor layer.
4. symmetrical inductance element according to claim 2, it is characterized in that, line-spacing between this first half-turn shape conductor layer and this second half-turn shape conductor layer is same as the line-spacing between the 3 half figure conductor layer and this second half-turn shape conductor layer, and less than the line-spacing between the 4 half figure conductor layer and the 3 half figure conductor layer.
5. symmetrical inductance element, described symmetrical inductance element comprises:
Insulating barrier; It is characterized in that,
A plurality of half-turn shape conductor layers, concentric arrangement is in this insulating barrier from inside to outside for it, and each half-turn shape conductor layer has first end and second end, described first end that wherein is positioned at two and half the most inboard figure conductor layers couples mutually;
At least one first pair of articulamentum connects described first end of described a plurality of half-turn shape conductor layers; And
At least one second pair of articulamentum connects described second end of described a plurality of half-turn shape conductor layers;
Have line-spacing between wherein adjacent two these half-turn shape conductor layers, and the line-spacing outside being positioned at is greater than being positioned at inboard line-spacing.
6. symmetrical inductance element, described symmetrical inductance element comprises:
Insulating barrier; It is characterized in that,
First winding section, it places in this insulating barrier, and has a plurality of conductor layers;
Second winding section, it places in this insulating barrier, and is symmetrical in this first winding section, and has a plurality of conductor layers; And
Two half-turn shape conductor layers, it is arranged in this insulating barrier, and lays respectively at the outside of this first winding section and this second winding section, and wherein these two half-turn shape conductor layers are electrically connected at this first winding section and this second winding section respectively;
Wherein have line-spacing between these two half-turn shape conductor layers and the winding section that is adjacent, and this line-spacing is greater than the line-spacing between two adjacent in this winding section these conductor layers.
7. symmetrical inductance element according to claim 6, it is characterized in that, each winding section comprises the first half-turn shape conductor layer, the second half-turn shape conductor layer and the 3rd half-turn shape conductor layer of concentric arrangement from inside to outside, and each half-turn shape conductor layer has first end and second end, and described first end of the wherein said first half-turn shape conductor layer couples mutually.
8. symmetrical inductance element according to claim 7 is characterized in that it more comprises couplings, be arranged in this insulating barrier between this first winding section and this second winding section, and this couplings comprises:
First pair of articulamentum is cross-linked this second half-turn shape conductor layer of two winding sections and described first end of the 3rd half-turn shape conductor layer; And
Second pair of articulamentum is cross-linked this first half-turn shape conductor layer of two winding sections and described second end of this second half-turn shape conductor layer.
9. symmetrical inductance element according to claim 8 is characterized in that, this first pair of articulamentum and second pair of articulamentum include the cross-over connection layer and reach cross-over connection layer down.
10. symmetrical inductance element according to claim 7, it is characterized in that, described first winding section and second winding section comprise that more the 4th half-turn shape conductor layer is positioned at the outside of the 3 half figure conductor layer, and this couplings more comprises the 3rd pair of articulamentum, is cross-linked the 3rd half-turn shape conductor layer of two winding sections and described second end of the 4th half-turn shape conductor layer.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101672891A CN100442507C (en) | 2006-12-15 | 2006-12-15 | A symmetrical inductance component |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2006101672891A CN100442507C (en) | 2006-12-15 | 2006-12-15 | A symmetrical inductance component |
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| CN1964043A CN1964043A (en) | 2007-05-16 |
| CN100442507C true CN100442507C (en) | 2008-12-10 |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101145435B (en) * | 2007-08-23 | 2010-08-25 | 威盛电子股份有限公司 | Inductance structure |
| US20150340148A1 (en) * | 2014-05-23 | 2015-11-26 | Infineon Technologies Ag | Inductor and method of forming an inductor |
| CN106876379B (en) * | 2016-07-07 | 2019-10-08 | 威盛电子股份有限公司 | Semiconductor device with a plurality of semiconductor chips |
| CN112838859A (en) * | 2019-11-22 | 2021-05-25 | 瑞昱半导体股份有限公司 | Inductance-capacitance oscillator and common mode resonant cavity |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1606127A (en) * | 2004-10-28 | 2005-04-13 | 复旦大学 | Method for designing low parasitic capacity differential driving symmetrical inductance through standard integrated circuit process |
| CN1723513A (en) * | 2002-12-13 | 2006-01-18 | 皇家飞利浦电子股份有限公司 | A planar inductive component and an integrated circuit comprising a planar inductive component |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1723513A (en) * | 2002-12-13 | 2006-01-18 | 皇家飞利浦电子股份有限公司 | A planar inductive component and an integrated circuit comprising a planar inductive component |
| CN1606127A (en) * | 2004-10-28 | 2005-04-13 | 复旦大学 | Method for designing low parasitic capacity differential driving symmetrical inductance through standard integrated circuit process |
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