CN112802803A - High-yield wafer-level filter chip packaging structure and method - Google Patents
High-yield wafer-level filter chip packaging structure and method Download PDFInfo
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- CN112802803A CN112802803A CN202110141437.7A CN202110141437A CN112802803A CN 112802803 A CN112802803 A CN 112802803A CN 202110141437 A CN202110141437 A CN 202110141437A CN 112802803 A CN112802803 A CN 112802803A
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- wafer
- cofferdam
- cover
- welding
- filter chip
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 24
- 238000000034 method Methods 0.000 title claims abstract description 20
- 229910052751 metal Inorganic materials 0.000 claims abstract description 33
- 239000002184 metal Substances 0.000 claims abstract description 33
- 238000003466 welding Methods 0.000 claims abstract description 25
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 23
- 229910052737 gold Inorganic materials 0.000 claims abstract description 23
- 239000010931 gold Substances 0.000 claims abstract description 23
- 229910000679 solder Inorganic materials 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 238000005520 cutting process Methods 0.000 claims description 12
- 239000011810 insulating material Substances 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 8
- 230000008719 thickening Effects 0.000 claims description 7
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 238000007789 sealing Methods 0.000 claims description 5
- 239000010936 titanium Substances 0.000 claims description 5
- 229910052719 titanium Inorganic materials 0.000 claims description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 239000010949 copper Substances 0.000 claims description 4
- 239000003292 glue Substances 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 4
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052804 chromium Inorganic materials 0.000 claims description 3
- 239000011651 chromium Substances 0.000 claims description 3
- 238000009713 electroplating Methods 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 claims description 3
- 229910052763 palladium Inorganic materials 0.000 claims description 3
- 238000007747 plating Methods 0.000 claims description 3
- 229920000642 polymer Polymers 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract 1
- 239000000463 material Substances 0.000 description 5
- 230000003064 anti-oxidating effect Effects 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 3
- 230000002265 prevention Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000007731 hot pressing Methods 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000005022 packaging material Substances 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
Abstract
The invention discloses a high-yield wafer-level filter chip packaging structure and a method, wherein a filter chip and a substrate are connected, the filter chip comprises a wafer, a plurality of welding pads, a cofferdam and a cover, the welding pads are arranged beside the wafer, the cofferdam is arranged at the periphery of the wafer, the cover is arranged above the cofferdam, the cover is tightly attached to the upper part of the cofferdam, a sealed cavity is formed among the wafer, the cofferdam and the cover, a welding layer is electroplated or chemically plated on the welding pads, and a tin ball or a gold ball is arranged above the welding layer; the base plate is provided with a plurality of metal pads and solder resist oil, the metal pads are welded with the solder balls or the gold balls, grooves are formed among the metal pads, and the covers are arranged in the grooves. According to the invention, a plurality of cavity environments are provided for the wafer, the strength of the cover is improved, the qualified efficiency of the product is improved, and the packaging cost can be greatly reduced; solder balls or gold balls are implanted on the bonding pads on the chip surface, so that the qualified efficiency in the flip process can be greatly improved.
Description
Technical Field
The present invention relates to semiconductor packages, and more particularly to a wafer level filter chip package and method with high yield.
Background
With the increasing number of modes and frequency bands supported by wireless mobile communication systems, the radio frequency front end architecture of current wireless communication mobile terminals is becoming more and more complex. The examination of front-end semiconductor modularization is becoming more and more popular. Due to the limitation of space of equipment and terminals, the newly added radio frequency front end in the 5G era mainly appears in a module form, and more devices are integrated in the module. The traditional filter package (including metal casing package, plastic package or surface mount package, etc.) has a large product size and relatively high cost, and the matching of each product is inconsistent, so that the requirements of the terminal cannot be met gradually.
Disclosure of Invention
In order to solve the technical problem, an embodiment of the present invention provides a high yield wafer-level filter chip packaging structure, which includes a filter chip and a substrate, wherein the filter chip is connected to the substrate, the filter chip includes a wafer, a plurality of bonding pads, a cofferdam and a cover, the bonding pads are disposed beside the wafer, the cofferdam is disposed around the wafer, the cover is disposed above the cofferdam, the cover is tightly attached to the upper portion of the cofferdam, a sealed cavity is formed among the wafer, the cofferdam and the cover, a welding layer is electroplated or chemically plated on the bonding pads, and solder balls or gold balls are disposed above the welding layer;
the base plate is provided with a plurality of metal pads and solder resist oil, the metal pads are welded with the solder balls or the gold balls, grooves are formed among the metal pads, and the covers are arranged in the grooves.
Further, the thickness of the cofferdam is more than or equal to 1 um.
Further, the bonding pad comprises an adhesion layer, a thickening layer and an oxidation prevention layer.
Furthermore, the adhesion layer adopts metal titanium or/and metal chromium, the thickening layer adopts metal copper or/and metal nickel, and the anti-oxidation layer adopts metal gold or/and metal palladium.
Further, the thickness of the cover is larger than or equal to 1um, and the cover and the cofferdam are made of insulating materials.
Furthermore, the insulating material is a high-molecular insulating material.
Also provided is a high yield filter chip packaging method, comprising:
step 1: manufacturing the cofferdam on the wafer by adopting a glue coating, exposing and developing technology, wherein the cofferdam surrounds the wafer;
step 2: adopting a film-pasting exposure and development method to manufacture the cover on the cofferdam, and forming a sealing cavity among the chip, the cofferdam and the cover;
and step 3: arranging a welding layer on the welding pad by adopting electroplating or chemical plating;
and 4, step 4: manufacturing a solder ball or a gold ball on the welding layer by adopting a ball mounting process to form a filter chip;
and 5: connecting a metal pad on the substrate with the solder ball or the gold ball by adopting a reverse chip bonding process;
step 6: plastically packaging the substrate and the filter chip in a plastic packaging mode;
and 7: and cutting the substrate according to the packaging area to obtain cutting units, wherein each cutting unit comprises the substrate and the chip in the packaging area, and the cutting units are filters.
The embodiment of the invention has the following beneficial effects: according to the invention, a sealed cavity is formed among the wafer, the cofferdam and the cover, and the cofferdam and the cover are made of high polymer insulating materials to protect the chip electrodes; the solder balls or gold balls are connected to the solder pads of the chip, so that the chip and the substrate can be conveniently packaged. According to the invention, a plurality of cavity environments are provided for the wafer, the strength of the cover is improved, the qualified efficiency of the product is improved, and the packaging cost can be greatly reduced; solder balls or gold balls are implanted on the bonding pads on the chip surface, so that the qualified efficiency in the flip process can be greatly improved.
Drawings
In order to more clearly illustrate the high yield wafer level filter chip package structure and method of the present invention, the drawings required for the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic cross-sectional view of a filter chip according to the present invention;
FIG. 2 is a schematic diagram of a filter chip according to the present invention;
FIG. 3 is a schematic view of a substrate structure according to the present invention;
FIG. 4 is a cross-sectional view of a high yield wafer level filter chip package structure according to the present invention;
fig. 5 is a flowchart of a high yield wafer level filter chip packaging method.
The drawings are numbered as follows:
1-a wafer; 2-cofferdam; 3-a lid; 4-a bond pad; 5-tin or gold balls; 6-a substrate; 7-a pad; 8-a groove; 9-sealing the cavity; 10-solder layer.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
Example 1:
as shown in fig. 1 to 4, a high yield wafer level 1 filter chip package structure, a filter chip and a substrate 6, wherein the filter chip is connected to the substrate 6, the filter chip includes a wafer 1, a plurality of pads 4, a cofferdam 2 and a cover 3, the pads 4 are disposed beside the wafer 1 and provided with the pads 4, the periphery of the wafer 1 is provided with the cofferdam 2, the cover 3 is disposed above the cofferdam 2, the cover 3 is tightly attached above the cofferdam 2, a sealed cavity 9 is formed among the wafer 1, the cofferdam 2 and the cover 3, a welding layer 10 is electroplated or chemically plated on the pads 4, and a solder ball or a gold ball 5 is disposed above the welding layer 10;
the base plate 6 is provided with a plurality of metal pads 7 and solder resist oil, the metal pads 7 are welded with the solder balls or the gold balls 5, grooves 8 are formed among the metal pads 7, and the covers are arranged in the grooves 8.
Specifically, the cofferdam 2 surrounds the wafer 1, and the outer layer edge of the cover 3 is retracted a distance in a plane angle range from 0 to 25um in comparison with the outer layer edge of the cofferdam 2, so that the wafer is convenient to flip; the groove is used for placing the surface 1 of the wafer of the filter chip.
Specifically, the thickness of the cofferdam 2 is greater than or equal to 1um, so as to prevent the cover 3 from contacting the wafer 1.
Further, the bonding pad 4 includes an adhesion layer, a thickening layer and an oxidation prevention layer, the adhesion layer adopts metal titanium or/and metal chromium, the thickening layer adopts metal copper or/and metal nickel, and the oxidation prevention layer adopts metal gold or/and metal palladium, so that ball planting of the bonding pad 4 is facilitated.
Specifically, the adhesion layer is made of metal titanium, and the thickness of the metal titanium adhesion layer is 0.1-0.4 um; the thickening layer comprises a conductive layer and a blocking layer, the conductive layer comprises metal copper, the thickness of the conductive layer is greater than 1um, the blocking layer comprises metal nickel, and the thickness of the blocking layer is 1um-4 um; the anti-oxidation layer is preferably made of metal gold, the anti-oxidation effect is good, and the thickness of the anti-oxidation layer is generally 0.05-1 um.
Further, the thickness of the cover 3 is larger than or equal to 1um, and the cover 3 and the cofferdam 2 are made of insulating materials.
Further, the insulating material is preferably a polymer insulating material, and the cover 3 is made of a dry film material.
Example 2:
as shown in fig. 5, a high yield filter chip packaging method includes:
step 1: manufacturing the cofferdam 2 on the wafer 1 by adopting a glue coating, exposing and developing technology, wherein the cofferdam 2 surrounds the wafer 1; the dam 2 is arranged between the wafer 1 and the bonding pad 4, the glue coating rotating speed formed by the dam 2 is between 500-.
Step 2: adopting a film-pasting exposure and development method to manufacture the cover 3 on the cofferdam 2, and forming a sealing cavity 9 among the chip, the cofferdam 2 and the cover 3; the cover 3 is preferably made of dry film material, and the outer layer edge of the cover 3 is retracted a distance from the outer layer edge of the cofferdam 2 at a plane angle, so that the cover can be inverted conveniently.
And step 3: arranging a welding layer 10 on the welding pad 4 by adopting electroplating or chemical plating; the ball planting in the step 4 is convenient.
And 4, step 4: manufacturing a solder ball or a gold ball 5 on the welding layer 10 by adopting a ball mounting process to form a filter chip; the solder ball is heated to 280 ℃, melted and then welded on the welding layer 10; or the gold ball is fixed with the welding layer 10 in a hot-pressing ultrasonic mode.
And 5: connecting a metal pad 7 on the substrate 6 with the solder ball or the gold ball 5 by adopting a reverse chip bonding process;
step 6: the substrate 6 and the filter chip are plastically packaged in a plastic packaging mode; the plastic packaging material generally adopts epoxy material, and epoxy material price is lower, and the encapsulation is convenient, and mobility is good, with the whole closing caps of filter chip, the filter chip with epoxy material has all been annotated to the clearance between the base plate upper groove, and stability is good, the filter is kept away from 1 one side plastic packaging thickness of wafer and is greater than 50um, the plastic packaging thickness of filter chip lateral wall is greater than 50 um.
And 7: and cutting the substrate 6 according to the packaging area to obtain cutting units, wherein each cutting unit comprises the substrate 6 and the chip in the packaging area, and the cutting units are filters.
The foregoing description has disclosed fully preferred embodiments of the present invention. It should be noted that those skilled in the art can make modifications to the embodiments of the present invention without departing from the scope of the appended claims. Accordingly, the scope of the appended claims is not to be limited to the specific embodiments described above.
Claims (7)
1. A high-yield wafer-level filter chip packaging structure is characterized by comprising a filter chip and a substrate, wherein the filter chip is connected with the substrate and comprises a wafer, a plurality of welding pads, cofferdams and covers, the welding pads are arranged beside the wafer, the cofferdams are arranged around the wafer, the covers are arranged above the cofferdams, the covers are tightly attached to the upper portions of the cofferdams, sealing cavities are formed among the wafer, the cofferdams and the covers, welding layers are electroplated or chemically plated on the welding pads, and solder balls or gold balls are arranged above the welding layers;
the base plate is provided with a plurality of metal pads and solder resist oil, the metal pads are welded with the solder balls or the gold balls, grooves are formed among the metal pads, and the covers are arranged in the grooves.
2. The structure of claim 1, wherein the dam thickness is greater than or equal to 1 um.
3. The package structure of claim 1, wherein the bonding pad comprises an adhesion layer, a thickening layer, and an oxidation preventing layer.
4. The package structure of claim 3, wherein the adhesion layer is made of titanium or/and chromium, the thickening layer is made of copper or/and nickel, and the oxidation preventing layer is made of gold or/and palladium.
5. The structure of claim 1, wherein the thickness of the cover is greater than or equal to 1um, and the cover and the dam are made of an insulating material.
6. The structure of claim 5, wherein the insulating material is a polymer insulating material.
7. A high-yield wafer-level filter chip packaging method is characterized by comprising the following steps:
step 1: manufacturing the cofferdam on the wafer by adopting a glue coating, exposing and developing technology, wherein the cofferdam surrounds the wafer;
step 2: adopting a film-pasting exposure and development method to manufacture the cover on the cofferdam, and forming a sealing cavity among the chip, the cofferdam and the cover;
and step 3: arranging a welding layer on the welding pad by adopting electroplating or chemical plating;
and 4, step 4: manufacturing a solder ball or a gold ball on the welding layer by adopting a ball mounting process to form a filter chip;
and 5: connecting a metal pad on the substrate with the solder ball or the gold ball by adopting a reverse chip bonding process;
step 6: plastically packaging the substrate and the filter chip in a plastic packaging mode;
and 7: and cutting the substrate according to the packaging area to obtain cutting units, wherein each cutting unit comprises the substrate and the chip in the packaging area, and the cutting units are filters.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110141437.7A CN112802803A (en) | 2021-02-01 | 2021-02-01 | High-yield wafer-level filter chip packaging structure and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110141437.7A CN112802803A (en) | 2021-02-01 | 2021-02-01 | High-yield wafer-level filter chip packaging structure and method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112802803A true CN112802803A (en) | 2021-05-14 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110141437.7A Pending CN112802803A (en) | 2021-02-01 | 2021-02-01 | High-yield wafer-level filter chip packaging structure and method |
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| Country | Link |
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| CN (1) | CN112802803A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113451427A (en) * | 2021-06-09 | 2021-09-28 | 佛山市国星半导体技术有限公司 | Light detector chip interdigital electrode based on GaN micrometer line array, light detector chip and preparation method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10270975A (en) * | 1996-03-08 | 1998-10-09 | Matsushita Electric Ind Co Ltd | Electronic part and its manufacture |
| CN106888001A (en) * | 2017-03-08 | 2017-06-23 | 宜确半导体（苏州）有限公司 | Acoustic wave device and its wafer-level packaging method |
| TW201730994A (en) * | 2015-12-08 | 2017-09-01 | 天工方案公司 | Method of providing protective cavity and integrated passive components in wafer-level chip-scale package using a carrier wafer |
| CN110759311A (en) * | 2019-10-29 | 2020-02-07 | 太极半导体（苏州）有限公司 | Leadless MEMS chip packaging structure based on window type substrate and process thereof |
-
2021
- 2021-02-01 CN CN202110141437.7A patent/CN112802803A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10270975A (en) * | 1996-03-08 | 1998-10-09 | Matsushita Electric Ind Co Ltd | Electronic part and its manufacture |
| TW201730994A (en) * | 2015-12-08 | 2017-09-01 | 天工方案公司 | Method of providing protective cavity and integrated passive components in wafer-level chip-scale package using a carrier wafer |
| CN106888001A (en) * | 2017-03-08 | 2017-06-23 | 宜确半导体（苏州）有限公司 | Acoustic wave device and its wafer-level packaging method |
| CN110759311A (en) * | 2019-10-29 | 2020-02-07 | 太极半导体（苏州）有限公司 | Leadless MEMS chip packaging structure based on window type substrate and process thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113451427A (en) * | 2021-06-09 | 2021-09-28 | 佛山市国星半导体技术有限公司 | Light detector chip interdigital electrode based on GaN micrometer line array, light detector chip and preparation method thereof |
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Application publication date: 20210514 |