CN112802770A

CN112802770A - Etching amount detection method and display panel mother board

Info

Publication number: CN112802770A
Application number: CN202110050519.0A
Authority: CN
Inventors: 马红星; 李勃; 李素华; 黄毅; 初艳新
Original assignee: Hefei Visionox Technology Co Ltd
Current assignee: Hefei Visionox Technology Co Ltd
Priority date: 2021-01-14
Filing date: 2021-01-14
Publication date: 2021-05-14
Anticipated expiration: 2041-01-14
Also published as: CN112802770B

Abstract

The invention discloses an etching amount detection method and a display panel mother board. The method for detecting the etching amount comprises the following steps: providing a semi-finished product of a display panel mother board, which comprises a substrate, a blocking column arranged on the substrate and surrounding an opening area, and a testing assembly arranged on the substrate and located in the peripheral area of the display area, wherein the testing assembly comprises a testing line, the length of the testing line is greater than the peripheral perimeter of the opening area, and the material of the testing line is the same as that of the blocking column; synchronously and laterally etching the blocking columns and the test lines to form lateral concave parts on the blocking columns and the lateral concave parts on the test lines; and detecting the resistance value of the test line, and determining the etching amount of the barrier column according to the resistance value. According to the invention, the etching amount of the barrier pillars in the display panel can be effectively monitored.

Description

Etching amount detection method and display panel mother board

Technical Field

The invention relates to the technical field of display, in particular to an etching amount detection method and a display panel mother board.

Background

The Organic Light Emitting Diode (OLED) display has the advantages of wide viewing angle, low driving voltage, fast response speed, rich light emitting colors, capability of realizing large-area flexible display, and the like, and is a display technology which is widely concerned and applied at present.

In the OLED display panel, through arranging the opening surrounded by the display area, functional devices such as a front camera, an infrared photosensitive element and the like can be conveniently integrated while a high screen ratio is obtained. In the packaging structure of the display panel with the opening, a barrier pillar which surrounds the opening and is laterally etched is generally included. In the lateral etching process, due to poor etching performance at the end of the etching liquid or other unstable factors, the lateral etching amount of the barrier column is too small, so that organic layers near the hole area cannot be effectively broken, and the display panel has a large risk of invasion of water vapor, oxygen and the like in a reliability test (RA) or a use process, thereby affecting the reliability of the display panel or generating abnormal display phenomena such as black spots and the like. Therefore, it is necessary to detect the amount of lateral etching of the barrier pillars.

In the existing display panel detection technology, Focused Ion Beam (FIB) slicing is often required to detect the lateral etching amount of the isolation pillars. However, the detection method is complicated in operation and long in test period, and may cause the rejection of the display panel. Therefore, there is still a need to provide a new method for detecting the etching amount of the isolation pillar.

Disclosure of Invention

The invention provides an etching amount detection method and a display panel mother board, and aims to conveniently and effectively detect the etching amount of a barrier column in a display panel.

The first aspect of the present invention provides a method for detecting an etching amount, which includes the steps of:

providing a semi-finished product of a display panel mother board, wherein the semi-finished product of the display panel mother board comprises a substrate, and a blocking column and a testing assembly which are arranged on the substrate, the substrate is provided with a display panel forming area, the display panel forming area comprises a display area, an opening area and blocking areas positioned in the display area and the opening area, the blocking areas are arranged around at least part of the opening area, the blocking columns are positioned in the blocking areas and arranged around the opening area, the testing assembly is positioned in the peripheral area of the display area, the testing assembly comprises testing lines, the length of the testing lines is greater than the peripheral perimeter of the opening area, and the materials of the testing lines are the same as those of the blocking column;

synchronously and laterally etching the blocking columns and the test lines to form lateral concave parts on the blocking columns and the lateral concave parts on the test lines;

and detecting the resistance value of the test line, and determining the etching amount of the barrier column according to the resistance value.

In the foregoing embodiment of the present invention, in the step of providing the semi-finished product of the display panel mother board, the substrate has a plurality of display panel forming regions and a connection region connected between the plurality of display panel forming regions, the display panel forming regions further include a frame region surrounding the display regions, the peripheral region includes the frame region and the connection region, and the test component is located in the frame region or the connection region.

In any of the foregoing embodiments of the invention, the test line is disposed adjacent to the barrier column.

In any of the foregoing embodiments of the present invention, in the step of providing a semi-finished product of a display panel mother board, the blocking pillars and the test lines are both of a composite metal layer structure, and the composite metal layer structure includes a first metal layer, a second metal layer and a third metal layer, which are stacked, where the first metal layer and the third metal layer are both etching-resistant layers, and the second metal layer is a layer to be etched; further, the first metal layer includes Ti and/or Mo, the second metal layer includes Al, and the third metal layer includes Ti and/or Mo.

In any of the embodiments of the present invention, the display panel forming region of the substrate is provided with a pixel circuit device layer, the pixel circuit device layer includes a source drain layer, and the blocking pillar and the test line are formed in the same process as the source drain layer.

In any of the foregoing embodiments of the invention, the barrier column may be in the form of a closed loop. In some embodiments, the barrier post is square ring shaped, circular ring shaped, quasi-circular ring shaped, or a combination of two or more thereof.

In any of the foregoing embodiments of the present invention, the barrier region is provided with a plurality of barrier pillars in a direction from the aperture region to the display region.

In any of the embodiments of the present invention, in the step of providing the display panel mother board semi-finished product, a ratio of the peripheral perimeter of the open region to the length of the test line may be 1:5 to 1: 20.

In any of the foregoing embodiments of the invention, the test line may have a serpentine shape. In some embodiments, the test line includes a plurality of first line segments disposed in parallel and spaced apart from each other, and a second line segment electrically connecting the plurality of first line segments in series.

In any of the foregoing embodiments of the invention, the first line segment is a straight line segment; and/or the second line segment is a straight line segment.

In any of the foregoing embodiments of the present invention, the length of the first line segment is 20 μm to 30 μm.

In any of the foregoing embodiments of the present invention, the line width of the first line segment is 1 μm to 3 μm, and the line width of the first line segment is the same as or different from the width of the barrier pillar.

In any of the foregoing embodiments of the present invention, the line pitch of adjacent first line segments is 2 μm to 3 μm.

In any of the foregoing embodiments of the present invention, the number of the first segments is 200 to 300.

In any of the foregoing embodiments of the invention, the line width of the second line segment is 1 μm to 3 μm, and the line width of the second line segment is the same as or different from the line width of the first line segment.

In any of the foregoing embodiments of the invention, the angle between the first line segment and the second line segment is 80 degrees to 100 degrees.

In any of the foregoing embodiments of the present invention, in the step of performing synchronous lateral etching on the barrier pillars and the test lines, the method of lateral etching includes using dry etching or wet etching.

In any of the foregoing embodiments of the present invention, before detecting the resistance value of the test line and determining the etching amount of the barrier pillars based on the resistance value, the method includes: providing a standard sample, wherein the standard sample comprises a standard part which is the same as the barrier column or the test line; laterally etching the standard part by using a lateral etching method which is the same as that of the barrier column and the test line; determining the ratio A of the resistance value R' of the standard part under different etching amounts to the resistance value R before etching; drawing a scatter diagram about the etching amount and A; fitting a linear relation between the etching amount and A according to the scatter diagram;

detecting the resistance value of the test line, and determining the etching amount of the barrier column according to the resistance value, wherein the method comprises the following steps: determining an A value according to the ratio of the resistance value of the test line after etching to the resistance value of the test line before etching; and substituting the A value into the linear relation to determine the etching amount of the test line, thereby determining the etching amount of the barrier column.

A second aspect of the present invention provides a display panel mother board, comprising:

the display panel comprises a substrate, a first electrode, a second electrode and a third electrode, wherein the substrate is provided with a display panel forming area, the display panel forming area comprises a display area, an opening area and a blocking area positioned between the display area and the opening area, and the blocking area surrounds at least part of the opening area;

the blocking column is arranged in the blocking area of the substrate and arranged around the opening area, and is provided with a lateral concave part;

the testing component is arranged on the substrate and located in the peripheral area of the display area, the testing component comprises a testing line with a lateral concave portion, the length of the testing line is larger than the peripheral perimeter of the opening area, and the testing line and the blocking column are formed in the same manufacturing process.

In any of the foregoing embodiments of the present invention, the test assembly further includes a first contact pad electrically connected to one end of the test line and a second contact pad electrically connected to the other end of the test line. In some embodiments, two first pads are connected in parallel to one end of the test line and two second pads are connected in parallel to the other end of the test line.

According to the etching amount detection method and the display panel mother board, the test line with the length larger than the peripheral perimeter of the opening area is arranged on the substrate, the test line is made of the same material as the isolation column and is formed by synchronous lateral etching with the isolation column, and therefore the resistance value of the test line can reflect the lateral etching amount of the isolation column, and the lateral etching amount of the isolation column can be conveniently and effectively detected by detecting the resistance of the test line. The etching amount detection method is simple, and damage or scrap of the display panel is avoided.

Drawings

Other features, objects and advantages of the invention will become apparent from the following detailed description of non-limiting embodiments thereof, when read in conjunction with the accompanying drawings, in which like reference characters designate the same or similar parts throughout the figures thereof, and which are not to scale.

Fig. 1 is a flowchart of an etching amount detection method according to an embodiment of the present invention.

Fig. 2 is a schematic plan view of a display panel mother board semi-finished product according to an embodiment of the present invention.

Fig. 3 is a schematic cross-sectional view of the display panel mother sheet semi-finished product of fig. 2 along OO.

Fig. 4 is a schematic plan view of a display panel mother board semi-finished product according to another embodiment of the present invention.

FIG. 5 is an enlarged schematic view of a test assembly according to one embodiment of the invention.

Fig. 6 is a diagram illustrating a step of forming an initial source/drain layer of a mother board half-finished product of a display panel according to an embodiment of the present invention.

Fig. 7 is a diagram illustrating steps of forming barrier pillars, test lines, and source/drain protective layers of a mother panel half-finished product of a display panel according to an embodiment of the present invention.

FIG. 8 is a diagram illustrating a step of simultaneously etching barrier pillars and test lines of a mother substrate for a display panel according to an embodiment of the present invention.

FIG. 9 is a schematic structural diagram of a barrier pillar and a test line after simultaneous lateral etching according to one embodiment of the present invention.

Fig. 10 is a schematic structural view of an OLED and an encapsulation layer forming a display panel according to an embodiment of the present invention.

Fig. 11 is an enlarged schematic view of the R portion of fig. 10.

Fig. 12 is a schematic cross-sectional view of a display panel in which an aperture is formed according to an embodiment of the present invention.

Detailed Description

Features and exemplary embodiments of various aspects of the present invention will be described in detail below, and in order to make objects, technical solutions and advantages of the present invention more apparent, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not to be construed as limiting the invention. It will be apparent to one skilled in the art that the present invention may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present invention by illustrating examples of the present invention.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

FIG. 1 is a flow chart of an etching amount detecting method according to an embodiment of the present invention. As shown in fig. 1, the etching amount inspecting method according to one embodiment of the present invention includes a step S10 of providing a display panel mother board semi-finished product, an etching step S20, and an inspecting step S30.

Fig. 2 shows a schematic plan view of a display panel mother board half-finished product as an example. Fig. 3 is a schematic cross-sectional view of a semi-finished display panel mother board shown in fig. 2. Referring to fig. 2 and 3, in the step S10 of providing a display panel mother board semi-finished product, the display panel mother board semi-finished product includes a substrate 100, and barrier pillars 200 and a test assembly 300 disposed on the substrate 100.

The substrate 100 may be formed using materials known in the art. In some embodiments, the substrate 100 may be formed of glass, hard plastic, or plastic having flexibility. As an example, the substrate 100 is a glass substrate. As another example, the substrate 100 may be a Polyimide (PI) flexible substrate.

The substrate 100 has a display panel forming region a including a display region a1, an opening region a2, and a blocking region A3 located in the display region a1 and the opening region a2, wherein the blocking region A3 is disposed around at least a portion of the opening region a 2.

The display panel formation region a of the substrate 100 is used to form a display panel. The display area a1 corresponds to an Active area (Active area) of the display panel. The organic light emitting units are formed in an array arrangement in the display area a 1. The organic light emitting unit is used for emitting light to display image information. Each organic light emitting unit may include an OLED and a pixel circuit module for driving the OLED to emit light, and other optional modules known in the art. In the display panel mother sheet semi-finished product, the display area a1 may include a part of the film layer of the light emitting cell, for example, a pixel circuit device layer. The pixel circuit device layer includes a pixel circuit module. The pixel circuit module may include more than one thin film transistor TFT and more than one storage capacitor Cst. The TFT may be a top gate type TFT or a bottom gate type TFT.

An open area a2 is defined within the display area a 1. The display area a1 may completely surround the open area a 2. It is also possible that the open area a2 is located at the edge of the display area a1, i.e., the display area a1 partially surrounds the open area a 2. The opening area a2 corresponds to the opening of the display panel. The substrate 100 in the region and the film layer formed in the region are removed at a later time, and an opening penetrating the display panel is formed. Functional devices such as a front camera, an infrared sensor, and the like may be integrated in the opening or at a position below the bottom of the display panel corresponding to the opening. The shape of the opening is not particularly limited and may be selected according to practical requirements. In some embodiments, the openings may be square, circular-like, or a combination thereof.

The barrier region A3 is located between the display region a1 and the opening region a 2. Barrier pillars 200 are disposed at barrier region A3, and barrier pillars 200 surround open region a 2. The barrier column 200 may partially surround the open area a2, or form a ring completely surrounding the open area a 2. In some embodiments, the barrier column 200 is a closed loop. The barrier column 200, which is a closed loop structure surrounding the open area a2, provides a better barrier to the ingress of water and oxygen. The closed loop shape may be any shape. The skilled person can choose arbitrarily according to the shape of the opening or the actual requirements. For example, the barrier column 200 may have a square ring shape, a circular ring shape, a quasi-circular ring shape, or a combination of two or more thereof.

In some embodiments, the barrier region A3 is provided with a plurality of barrier pillars 200 in a direction from the opening region a2 to the display region a 1. The number of the plurality. The provision of the plurality of barrier pillars 200 may enhance the effect of blocking water and oxygen.

Alternatively, among the plurality of barrier pillars 200 in the direction from the opening area a2 to the display area a1, the interval between adjacent barrier pillars 200 may be 2 μm to 3 μm.

In some embodiments, the width of the barrier pillars 200 may be 1 μm to 3 μm, such as 1 μm to 2 μm, 1.5 μm to 2.5 μm, or 2 μm to 3 μm, and the like.

The barrier pillars 200 may employ a material known in the art that blocks moisture, oxygen, for example, a metal material such as Al, Ca, Mg, Ti, Mo, etc., an inorganic material such as silicon oxide, silicon nitride, silicon oxynitride, etc., and the like. The barrier column 200 may be a single layer structure or a multi-layer composite structure. In some embodiments, the barrier pillars 200 are composite metal layer structures. Optionally, the composite metal layer structure includes a first metal layer M1, a second metal layer M2, and a third metal layer M3, which are stacked, where the first metal layer M1 and the third metal layer M3 are both etch-resistant layers, and the second metal layer M2 is a layer to be etched. This facilitates subsequent lateral etching of the barrier pillars 200. As an example, the first metal layer M1 includes one or more of Ti and Mo, the second metal layer M2 includes Al, and the third metal layer M3 includes one or more of Ti and Mo. For example, the barrier pillars 200 are a composite metal layer structure of Ti layer/Al layer/Ti layer.

In some embodiments, the pixel circuit module includes a TFT, and the source and drain electrodes of the TFT may be a composite layer structure of Ti layer/Al layer/Ti layer. In these embodiments, the barrier pillars 200 may be formed in the same process as the source and drain electrodes S and D of the TFT.

In addition, barrier zone a3 may also route traces. For example, the pixel circuit traces originally disposed in the opening region a2 may bypass the opening region a2 and be disposed in the blocking region A3 on the periphery of the opening region a 2.

The display panel formation area a also typically includes a bezel area a4 surrounding the display area a 1. Various driving elements known in the art, such as a data driver for supplying a data signal to the display panel device layer, a gate driver for supplying a gate signal to the display panel device layer, etc., may be disposed at the bezel area a 4.

The substrate 100 includes at least one display panel formation region a. In some embodiments, the substrate 100 includes a plurality of display panel formation regions a disposed to be spaced apart from each other and a connection region C connected between the plurality of display panel formation regions a. Alternatively, the connection region C partially or entirely surrounds the periphery of the display panel formation region a.

The test assembly 300 is located at a peripheral area of the display area a 1. The test assembly is located in the peripheral area of the display area a1, and thus does not affect the display panel to display light. In some embodiments, peripheral areas of display area a1 may include a bezel area a4 and/or a connection area C. Referring to fig. 2 and 4, the test assembly 300 may be located in either the rim area a4 or the attachment area C. This will facilitate the selection by a person skilled in the art according to the actual situation and need.

Referring to fig. 5, the test assembly 300 includes a test line 310, the length of the test line 310 is greater than the outer circumference of the open area a2, and the material of the test line 310 is the same as that of the barrier column 200. Specifically, when the barrier pillars 200 have a single-layer structure, the test line 310 has a single-layer structure of the same material as the barrier pillars 200. When the barrier pillars 200 are of a multi-layer composite structure, the test line 310 is of the same composite layer structure as the barrier pillars 200, and at least the layer to be etched of the test line 310 and the layer to be etched of the barrier pillars 200 are made of the same material. In some embodiments, the layers of the test line 310 are made of the same material as the layers of the barrier pillars 200, respectively. As an example, the test line 310 is a composite metal layer structure of Ti layer/Al layer/Ti layer. Alternatively, the test line 310 is formed in the same process as the source S and the drain D of the TFT.

In some embodiments, the test line 310 may have a serpentine shape. As an example, the serpentine test line 310 may include a plurality of first line segments 311 arranged in parallel and spaced apart from each other, and a second line segment 312 electrically connecting the plurality of first line segments 311 in series. In some embodiments, the first line segment 311 may be a straight line segment or a curved line segment, and the second line segment 312 may be a straight line segment or a curved line segment. As an example, as shown in fig. 5, the first line segment 311 is a straight line segment, and the second line segment 312 is a straight line segment.

Alternatively, as shown in fig. 2 to 4, the first line segment 311 may extend along the longitudinal direction (e.g., Y direction in the figure). The first line segment 311 may also extend in a transverse direction (e.g., X direction in the figure) or a direction intersecting the longitudinal direction and the transverse direction.

In step S10, a display panel mother board semi-finished product is provided, which may be prepared by methods known in the art. As a specific example, S10 may include:

s11, referring to fig. 6, a semiconductor layer 410, a gate layer 420, and an initial source/drain layer 430 'are sequentially stacked in a display panel formation region a of a substrate 100, and the semiconductor layer 410, the gate layer 420, and the initial source/drain layer 430' are separated from each other by an insulating layer.

The semiconductor layer 410 includes a source region, a drain region, and a channel region between the source region and the drain region. Alternatively, the semiconductor layer 410 may be formed of one or more of amorphous silicon, single crystal silicon, polycrystalline silicon (e.g., low temperature polysilicon LTPS, etc.), and indium gallium zinc oxide.

The gate layer 420 includes a gate G disposed corresponding to a channel region of the semiconductor layer 410. Alternatively, the gate layer 420 may be made of one or more of ti, mo, au, pt, al, ni, and cu.

In some embodiments, the gate layer 420 may further optionally include a first electrode of the storage capacitor Cst. The second electrode of the storage capacitor Cst is located on a side of the first electrode away from the substrate 100, and is spaced apart from the first electrode by a capacitor dielectric layer. The second electrode can adopt more than one of titanium, molybdenum, gold, platinum, aluminum, nickel and copper.

The initial source drain layer 430 'is electrically connected to the source and drain regions, respectively, through vias that penetrate an insulating layer between the initial source drain layer 430' and the semiconductor layer 410. In some embodiments, the test assembly 300 is located in the border area a4, and the source drain layer 430' covers the display panel forming area a. In other embodiments, the test element 300 is located at the connection region C, and the initial source/drain layer 430' covers the display panel formation region a and further extends to at least the region of the connection region C where the test line 310 is formed.

Optionally, the source-drain layer 430' includes a first metal layer M1, a second metal layer M2, and a third metal layer M3 stacked in a stacked manner, where the first metal layer M1 and the third metal layer M3 are both etch-resistant layers, and the second metal layer M2 is a layer to be etched. As an example, the initial source drain layer 430' is a composite layer of Ti layer/Al layer/Ti layer.

S12, the original source/drain layer 430' is patterned to form a patterned source/drain layer 430. Referring to fig. 3, the source-drain layer 430 includes a source S electrically connected to the source region of the semiconductor layer 410 and a drain D electrically connected to the drain region of the semiconductor layer 410, a barrier pillar 200, and a test line 310.

At S12, the patterning process may use methods known in the art, such as dry etching the initial source drain layer 430' using a plasma with a photoresist as a mask.

In some embodiments, S10 may also optionally include S13, forming a protective layer on the side of source drain layer 430 facing away from substrate 100. The protective layer covers the source electrode S and the drain electrode D and exposes the barrier pillars 200 and the test lines 310. The protective layer serves to protect the source electrode S and the drain electrode D from being damaged in a subsequent etching step. The protective layer may be made of a protective material known in the art, such as a polymer, an oxide, or the like. Optionally, the protective layer is made of photoresist. Alternatively, referring to fig. 7, the protective layer may be the planarization layer 600. The planarization layer 600 may use a material known in the art, such as Polyimide (PI), etc.

In some embodiments, a buffer layer 500 may also be formed between the substrate 100 and the semiconductor layer 410. The buffer layer 500 may be a silicon oxide layer, a silicon nitride layer, or a composite layer of the silicon oxide layer and the silicon nitride layer.

Referring to fig. 8 and 9, in the etching step S20, the barrier pillars 200 and the test lines 310 are simultaneously laterally etched so that the barrier pillars 200 form the lateral recesses 210 and the test lines 310 form the lateral recesses 311.

In the etching step S20, the barrier pillars 200 and the test lines 310 are simultaneously laterally etched using the same etching process in the same etching process. The lateral etching may be performed using methods known in the art, such as dry etching or wet etching. As an example, simultaneous lateral etching of the barrier pillars 200 and the test lines 310 may be performed using a drill-and-etch method.

In some embodiments, the barrier pillars 200 and the test lines 310 are each a composite metal layer structure including a first metal layer M1, a second metal layer M2, and a third metal layer M3, which are stacked; for example, a composite metal layer structure of Ti layer/Al layer/Ti layer. The wet etching is performed by using an etching solution, since the first metal layer M1 and the third metal layer M3 both have etching resistance and are not substantially etched, and the first metal layer M1 can be used as a mask for the second metal layer M2, so that the etching solution laterally etches the barrier pillars 200 and the test lines 310 from the side. And the required lateral etching amount is obtained by reasonably controlling the etching time. The etching solution can be one known in the art, and for example, contains H₃PO₄、HNO₃And CH₃Etching solution of COOH containing H₃PO₄And HNO₃Or contains H₂SO₄And HNO₃Etching solution, and the like. The skilled person can select it as desired.

In these embodiments, the barrier pillars 200 are laterally etched to form lateral recesses 210 having a cross-section of a "I" shape. In the subsequent process of forming the organic layer, the organic layer can be more effectively broken under the blocking effect of the blocking pillar 200 of the I-shaped structure, so as to block the invasion path of water and oxygen and block the invasion of water and oxygen. The test lines 310 simultaneously form lateral recesses 311, which are in the form of i-shaped cross-sections.

In the detecting step S30, the resistance value of the test line 310 is detected, and the lateral etching amount of the barrier pillars 200 is determined based on the resistance value.

At S30, the detection of the resistance value of the test line 310 may be performed using equipment and means known in the art, and the present invention is not particularly limited. For example, using an electrical characteristic measuring device, and then using a resistance meter, for example, two electrodes of the resistance meter are respectively connected to two ends of the test line 310, so as to obtain the resistance value of the test line 310.

The detection principle is as follows: since the material of the test line 310 is the same as that of the barrier pillars 200, similar lateral etching will occur when the test line 310 and the barrier pillars 200 are etched simultaneously. The lateral etching amount of the test line 310 can truly and reliably reflect the lateral etching amount of the isolation pillars 200.

The test lines 310 are similar to the pillars 200, and are narrower in width with respect to the region where the lateral etching occurs (e.g., the second metal layer M2), but have a constant resistivity and a constant length and height. According to the resistance formula, the resistance of the test line 310 varies with the lateral etching amount.

The formula of resistance is

Wherein R is the resistance of the test line 310; ρ is the resistivity of the test line 310, which is the electrical property of the material of the test line 310 itself; l is the length of the test line 310; h is the height of the test line 310; w is the width of the test line 310, which varies with the amount of lateral etching.

Typically, the lateral etch is a double-sided simultaneous etch. Width W of lateral etched region of etched test line 310₁Width W of lateral etch region before etching for test line 310₀Minus 2 times the lateral etch amount x. Therefore, the resistance value R of the test line 310 before etching₀And resistance value R after etching₁Satisfies the following conditions:

further, the relation between the lateral etching amount x and y can be obtained:

resistance value R before etching through test line 310₀And resistance value R after etching₁The lateral etching amount x of the test line 310 can be obtained, and thus the lateral etching amount of the barrier pillars 200 can be obtained.

According to the embodiment of the invention, the lateral etching amount of the barrier column 200 can be accurately and effectively measured and monitored by detecting the resistance value of the test line 310 after etching, the detection operation is simple and convenient, and the detection efficiency is higher. Particularly, the scheme of the invention can also realize the on-line monitoring of the lateral etching amount of the barrier pillars 200.

The inventors have found that the test line 310 having a length greater than the outer circumference of the opening area a2 can feed back the lateral etching amount of the barrier pillars 200 more truly and accurately. Moreover, the length of the test line 310 is greater than the peripheral perimeter of the opening area a2, which is beneficial to making the resistance value of the test line 310 appropriate, facilitating visual detection, and improving the sensitivity of the resistance value change of the test line 310.

In some embodiments, the ratio of the perimeter of the open-cell area a2 to the length of the test line 310 is 1:5 to 1:20, optionally 1:5 to 1:10, 1:8 to 1:15, or 1:10 to 1:20, etc.; for example 1: 10. The test line 310 satisfies the above conditions, and the subsequent simultaneous lateral etching with the barrier pillars 200 can feed back the lateral etching amount of the barrier pillars 200 more accurately.

In some embodiments, the test line 310 is disposed proximate to the barrier pillars 200. Therefore, the etching consistency of the test line 310 and the barrier column 200 is better during etching, and the difference between the lateral etching amount of the test line 310 and the barrier column 200 is smaller, so that the accuracy of the detection result can be further improved.

In some embodiments, the testing line 310 has a serpentine shape and includes a plurality of first segments 311 disposed in parallel and spaced apart from each other, and a second segment 312 electrically connecting the plurality of first segments 311 in series, wherein the number of the first segments 311 may be 200 to 300, such as 200 to 250, 220 to 280, 230 to 270, or 250 to 300. The appropriate number of traces can more accurately detect the resistance of the test line 310, thereby more accurately feeding back the lateral etching amount of the barrier pillars 200.

In some embodiments, the ratio of the line width of the test line 310 to the total length thereof is 1:5 to 1:100, optionally 1:10 to 1:50, 1:30 to 1:70, 1:40 to 1:60, or 1:50 to 1: 80; for example 1: 50. The ratio of the line width to the length of the test line 310 is appropriate, which is beneficial to improving the sensitivity of the resistance value change before and after the lateral etching of the test line 310, so that the accuracy of the resistance value before and after the lateral etching of the test line 310 can be improved, and the detection accuracy of the lateral etching amount of the isolation pillar 200 can be further improved.

In some embodiments, the length of the first segment 311 may be 20 μm to 30 μm, such as 20 μm to 25 μm, 23 μm to 28 μm, or 25 μm to 30 μm, and the like.

In some embodiments, the line width of the first line segment 311 may be 1 μm to 3 μm, such as 1 μm to 2 μm, 1.5 μm to 2.5 μm, or 2 μm to 3 μm, and the like. The line width of the first line segment 311 may be the same as or different from the width of the barrier pillar 200. In some embodiments, the line width of the first line segment 311 is the same as the width of the barrier pillar 200.

In some embodiments, the line spacing between adjacent first line segments 311 is between 2 μm and 3 μm. The adjacent first line sections 311 have proper line spacing, so that the consistency of lateral etching of the test line 310 and the barrier pillars 200 can be improved, and the lateral etching amount of the barrier pillars 200 can be fed back more accurately. The line spacing of adjacent first line segments 311 and the spacing of adjacent spacers 200 may be the same or different. In some embodiments, the line spacing of adjacent first line segments 311 is the same as the spacing of adjacent spacers 200.

In some embodiments, the line width of the second line segment 312 may be 1 μm to 3 μm, such as 1 μm to 2 μm, 1.5 μm to 2.5 μm, or 2 μm to 3 μm, and the like. The line width of the second line segment 312 may be the same as or different from the line width of the first line segment 311. In some embodiments, the line width of the second line segment 312 is the same as the line width of the first line segment 311.

In some embodiments, the included angle between the first line segment 311 and the second line segment 312 is 80 degrees to 100 degrees. Optionally, the included angle between the first line segment 311 and the second line segment 312 is 85 to 95 degrees, 85 to 90 degrees, or 90 to 95 degrees, etc. This is advantageous in accurately feeding back the amount of lateral etching of the barrier pillars 200 and in saving space.

In some embodiments, the thickness of each layer of the first line segment 311 is the same as the corresponding of the isolation pillar 200. Further, the respective layer thicknesses of the second line segment 312 are the same as those of the separator pillar 200.

In some embodiments, the test assembly 300 further includes a first contact pad 330 and a second contact pad 340, the first contact pad 330 being electrically connected to one end of the test line 310, the second contact pad 340 being electrically connected to the other end of the test line 310. Therefore, the electrode of the resistance measuring equipment can be conveniently connected, and the detection convenience is improved.

Alternatively, one end of the test line 310 may be electrically connected to one first contact pad 330, or may be electrically connected to more than two first contact pads 330 connected in parallel. The other end of the test line 310 may be electrically connected to one second pad 340, or may be electrically connected to more than two second pads 340 connected in parallel. As an example, two first pads 330 are connected in parallel to one end of the test line 310, and two second pads 340 are connected in parallel to the other end of the test line 310. By adopting the design, the detection precision can be further improved.

In some embodiments, before the detecting step S30, further optionally including S40: providing a standard sample including the same standard portion as the barrier pillars 200 or the test line 310; laterally etching the standard part by using the same lateral etching method as the barrier pillars 200 and the test lines 310; determining the ratio A of the resistance value R' of the standard part under different etching amounts to the resistance value R before etching; drawing a scatter diagram about the etching amount and A; and fitting a linear relation between the etching amount and A according to the scatter diagram. This facilitates the subsequent determination of the lateral etching amount of the test line 310 according to the resistance value of the test line 310, thereby conveniently obtaining the lateral etching amount of the barrier pillars 200.

Alternatively, the standard sample may include a plurality of standards. Therefore, the linear relation between the etching amount and A can be fitted according to a plurality of optional standard parts, and the accuracy and the reliability are improved.

Alternatively, the standard sample may be obtained by forming the barrier pillars 200 or the test lines 310 on the substrate. The substrate 100 may be used as the substrate. And the above-described buffer layer 500 may also be formed between the substrate and the barrier pillars 200 or the test lines 310. The standard sample may also be a display panel mother substrate or a display panel including the barrier pillars 200 or the test lines 310 according to the present invention.

In these embodiments, the detecting step S30 may include: determining the value A according to the ratio of the resistance value after the lateral etching of the test line 310 to the resistance value before the etching; the value a is substituted into the linear relationship to determine the lateral etching amount of the test line 310, thereby determining the lateral etching amount of the barrier pillars 200.

In some embodiments, an OLED is also optionally formed on source drain layer 430 before detection step S30. Referring to fig. 10 and 11, the OLED generally includes a first electrode layer 710, a second electrode layer 720, and an organic thin film layer 730 between the first electrode layer 710 and the second electrode layer 720.

The first electrode layer 710 may be an anode layer. As an example, the first electrode layer 710 may be a composite layer of ITO layer/silver layer/ITO layer. The first electrode layer 710 may be electrically connected to the source S or the drain D through a via of the planarization layer 600 between it and the source drain layer 430.

The second electrode layer 720 may be a cathode layer. As an example, the second electrode layer 720 may include a cathode material selected from Al, Mg, Ca, and the like.

The organic thin film layer 730 includes an organic emission layer (EML)731 and a common organic layer 732. The organic light emitting layer 731 is generally positioned within the pixel opening of the pixel defining layer 800. The organic light emitting layer 731 may be located between the common organic layer 732 and the first electrode layer 710, between the common organic layer 732 and the second electrode layer 720, or between the common organic layers 732. The organic light emitting layer 731 may include an organic light emitting material known in the art. For example, red light emitting materials, blue light emitting materials, green light emitting materials, and the like are classified by color. As another example, a fluorescent light emitting material, a phosphorescent light emitting material, a thermally activated delayed fluorescent light emitting material classified by the principle of light emission. The common organic layer 732 is generally an organic film layer that is continuously formed in the display area a1 to be shared by a plurality of light emitting cells. In general, the common organic layer 732 may include one or more of an Electron Injection Layer (EIL), an Electron Transport Layer (ETL), a Hole Blocking Layer (HBL), an Electron Blocking Layer (EBL), a Hole Transport Layer (HTL), and a Hole Injection Layer (HIL). These layers may be made of any of the materials known in the art.

Since the barrier pillars 200 having the lateral recesses 210 are disposed around the opening area a2, the common organic layer 732 of the barrier area A3 may be broken, so that the intrusion path of water and oxygen to the display area a1 may be cut, thereby advantageously reducing the risk of water and oxygen entering the display area a1 and improving the reliability of the display panel. Furthermore, the display panel can also reduce abnormal display phenomena caused by water and oxygen invasion.

In some embodiments, before the detecting step S30, an encapsulation layer 900 may be further formed on the second electrode layer 720. The encapsulation layer 900 may include organic layers, inorganic layers, or a combination thereof. The organic layer may include one or more of polyolefin, polyvinyl chloride, polystyrene, Polyimide (PI), polyethylene terephthalate (PET), epoxy resin, phenolic resin, and the like. The inorganic layer may include one or more of silicon oxide, silicon nitride, and silicon-based oxynitride. Optionally, the encapsulation layer 900 is an inorganic layer or a composite layer of an inorganic layer and an organic layer. This can improve the packaging effect.

The encapsulation layer 900 also extends to the barrier region a3, and the encapsulation layer 900 fills the lateral recess 210 of the barrier pillar 200 to form a fitting connection with the barrier pillar 200. Therefore, the packaging stability can be improved, and the effect of blocking water and oxygen can be further improved.

In some embodiments, prior to the detecting step S30, referring to fig. 12, a hole H may also be formed in the hole region a 2. Perforations in perforated area a2 can be made using methods known in the art to form perforations H. For example, a laser method, etc.

The invention also provides a display panel mother board. The display panel mother board includes a substrate 100, and barrier pillars 200 and a test assembly 300 disposed on the substrate 100. The substrate 100 has a display panel forming region a including a display region a1, an opening region a2, and a blocking region A3 located in the display region a1 and the opening region a2, wherein the blocking region A3 is disposed around at least a portion of the opening region a 2. The barrier posts 200 are located in barrier zone A3 and are disposed around the apertured zone a 2. And the barrier posts 200 have lateral recesses. The testing device 300 is disposed on the substrate 100 and located in the peripheral region of the display area a1, the testing device 300 includes a testing line 310 having a lateral recess 311, the length of the testing line 310 is greater than the peripheral perimeter of the opening area a2, and the testing line 310 and the barrier pillars 200 are formed in the same process.

According to the display panel motherboard of the invention, the test line 310 formed in the same process with the barrier column 200 is arranged on the substrate 100, so that the resistance value of the test line 310 can reflect the lateral etching amount of the barrier column 200, and the lateral etching amount of the barrier column 200 can be conveniently and effectively detected by detecting the resistance of the test line 310. The etching amount detection process is simple, and damage or scrap of the display panel is avoided.

In some embodiments, the display panel device layer further includes an OLED device layer and a pixel circuit device layer.

The technical features described in the etching amount detection method of the present invention are also applicable to the display panel mother board of the present invention, and are not described herein again.

In accordance with the above-described embodiments of the present invention, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. An etching amount detection method is characterized by comprising the following steps:

providing a semi-finished product of a display panel mother board, wherein the semi-finished product of the display panel mother board comprises a substrate, and a blocking column and a testing assembly which are arranged on the substrate, the substrate is provided with a display panel forming area, the display panel forming area comprises a display area, an open area and a blocking area which is arranged in the display area and the open area, the blocking area is arranged around at least part of the open area, the blocking column is arranged in the blocking area and is arranged around the open area, the testing assembly is arranged in the peripheral area of the display area, the testing assembly comprises a testing line, the length of the testing line is greater than the peripheral perimeter of the open area, and the material of the testing line is the same as that of the blocking column;

synchronously and laterally etching the blocking columns and the test lines to form lateral concave parts on the blocking columns and the test lines;

2. The inspection method according to claim 1, wherein in the step of providing a display panel mother board semi-finished product, the substrate has a plurality of the display panel forming regions and a connection region connected between the plurality of the display panel forming regions, the display panel forming region further includes a bezel region surrounding the display region, the peripheral region includes the bezel region and the connection region, and the test component is located in the bezel region or the connection region;

further, the test line is disposed adjacent to the blocking pillar.

3. The detecting method according to claim 1, wherein in the step of providing the display panel mother board semi-finished product, the barrier pillars and the test lines are both of a composite metal layer structure, and the composite metal layer structure includes a first metal layer, a second metal layer and a third metal layer which are stacked, wherein the first metal layer and the third metal layer are both etching-resistant layers, and the second metal layer is a layer to be etched; further, the first metal layer includes Ti and/or Mo, the second metal layer includes Al, and the third metal layer includes Ti and/or Mo.

4. The inspection method according to any one of claims 1 to 3, wherein the display panel mother board semi-finished product satisfies one or more of the following conditions:

(i) the display panel forming area of the substrate is provided with a pixel circuit device layer, the pixel circuit device layer comprises a source drain layer, and the blocking column, the test line and the source drain layer are formed in the same process;

(ii) the blocking column is in a closed ring shape; furthermore, the isolation column is in a square ring shape, a circular ring shape, a similar circular ring shape or a combination of more than two of the square ring shape, the circular ring shape and the similar circular ring shape;

(iii) the barrier region is provided with a plurality of barrier pillars in a direction from the opening region to the display region.

5. The detection method according to any one of claims 1 to 3, wherein in the step of providing the display panel mother board semi-finished product, the ratio of the peripheral perimeter of the open region to the length of the test line is 1:5 to 1: 20;

further, the test line is serpentine;

furthermore, the test line comprises a plurality of first line segments which are parallel and arranged at intervals, and a second line segment which electrically connects the plurality of first line segments in series;

further, the first line segment is a straight line segment; and/or the second line segment is a straight line segment.

6. The detection method according to claim 5, wherein the test line satisfies one or more of the following:

(a) the length of the first line segment is 20-30 mu m;

(b) the line width of the first line segment is 1-3 mu m, and the line width of the first line segment is the same as or different from the width of the barrier column;

(c) the line spacing between adjacent first line segments is 2-3 mu m;

(d) the number of the first line segments is 200-300;

(e) the line width of the second line segment is 1-3 mu m, and the line width of the second line segment is the same as or different from the line width of the first line segment;

(f) the included angle between the first line segment and the second line segment is 80-100 degrees.

7. The detection method according to claim 1, wherein in the step of synchronously performing lateral etching on the barrier pillars and the test lines, the lateral etching method includes dry etching or wet etching.

8. The method according to claim 1, wherein before said detecting a resistance value of said test line and determining an etching amount of said barrier pillar based on said resistance value, comprising:

providing a standard sample comprising the same standard as the barrier pillars or the test lines;

laterally etching the standard part by using a lateral etching method which is the same as that of the barrier column and the test line;

determining the ratio A of the resistance value R' of the standard part under different etching amounts to the resistance value R before etching;

drawing a scatter diagram about the etching amount and A;

fitting a linear relation between the etching amount and A according to the scatter diagram;

the detecting the resistance value of the test line and determining the etching amount of the barrier column according to the resistance value comprises the following steps:

determining an A value according to the ratio of the resistance value of the test line after etching to the resistance value of the test line before etching;

and substituting the value A into the linear relation to determine the etching amount of the test line, thereby determining the etching amount of the barrier column.

9. A display panel motherboard, comprising:

the display panel comprises a substrate and a plurality of display panels, wherein the substrate is provided with a display panel forming area, the display panel forming area comprises a display area, an opening area and a blocking area positioned in the display area and the opening area, and the blocking area is arranged around at least part of the opening area;

the testing component is arranged on the substrate and located in the peripheral area of the display area, the testing component comprises a testing line with a lateral concave portion, the length of the testing line is larger than the peripheral perimeter of the opening area, and the testing line and the barrier column are formed in the same manufacturing process.

10. The display panel motherboard of claim 9, wherein the test assembly further comprises a first contact pad electrically connected to one end of the test line and a second contact pad electrically connected to the other end of the test line;

furthermore, the two first contact pads are connected to one end of the test line in parallel, and the two second contact pads are connected to the other end of the test line in parallel.