CN114758586A - Test element group, display panel, preparation method of display panel and test method - Google Patents
Test element group, display panel, preparation method of display panel and test method Download PDFInfo
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
- G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
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Abstract
The embodiment of the application provides a test element group, a display panel, a preparation method of the display panel and a test method of the display panel. The test element group is applied to the display panel and comprises test elements positioned in the non-display area; the test element comprises a part to be tested, a first test part and a second test part, wherein the first test part and the second test part are respectively positioned at two sides of the part to be tested; the part to be tested comprises a dielectric layer and an organic layer which are arranged in a laminated mode, the dielectric layer is close to the first testing part, the organic layer is close to the second testing part, and the shrinking-in size of the dielectric layer relative to the organic layer is the same as the etching depth of the pixel isolation column; the first testing part and the second testing part are electrically connected with the electrical testing equipment, and the capacitance value of the testing element as a capacitor is obtained by monitoring the electrical testing equipment. According to the embodiment of the application, the etching depth of the pixel isolation column in the display area can be accurately monitored in real time by adopting the electrical monitoring method, and meanwhile, the monitoring method is convenient and large in monitoring amount and can be used as a mode for batch monitoring of mass production.
Description
Technical Field
The application relates to the technical field of display, in particular to a test element group, a display panel, a preparation method of the test element group and the display panel, and a test method of the test element group and the display panel.
Background
With the increasing demand of the market for power consumption and life of products, Tandem EL (electroluminescence) devices are increasingly being used. For example: a Tandem OLED (Organic Light-Emitting Diode) is a high-efficiency OLED device structure formed by stacking a plurality of conventional OLED devices in series through connecting layers. The pixel structure of the Tandem EL device has the advantages of long service life, low power consumption, capability of realizing high brightness and the like, but the pixel structure of the Tandem EL device has the risk of pixel crosstalk.
In order to solve the problem of pixel crosstalk, the main current solution is to add a pixel isolation column scheme in an AA area (display area) of a display panel, where the etching depth of the pixel isolation column is a very critical parameter, and if the etching depth of the pixel isolation column does not meet the requirement, the pixel isolation column has a low effect of preventing pixel crosstalk.
Disclosure of Invention
The application provides a testing element group, a display panel, a manufacturing method of the display panel and a testing method of the display panel, aiming at the defects of the prior art, and aims to solve the technical problem that the pixel isolation column cannot effectively prevent pixel crosstalk because the etching depth of the pixel isolation column cannot be monitored in real time in the prior art.
In a first aspect, an embodiment of the present application provides a test element group, which is applied to a display panel, where the display panel includes a display region and a non-display region, the display region includes a plurality of pixel isolation pillars located between two adjacent light emitting units, and the test element group is located in the non-display region and includes a test element;
the test element comprises a part to be tested, a first test part and a second test part, wherein the first test part and the second test part are respectively positioned at two sides of the part to be tested;
the part to be tested comprises a dielectric layer and an organic layer which are arranged in a laminated mode, the dielectric layer is close to the first testing part, the organic layer is close to the second testing part, and the shrinking-in size of the dielectric layer relative to the organic layer is the same as the etching depth of the pixel isolation column;
the first testing part and the second testing part are electrically connected with the electrical testing equipment, and the capacitance value of the testing element as a capacitor is obtained by monitoring the electrical testing equipment.
In one possible implementation, the test element further comprises a planarization layer;
the flat layer is located on one side of the first testing portion, the portion to be tested is located on one side, away from the first testing portion, of the flat layer, and the second testing portion is located on one side, away from the flat layer, of the portion to be tested.
In one possible implementation manner, the orthographic projection of the second testing part on the flat layer covers the orthographic projection of the dielectric layer on the flat layer, and the area of the orthographic projection of the second testing part on the flat layer is larger than that of the orthographic projection of the dielectric layer on the flat layer.
In one possible implementation manner, the orthographic projection of the first test part on the flat layer covers the orthographic projection of the second test part on the flat layer, and the area of the orthographic projection of the first test part on the flat layer is larger than that of the orthographic projection of the second test part on the flat layer.
In one possible implementation, the organic layer is disposed in the same layer as a pixel definition layer included in the display region.
In one possible implementation, the testing component group further includes: a first test pad and a second test pad;
the first testing part is electrically connected with the electrical testing equipment through the first testing pad, and the second testing part is electrically connected with the electrical testing equipment through the second testing pad.
In one possible implementation of the method according to the invention,
the first testing part and the first testing bonding pad are arranged in the same layer with the source drain layer included in the display area;
the second testing part and the second testing pad are arranged on the same layer.
In a second aspect, an embodiment of the present application provides a display panel, which includes a display area and a non-display area, wherein the display area includes a plurality of light emitting units arranged in an array, a pixel isolation pillar is disposed between adjacent light emitting units, and the non-display area is provided with the test element group as in the first aspect.
In a third aspect, embodiments of the present application provide a display device comprising a display panel as in the second aspect
In a fourth aspect, an embodiment of the present application provides a method for manufacturing a display panel as in the second aspect, the display panel including a display area and a non-display area, including:
providing a substrate;
manufacturing a driving circuit layer and a first testing part on one side of a substrate, wherein the driving circuit layer is positioned in a display area, and the first testing part is positioned in a non-display area;
manufacturing a pixel isolation column and a part to be tested on one side of the driving circuit layer and one side of the first testing part, which are far away from the substrate, wherein the pixel isolation column is positioned in the display area, and the part to be tested is positioned in the non-display area;
and manufacturing a second testing part on one side of the part to be tested, which is far away from the substrate.
In one possible implementation manner, the manufacturing of the driving circuit layer and the first testing portion on one side of the substrate includes:
forming a plurality of thin film transistors arranged in an array on a substrate, wherein each thin film transistor comprises a gate layer, a source drain layer and an active layer, and the first test part and the source drain layer are manufactured in the same layer;
after the driving circuit layer and the first testing part are manufactured on one side of the substrate, the method further comprises the following steps:
and manufacturing a flat layer on one side of the driving circuit layer and the first testing part far away from the substrate, wherein the flat layer covers the driving circuit layer and the first testing part.
In one possible implementation manner, the manufacturing of the pixel isolation column and the part to be tested on the side of the driving circuit layer and the first testing part far away from the substrate includes:
depositing an inorganic layer film on one side of the flat layer far away from the substrate, and forming a dielectric layer and an inorganic layer through a composition process, wherein the inorganic layer is positioned in the display area, and the dielectric layer is positioned in the non-display area;
depositing an organic layer film on one side of the dielectric layer and the inorganic layer far away from the substrate, forming a pixel defining layer and an organic layer through a composition process, wherein the pixel defining layer is positioned in the display area, the organic layer is positioned in the non-display area, the dielectric layer and the organic layer form a part to be detected, and the inorganic layer and the pixel defining layer form a pixel isolation column.
In a fifth aspect, an embodiment of the present application provides a method for testing a display panel as in the second aspect, including:
applying an electrical signal to the first test portion and the second test portion;
measuring the capacitance value of the test element as a capacitor;
and determining the retraction size of the dielectric layer of the test element relative to the organic layer according to the capacitance value, thereby determining the etching depth of the pixel isolation column.
The beneficial technical effects brought by the technical scheme provided by the embodiment of the application comprise:
the test element group provided by the embodiment of the application is applied to a display panel, and the test element group is positioned in a non-display area. The testing element group comprises a testing element, the testing element comprises a part to be tested, a first testing part and a second testing part, the first testing part and the second testing part which are used as capacitors of the testing element are electrically connected with electrical testing equipment, the capacitance value of the testing element which is used as a capacitor is obtained by monitoring the electrical testing equipment, the electrical testing equipment can determine the shrinkage size of a dielectric layer of the testing element relative to an organic layer according to the capacitance value of the testing element which is used as a capacitor, and the shrinkage size of the dielectric layer of the testing element relative to the organic layer is the same as the etching depth of a pixel isolation column, so that the etching depth of the pixel isolation column can be determined by determining the shrinkage size of the dielectric layer of the testing element relative to the organic layer.
According to the embodiment of the application, an electrical monitoring method is adopted, namely, a testing element group is monitored in real time in a production line through electrical testing Equipment (EPM) in the production line, the etching depth of the pixel isolation column of the display area can be accurately monitored in real time, and therefore the pixel isolation column can effectively prevent pixel crosstalk.
Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present application.
Drawings
The foregoing and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
fig. 1 is a schematic structural diagram of a Test Element Group (TEG) located in a non-display region according to an embodiment of the present disclosure;
fig. 2 is a top view of a Test Element Group (TEG) located in a non-display region according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a pixel isolation pillar scheme of a display panel (display area) according to an embodiment of the present disclosure;
fig. 4 is a schematic flowchart of a method for manufacturing a display panel according to an embodiment of the present disclosure;
FIG. 5 is a schematic structural diagram illustrating a different process for fabricating a display panel according to an embodiment of the present disclosure;
FIG. 6 is a schematic diagram of a process of fabricating the display panel shown in FIG. 5.
Reference numerals are as follows:
101 a-a first test part, 102-a flat layer, 103 a-a dielectric layer, 104 a-an organic layer, 105 a-a second test part, 111 a-a part to be tested, 106-a first test pad, 107-a second test pad;
100-substrate, 101 b-source drain layer, 103 b-inorganic layer, 104 b-pixel definition layer, 111 b-pixel isolation column, 108-anode layer, 109-photoresist.
Detailed Description
The present application is described in detail below and examples of embodiments of the present application are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements with the same or similar functionality throughout. In addition, if a detailed description of the known art is unnecessary for the features of the present application shown, it is omitted. The embodiments described below with reference to the drawings are exemplary only for the purpose of explaining the present application and are not to be construed as limiting the present application.
It will be understood by those within the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. Further, "connected" or "coupled" as used herein may include wirelessly connected or wirelessly coupled. As used herein, the term "and/or" includes all or any element and all combinations of one or more of the associated listed items.
The inventor of the present application has studied and found, as shown in fig. 3, that in the conventional pixel isolation pillar scheme of the display panel, the etching depth a of the pixel isolation pillar is a very critical parameter, for monitoring the value of the etching depth a, since the inorganic layer 103b is shielded by the pixel definition layer 104b, the boundary cannot be resolved, the commonly used optical line width test is not applicable, and meanwhile, because the top of the pixel definition layer 104b is relatively flat, the in-line Scanning Electron Microscope (SEM) monitoring cannot monitor the value of the etching depth a.
The currently used means for monitoring the etching depth a value is to take out the product and perform FIB (focused Ion Beam) sample cutting test in a laboratory outside the production line, and the method is relatively troublesome and cannot perform real-time monitoring.
The application provides a test element group, a display panel, a preparation method of the display panel and a test method of the display panel, and aims to solve the technical problems in the prior art.
The following describes the technical solutions of the present application and how to solve the above technical problems with specific embodiments.
The embodiment of the application provides a test element group, which is applied to a display panel, the display panel comprises a display area and a non-display area, the specific setting mode of the display area and the non-display area is similar to that of the prior art, and details are not repeated here, the display area comprises a plurality of pixel isolation columns located between two adjacent light emitting units, specifically, as shown in fig. 3, the pixel isolation columns 111b are represented by dotted frame portions, the pixel isolation columns 111b can play a role in preventing pixel crosstalk, and the left side of the dotted frame in fig. 3 can also frame the whole inorganic layer 103 b. The pixel isolation column 111b structure is formed by adding two exposure processes and forming a pit (i.e., etching depth a in fig. 3) by wet etching the dielectric layer 103a, the pixel isolation column 111b structure can save energy space, can arrange more pixels, and the specific manufacturing process of the pixel isolation column 111b is similar to that of the prior art, and is not repeated here.
As shown in fig. 1, the test element group in the embodiment of the present application is located in the non-display region of the display panel, the test element group includes test elements, and the number of the test elements is set according to actual production; the test element includes a portion to be tested 111a, a first test portion 101a and a second test portion 105a, and the first test portion 101a and the second test portion 105a are respectively located at both sides of the portion to be tested 111 a. The part to be tested 111a comprises a dielectric layer 103a and an organic layer 104a which are arranged in a laminated mode, the dielectric layer 103a is close to the first testing part 101a, the organic layer 104a is close to the second testing part 105a, and the retraction size (such as the retraction size a in fig. 1) of the dielectric layer 103a relative to the organic layer 104a is the same as the etching depth (such as the etching depth a in fig. 3) of the pixel isolation column 111 b.
The first test portion 101a and the second test portion 105a are electrically connected to an electrical test device (not shown), and the capacitance value of the test element as a capacitor is monitored by the electrical test device.
Alternatively, the material of the dielectric layer 103a includes an inorganic material, and the inorganic material may include: at least one of SiNx (silicon nitride), silicon oxide, aluminum oxide, titanium oxide, silicon oxynitride, and silicon oxycarbide. In specific implementation, the material of the dielectric layer 103a in this embodiment may be the same as the material of the inorganic layer 103b in the display region, for example: the material of the inorganic layer 103b in the display region is SiNx, and the material of the dielectric layer 103a in the embodiment of the present application is SiNx.
Optionally, the material of the organic layer 104a in this embodiment may be the same as the material of the pixel defining layer 104b in the display area, and the material of the first testing portion 101a in this embodiment may be the same as the material of the source drain layer 101b in the display area, so that the material selection cost can be reduced, and further the production cost can be reduced.
Optionally, the second testing portion 105a in this embodiment is a conductive layer, specifically, the second testing portion 105a is made of a metal material, if the display panel is a touch display panel with a touch function, the display panel includes a touch electrode, and the touch electrode may be made of a metal material, then the material of the second testing portion 105a in this embodiment may be the same as the material of the touch electrode, so that the material selection cost can be reduced, and further the production cost is reduced.
It should be noted that the test element group located in the non-display area may be manufactured through the same manufacturing process as the pixel isolation pillars 111b located in the display area, so that the characteristic value of the pixel (e.g., the etching depth of the pixel isolation pillar 111 b) in the display area may be monitored by testing the characteristic value (e.g., the shrinking size of the dielectric layer 103a relative to the organic layer 104 a) of the test element group.
The embodiment of the application provides a Test Element Group (TEG), which is located in a non-display area. The test element group comprises a test element, the test element comprises a part to be tested 111a, a first test part 101a and a second test part 105a, the first test part 101a and the second test part 105a which are used as capacitors of the test element are electrically connected with an electrical test device, the capacitance value of the test element which is used as a capacitor is obtained by monitoring of the electrical test device, the electrical test device can determine the retraction size of a dielectric layer 103a of the test element relative to an organic layer 104a according to the capacitance value of the test element which is used as a capacitor, and the retraction size of the dielectric layer 103a relative to the organic layer 104a is the same as the etching depth of a pixel isolation column 111b, so that the etching depth a of the pixel isolation column 111b positioned in a display area can be determined by determining the retraction size of the dielectric layer 103a of the test element relative to the organic layer 104 a.
In the embodiment of the application, by adopting an electrical monitoring method, namely, by monitoring the test element group in real time in a production line through an electrical test Equipment (EPM) in the production line, the etching depth a of the pixel isolation column 111b in the display area can be accurately monitored in real time, so that the pixel isolation column 111b can effectively prevent pixel crosstalk, and meanwhile, the monitoring method is convenient and has a large monitoring amount, and can be used as a mode of batch monitoring of mass production.
In some embodiments, as shown in fig. 1, the test device further includes a flat layer 102, the flat layer 102 is disposed on a side of the first test portion 101a, the portion to be tested 111a is disposed on a side of the flat layer 102 away from the first test portion 101a, and the second test portion 105a is disposed on a side of the portion to be tested 111a away from the flat layer 102. In specific implementation, the flat layer 102 included in the test element and the flat layer in the display area of the display panel are arranged on the same layer, that is, the flat layer 102 included in the test element and the flat layer in the display area of the display panel are manufactured by the same composition process.
In some embodiments, as shown in fig. 2, an orthographic projection of the second test portion 105a on the planarization layer 102 covers an orthographic projection of the dielectric layer 103a (T1) on the planarization layer 102, and an area of the orthographic projection of the second test portion 105a on the planarization layer 102 is larger than an area of the orthographic projection of the dielectric layer 103a on the planarization layer 102.
In some embodiments, as shown in fig. 2, the orthographic projection of the first test portion 101a on the planarization layer 102 covers the orthographic projection of the second test portion 105a on the planarization layer 102, and the area of the orthographic projection of the first test portion 101a on the planarization layer 102 is larger than the area of the orthographic projection of the second test portion 105a on the planarization layer 102.
Referring to fig. 1 and 2, the second test portion 105a (tma) and the organic layer 104a (pdl) are both square and have the same length, b, the first test portion 101a (tma) is also square and has the length of c, and the dielectric layer 103a (T1) has a shrinking size a relative to the organic layer 104a (pdl). It should be noted that four more blocks, i.e., the organic layer 104a (pdl), are shown in the top view of fig. 2 to prevent the whole organic layer 104a from dropping.
By providing the above-described flat layer 102 and the setting of the area of each layer, it is possible to make the test easier and more accurate.
In some embodiments, as shown in fig. 1-2, the organic layer 104a (pdl) and the pixel defining layer 104b included in the display region are disposed in the same layer, that is, the organic layer 104a and the pixel defining layer 104b are manufactured by the same patterning process, which can reduce the production cost.
In some embodiments, as shown in fig. 2, the test element group further comprises: a first test PAD 106(PAD1) and a second test PAD 107(PAD 2). The first testing portion 101a is electrically connected to an electrical testing device (not shown) through a first testing PAD 106(PAD1), and the second testing portion 105a is electrically connected to the electrical testing device (not shown) through a second testing PAD 107(PAD 2).
In some embodiments, the first test part 101a and the first test pad 106 are both disposed in the same layer as the source and drain layer 101b included in the display region; the second testing part 105a and the second testing pad 107 are arranged on the same layer, and the arrangement on the same layer is made by adopting the same composition process, so that the process time can be saved, and the production cost can be reduced.
Of course, each layer of the test element group may be disposed in a different layer from the film layer of the display region, and may be separately manufactured by using an independent manufacturing process, which is not limited in the present application.
As shown in fig. 1, a cross-sectional view of a test element group according to an embodiment of the present disclosure, a capacitance Cap1 is formed by a second test part 105a (e.g., TMA layer) and a first test part 101a (e.g., SD layer), and when an etching depth a changes, a change in Cap1 is caused, so that an etching depth a value is calculated from electrical characteristics Cap 1.
The principle and the calculation method for testing the test element group by the electrical test equipment are shown in fig. 1, and the top view is shown in fig. 2. The test value is Cap1 ═ Cap (TMA to SD), Cap1 corresponds to the capacitance formed by second test part 105a and first test part 101a in fig. 1, Cap (TMA to SD) corresponds to second test part 105a to first test part 101a in fig. 1, and the capacitance value of PLN (corresponding to flat layer 102 in fig. 1) is obtained from the test:
Wherein epsilonPLNPi, k is constant, S1 ═ b 2; d1 (THK — PLN (referring to the thickness of the PLN layer) is an existing process parameter, which can be derived,
similarly, the capacitance of PDL (corresponding to organic layer 104a in fig. 1) is:
wherein epsilonPDLPi, k is constant, S2 ═ b 2; d2, THK _ PDL (thickness of PDL layer) is a known process parameter, which can be derived,
the capacitance of T1 (corresponding to dielectric layer 103a in fig. 1) is:
wherein epsilonT1N, k is a constant, S3＝(b-2a)2(ii) a d 3-THK _ T1 (referring to the thickness of the T1 layer) is an existing process parameter, which can be derived,
and according to the series capacitance calculation formula:
it can be derived that,
the etching depth a of the pixel isolation column can be calculated by substituting the previous formula
Wherein the Cap1 is a test value, and the Cap2 and the Cap3 can be calculated according to the existing values; b, THK _ T1 is a known value, and the value a can be calculated by substituting expressions (1) and (2) into expression (4), namely the etching depth a is calculated.
Therefore, the embodiment of the application adopts an electrical monitoring method, namely, a Test Element Group (TEG) is monitored in real time in a production line through an electrical Test Equipment (EPM) in the production line, so that the etching depth a of the pixel isolation column 111b in the display area can be accurately monitored in real time, and meanwhile, the monitoring method is convenient and large in monitoring amount and can be used as a mode for batch monitoring of mass production.
Based on the same inventive concept, an embodiment of the present application provides a display panel, which includes a display area and a non-display area, wherein the display area includes a plurality of light emitting units arranged in an array, a pixel isolation pillar 111b is disposed between adjacent light emitting units, and the non-display area is provided with the test element group provided in any of the above embodiments.
The display panel provided by the embodiment of the present application has the same inventive concept and the same advantages as the previous embodiments, and the contents not shown in detail in the display panel can refer to the previous embodiments, and are not described herein again.
Based on the same inventive concept, embodiments of the present application provide a display device including a display panel as provided in any of the above embodiments.
The display device provided by the embodiment of the present application has the same inventive concept and the same advantageous effects as the previous embodiments, and the details that are not shown in detail in the display device can refer to the previous embodiments, and are not described herein again.
Based on the same inventive concept, an embodiment of the present application provides a method for manufacturing a display panel as in any one of the above embodiments, where the display panel includes a display area and a non-display area, and a flowchart of the method is shown in fig. 4, and includes the following steps S1-S4: the method comprises the following steps:
S1: providing a substrate;
s2: manufacturing a driving circuit layer and a first testing part on one side of a substrate, wherein the driving circuit layer is positioned in a display area, and the first testing part is positioned in a non-display area;
s3: manufacturing a pixel isolation column and a part to be tested on one side of the driving circuit layer and one side of the first testing part, which are far away from the substrate, wherein the pixel isolation column is positioned in the display area, and the part to be tested is positioned in the non-display area;
s4: and manufacturing a second testing part on one side of the part to be tested, which is far away from the substrate.
According to the preparation method of the display panel, the pixel isolation columns and the part to be tested are manufactured on one side, away from the substrate, of the driving circuit layer and the first testing part, the pixel isolation columns are located in the display area, the part to be tested is located in the non-display area, the second testing part is manufactured on one side, away from the substrate, of the part to be tested, and the electrical testing equipment enables the light emitting units arranged in the array of the testing element group and the display area to be manufactured through one-time process through the first testing part and the second testing part, so that the process preparation flow can be reduced, and the time is saved.
In some embodiments, fabricating the driving circuit layer and the first test part on one side of the substrate includes:
a plurality of thin film transistors arranged in an array are formed on a substrate, each thin film transistor comprises a grid layer, a source drain layer and an active layer, and a first testing part and the source drain layer are manufactured in the same layer.
After the driving circuit layer and the first testing part are manufactured on one side of the substrate, the method further comprises the following steps:
and manufacturing a flat layer on one side of the driving circuit layer and the first testing part far away from the substrate, wherein the flat layer covers the driving circuit layer and the first testing part.
In some embodiments, the fabricating the pixel isolation pillar and the portion to be tested on the side of the driving circuit layer and the first testing portion away from the substrate includes:
depositing an inorganic layer film on one side of the flat layer far away from the substrate, and forming a dielectric layer and an inorganic layer through a composition process, wherein the inorganic layer is positioned in the display area, and the dielectric layer is positioned in the non-display area;
depositing an organic layer film on one side of the dielectric layer and the inorganic layer far away from the substrate, forming a pixel defining layer and an organic layer through a composition process, wherein the pixel defining layer is positioned in the display area, the organic layer is positioned in the non-display area, the dielectric layer and the organic layer form a part to be detected, and the inorganic layer and the pixel defining layer form a pixel isolation column.
The following describes in detail a manufacturing process of a display panel according to an embodiment of the present application with reference to fig. 5 and 6. The patterning process in the embodiment of the present application includes a part or all of coating, exposing, developing, etching, and removing of the photoresist.
As shown in fig. 5(a), a substrate 100 (the substrate 100 may be a glass substrate or a flexible substrate) is provided, a driving circuit layer and a first testing portion 101a are manufactured on one side of the substrate 100 by using a patterning process, the driving circuit layer is located in a display area, the first testing portion 101a is located in a non-display area, the driving circuit layer includes a plurality of thin film transistors arranged in an array, the thin film transistors include a gate layer, a source drain layer 101b and an active layer, the first testing portion 101a and the source drain layer 101b are manufactured in the same layer, and only the source drain layer 101b located in the display area is shown in the figure. Then, a flat layer 102 is formed on the side of the driver circuit layer and the first test portion 101a away from the substrate 100, and the flat layer 102 covers the driver circuit layer and the first test portion 101 a.
As shown in fig. 5(b), next, an inorganic layer film is deposited on the side of the planarization layer 102 away from the substrate 100, and the material of the inorganic layer film may include: at least one of silicon nitride, silicon dioxide, aluminum oxide, titanium oxide, silicon oxynitride, and silicon oxycarbide.
As shown in fig. 5(c) to 5(d), next, a dielectric layer 103a and an inorganic layer 103b are formed through a patterning process, the inorganic layer 103b is located in the display region, and the dielectric layer 103a is located in the non-display region. Fig. 5(c) shows the structure after coating, exposure, development and etching of the photoresist, when a portion of the photoresist remains, and fig. 5(d) shows the structure after removal of the photoresist.
As shown in fig. 6(e), an anode layer film is then deposited on the dielectric layer 103a and the inorganic layer 103b on the side away from the substrate 100, an anode layer 108 is formed in the display region through a patterning process, and the anode layer film is removed through an etching step in the patterning process in the non-display region. Then, depositing an organic layer film on the dielectric layer 103a and the inorganic layer 103b away from the substrate 100, forming a pixel defining layer 104b through a patterning process, wherein the pixel defining layer 104b is located in the display region, and the patterning process of the pixel defining layer 104b is similar to that of the prior art, and is not repeated here.
As shown in fig. 6(f), next, a photoresist 109 is coated, and a portion of the photoresist is removed through exposure and development, leaving the photoresist 109 at the position where the pixel isolation pillars 111b and the pixel defining layer 104b need to be formed in the display region, and leaving the photoresist 109 at the position where the organic layer 104a needs to be formed in the non-display region.
As shown in fig. 6(g), next, the organic layer film not covered by the photoresist 109 is removed by vertical etching using dry etching, and the organic layer 104a located in the non-display region and the pixel defining layer 104b located in the display region are formed.
As shown in fig. 6(h), next, wet etching is adopted to laterally etch the inorganic layer 103b to form a pixel isolation pillar 111b in the display area, the etching depth of the pixel isolation pillar 111b is a, and a portion to be measured is formed in the non-display area, and the retraction dimension a formed by the portion to be measured (including the dielectric layer 103a and the organic layer 104a which are stacked) is equal to the etching depth a of the pixel isolation pillar 111 b.
As shown in fig. 6(i), next, the photoresist 109 is removed.
Finally, a second testing portion 105a (not shown) is formed on the portion to be tested 111a and the pixel isolation pillar 111b away from the substrate 100 to form a testing device in the embodiment of the present application in the non-display region.
Based on the same inventive concept, an embodiment of the present application provides a method for testing a display panel provided in any one of the above embodiments, including:
applying an electrical signal to the first test part 101a and the second test part 105 a;
measuring the capacitance value of the test element as a capacitor;
and determining the shrinking size of the dielectric layer 103a of the test element relative to the organic layer 104a according to the capacitance value so as to determine the etching depth of the pixel isolation column 111 b.
Specifically, the electrical test apparatus electrically connects the first test part 101a and the second test part 105a, respectively, and applies a voltage signal to the first test part 101a and the second test part 105 a. The specific test principle can be introduced by referring to the above principle, and the capacitance value of the test element as a capacitor can be obtained by testing the test element of the test element group, and since the shrinking size of the dielectric layer 103a of the test element relative to the organic layer 104a is the same as the etching depth of the pixel isolation column 111b, the etching depth of the pixel isolation column 111b can be determined by determining the shrinking size of the dielectric layer 103a of the test element relative to the organic layer 104 a.
According to the embodiment of the application, the testing element group is monitored in real time in the production line through the electrical testing equipment in the production line, the etching depth of the pixel isolation column of the display area can be accurately monitored in real time, and meanwhile, the monitoring method is convenient and large in monitoring amount and can be used as a mode for batch monitoring of mass production.
By applying the embodiment of the application, the following beneficial effects can be at least realized:
according to the testing component group provided by the embodiment of the application, the testing component group is located in the non-display area. The testing element group comprises a testing element, the testing element comprises a part to be tested, a first testing part and a second testing part, the first testing part and the second testing part of the testing element as capacitors are electrically connected with an electrical testing device, the capacitance value of the testing element as a capacitor is obtained by monitoring the electrical testing device, the electrical testing device can determine the shrinking size of a dielectric layer of the testing element relative to an organic layer according to the capacitance value of the testing element as a capacitor, and therefore the etching depth of a pixel isolation column located in a display area is determined.
According to the embodiment of the application, an electrical monitoring method is adopted, namely, a testing element group is monitored in real time in a production line through an electrical testing device (EPM) in the production line, the etching depth of the pixel isolation column of the display area can be accurately monitored in real time, and therefore the pixel isolation column can effectively prevent pixel crosstalk.
Those of skill in the art will understand that various operations, methods, steps in the flow, measures, schemes discussed in this application can be alternated, modified, combined, or deleted. Further, various operations, methods, steps, measures, schemes in the various processes, methods, procedures that have been discussed in this application may be alternated, modified, rearranged, decomposed, combined, or eliminated. Further, the steps, measures, and schemes in the various operations, methods, and flows disclosed in the present application in the prior art can also be alternated, modified, rearranged, decomposed, combined, or deleted.
In the description of the present application, it is to be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, merely for convenience of description and simplicity of description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, are not to be construed as limiting the present application.
The terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, the meaning of "a plurality" is two or more unless otherwise specified.
In the description of the present application, it should be noted that, unless otherwise explicitly stated or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, a fixed connection, a detachable connection, or an integral connection; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in this application will be understood to be a specific case for those of ordinary skill in the art.
The particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.
It should be understood that, although the steps in the flowcharts of the figures are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and may be performed in other orders unless explicitly stated herein. Moreover, at least a portion of the steps in the flow chart of the figure may include multiple sub-steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, which are not necessarily performed in sequence, but may be performed alternately or alternately with other steps or at least a portion of the sub-steps or stages of other steps.
The foregoing is only a few embodiments of the present application and it should be noted that those skilled in the art can make various improvements and modifications without departing from the principle of the present application, and that these improvements and modifications should also be considered as the protection scope of the present application.
Claims (13)
1. A test component group is applied to a display panel, the display panel comprises a display area and a non-display area, the display area comprises a plurality of pixel isolation columns positioned between two adjacent light-emitting units, and the test component group is characterized in that the test component group is positioned in the non-display area and comprises a test component;
the test element comprises a part to be tested, a first test part and a second test part, wherein the first test part and the second test part are respectively positioned at two sides of the part to be tested;
the part to be tested comprises a dielectric layer and an organic layer which are arranged in a laminated mode, the dielectric layer is close to the first testing part, the organic layer is close to the second testing part, and the shrinking-in size of the dielectric layer relative to the organic layer is the same as the etching depth of the pixel isolation column;
the first testing part and the second testing part are electrically connected with electrical testing equipment, and the capacitance value of the testing element as a capacitor is obtained by monitoring the electrical testing equipment.
2. The group of test elements of claim 1, wherein the test element further comprises a planar layer;
the flat layer is located on one side of the first testing portion, the portion to be tested is located on one side, away from the first testing portion, of the flat layer, and the second testing portion is located on one side, away from the flat layer, of the portion to be tested.
3. The test element group of claim 2,
the orthographic projection of the second testing part on the flat layer covers the orthographic projection of the dielectric layer on the flat layer, and the area of the orthographic projection of the second testing part on the flat layer is larger than that of the orthographic projection of the dielectric layer on the flat layer.
4. The test element group of claim 2,
the orthographic projection of the first test part on the flat layer covers the orthographic projection of the second test part on the flat layer, and the area of the orthographic projection of the first test part on the flat layer is larger than that of the orthographic projection of the second test part on the flat layer.
5. The test element group of claim 1,
the organic layer and the pixel definition layer included in the display area are arranged in the same layer.
6. The test element group of claim 1, further comprising: a first test pad and a second test pad;
the first test part is electrically connected with the electrical test equipment through the first test pad, and the second test part is electrically connected with the electrical test equipment through the second test pad.
7. The test element group of claim 6,
the first testing part and the first testing pad are arranged on the same layer with the source drain layer included in the display area;
the second testing part and the second testing pad are arranged on the same layer.
8. A display panel comprising a display region and a non-display region, wherein the display region comprises a plurality of light emitting cells arranged in an array, pixel isolation pillars are disposed between adjacent light emitting cells, and the non-display region is provided with the test element group according to any one of claims 1 to 7.
9. A display device characterized by comprising the display panel according to claim 8.
10. A method for manufacturing a display panel according to claim 8, the display panel including a display area and a non-display area, comprising:
Providing a substrate;
manufacturing a driving circuit layer and a first testing part on one side of the substrate, wherein the driving circuit layer is positioned in the display area, and the first testing part is positioned in the non-display area;
manufacturing a pixel isolation column and a part to be tested on one side of the driving circuit layer and one side of the first testing part, which are far away from the substrate, wherein the pixel isolation column is positioned in the display area, and the part to be tested is positioned in the non-display area;
and manufacturing a second testing part on one side of the part to be tested, which is far away from the substrate.
11. The method for manufacturing a display panel according to claim 10, wherein the manufacturing of the driver circuit layer and the first test portion on one side of the substrate includes:
forming a plurality of thin film transistors arranged in an array on the substrate, wherein each thin film transistor comprises a gate layer, a source drain layer and an active layer, and the first testing part and the source drain layer are manufactured in the same layer;
after the driving circuit layer and the first testing part are manufactured on one side of the substrate, the method further comprises the following steps:
and manufacturing a flat layer on one side of the driving circuit layer and the first testing part, which is far away from the substrate, wherein the flat layer covers the driving circuit layer and the first testing part.
12. The method for manufacturing a display panel according to claim 11, wherein the manufacturing of the pixel isolation pillar and the portion to be tested on the side of the driving circuit layer and the first testing portion away from the substrate includes:
depositing an inorganic layer film on one side of the flat layer far away from the substrate, and forming a dielectric layer and an inorganic layer through a composition process, wherein the inorganic layer is positioned in the display area, and the dielectric layer is positioned in the non-display area;
depositing an organic layer film on one sides of the dielectric layer and the inorganic layer far away from the substrate, and forming a pixel definition layer and an organic layer through a composition process, wherein the pixel definition layer is positioned in the display area, the organic layer is positioned in the non-display area, the dielectric layer and the organic layer form the part to be measured, and the inorganic layer and the pixel definition layer form a pixel isolation column.
13. The method for testing a display panel according to claim 8, comprising:
applying an electrical signal to the first test portion and the second test portion;
measuring the capacitance value of the test element as a capacitor;
and determining the shrinking size of the dielectric layer of the test element relative to the organic layer according to the capacitance value so as to determine the etching depth of the pixel isolation column.
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