CN112787503B - Current adjustable self-adaptive self-biased charge pump - Google Patents

Current adjustable self-adaptive self-biased charge pump Download PDF

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CN112787503B
CN112787503B CN202110017481.7A CN202110017481A CN112787503B CN 112787503 B CN112787503 B CN 112787503B CN 202110017481 A CN202110017481 A CN 202110017481A CN 112787503 B CN112787503 B CN 112787503B
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transistor
nmos
signal input
drain
gate
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CN112787503A (en
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周前能
杨小旭
李红娟
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Chongqing University of Post and Telecommunications
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Chongqing University of Post and Telecommunications
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices

Abstract

The invention discloses a current adjustable self-adaptive bias charge pump, which comprises an adjustable self-adaptive bias circuit, a charge pump core circuit and the like. The adjustable self-adaptive bias circuit adopts the NMOS tube M3 grid electrode to be connected with the output end of the charge pump to generate the bias current of the output voltage of the self-adaptive charge pump, and adopts the input end SL1, the input end SL2 and the input end SL3 to respectively control the grid electrodes of the NMOS tube M8, the NMOS tube M9 and the NMOS tube M10 to generate the adjustable bias current; in the charge pump core circuit, the error amplifier op1 and the error amplifier op2 are connected by unit gain and are connected with the 4 NMOS switching tubes and the 4 PMOS switching tubes to realize a bootstrap technique to eliminate the charge sharing effect of the charge pump, and meanwhile, the error amplifier op1 and the error amplifier op2 are connected in parallel to improve the current driving capability, so that the current adjustable self-adaptive self-biasing charge pump is realized.

Description

Current adjustable self-adaptive self-biased charge pump
Technical Field
The invention belongs to the technical field of microelectronics, and particularly relates to a self-adaptive self-biased charge pump with adjustable current.
Background
The charge pump is an important functional module of the phase-locked loop, and the performance of the charge pump directly affects the overall performance of the phase-locked loop. Fig. 1 is a schematic diagram of a basic charge pump, in which signals at a signal input terminal UP and a signal input terminal DN are from an output signal of a front-stage phase frequency detector, CL is a filter capacitor of a rear-stage filter, and when a switch S1 is closed and a switch S2 is opened, a charging current source IUP charges the filter capacitor CL of the rear-stage filter through a charge pump output terminal VC, and a voltage of the charge pump output terminal VC rises accordingly; when the switch S1 is turned off and S2 is turned on, the discharging current source IDN discharges the filter capacitor CL of the post filter through the charge pump output terminal VC, and the voltage of the charge pump output terminal VC decreases accordingly; when the switch S1 is turned on or off simultaneously with the switch S2, the voltage at the output terminal VC of the charge pump remains unchanged. The charge/discharge current of the conventional charge pump shown in fig. 1 cannot be dynamically adjusted with the output voltage of the charge pump, thereby limiting the application of the charge pump in high performance systems.
Disclosure of Invention
The present invention is directed to solving the above problems of the prior art. A current trimmable adaptive self-biasing charge pump is provided. The technical scheme of the invention is as follows:
a current trimmable adaptive self-biased charge pump, comprising: the adjustable self-adaptive bias circuit comprises an adjustable self-adaptive bias circuit and a charge pump core circuit, wherein the signal output end of the adjustable self-adaptive bias circuit is connected with the signal input end of the charge pump core circuit, the signal output end of the charge pump core circuit is connected with the signal input end of the adjustable self-adaptive bias circuit, the adjustable self-adaptive bias circuit provides a bias signal for the charge pump core circuit through the grid electrode of a PMOS (P-channel metal oxide semiconductor) tube M12 and the grid electrode of an NMOS (N-channel metal oxide semiconductor) tube M14, and the charge pump core circuit provides charge/discharge current for a filter capacitor of a rear-stage circuit through an output end VC.
Further, the adjustable adaptive bias circuit comprises: a PMOS transistor M1, a PMOS transistor M2, an NMOS transistor M3, an NMOS transistor M4, an NMOS transistor M5, an NMOS transistor M6, an NMOS transistor M7, an NMOS transistor M8, an NMOS transistor M9, an NMOS transistor M10, a PMOS transistor M11, a PMOS transistor M12, a PMOS transistor M13 and an NMOS transistor M14, wherein a source of the PMOS transistor M1 is connected to a source of the PMOS transistor M2, a source of the PMOS transistor M11, a source of the PMOS transistor M12, a source of the PMOS transistor M13 and an external power supply VDD, a gate of the PMOS transistor M1 is connected to a gate of the PMOS transistor M2, a drain of the PMOS transistor M1 and a drain of the NMOS transistor M3, a source of the NMOS transistor M3 is connected to a source of the NMOS transistor M3, a drain of the NMOS transistor M3 and an external ground, a gate of the PMOS transistor M3 is connected to a gate of the NMOS transistor M3, a gate of the PMOS transistor M3, a drain of the NMOS transistor M3, a drain of the transistor M3, a gate of the NMOS transistor M3, a drain of the transistor M3, a gate of the transistor M3, a drain of the NMOS transistor M3, a drain of the transistor M3, a gate of the transistor M3, a drain of the transistor M3, a transistor 3, a drain of the transistor M3, a gate of the transistor M3, a drain of the transistor M3, a gate of the transistor 3, a transistor M3, a gate of the transistor M3, a gate of the transistor 3, a transistor M3, a transistor M3, a transistor 3, a gate of a transistor M3, a transistor M, The grid electrode of the PMOS tube M24, the drain electrode of the PMOS tube M12, the drain electrode of the PMOS tube M11, the drain electrode of the NMOS tube M8, the drain electrode of the NMOS tube M9 and the drain electrode of the NMOS tube M10 are connected, the grid electrode of the NMOS tube M8 is connected with the signal input end SL1, the grid electrode of the NMOS tube M9 is connected with the signal input end SL2, the grid electrode of the NMOS tube M10 is connected with the signal input end SL3, the source electrode of the NMOS tube M8 is connected with the drain electrode of the NMOS tube M5, the source electrode of the NMOS tube M9 is connected with the drain electrode of the NMOS tube M6, the source electrode of the NMOS tube M10 is connected with the drain electrode of the NMOS tube M7, and the drain electrode of the PMOS tube M13 is respectively connected with the grid electrode of the NMOS tube M14, the drain electrode of the NMOS tube M14, the grid electrode of the NMOS tube M15, the bias end Vb1 of the error amplifier 1 and the bias end Vb2 of the error amplifier 2.
Furthermore, the gate of the NMOS transistor M3 in the trimmable adaptive bias circuit is connected to the output terminal VC of the charge pump, so that the drain current I of the NMOS transistor M33Dynamically tracking charge/discharge current of charge pump, i.e. drain current I of NMOS transistor M33Dynamically tracking voltage V of output VC of charge pumpCAnd the drain current I of the NMOS transistor M33Is provided with
Figure BDA0002887474510000021
Wherein, munFor electron mobility, CoxIs the unit area gate oxide capacitance (W/L)3Is the channel width-length ratio, V, of the NMOS transistor M3THnIs the threshold voltage of the NMOS transistor.
Further, the channel width-length ratio of the PMOS transistor M2 in the trimmable adaptive bias circuit is N times that of the PMOS transistor M1, the NMOS transistor M4, the NMOS transistor M5, the NMOS transistor M6 and the NMOS transistor M7 have the same channel width-length ratio, the input signals of the signal input terminal SL1, the signal input terminal SL2 and the signal input terminal SL3 are all digital signals, and the signal input terminal SL1, the signal input terminal SL2 and the signal input terminal SL3 respectively control the voltages of the gate of the NMOS transistor M8, the gate of the NMOS transistor M9 and the gate of the NMOS transistor M10, so as to realize the trimmable charge/discharge current of the charge pump, the PMOS transistor M13 is completely the same as the PMOS transistor M12, the gate of the PMOS transistor M11 is controlled by the digital signal of the signal input terminal EN, and when the digital signal of the signal input terminal EN is controlled to be at low level "0", the drain current I13 of the PMOS transistor M1313And drain current I of NMOS transistor M1414Is I13＝I14When the digital signal at the signal input end EN is controlled to be at high level "1", the drain current I of the PMOS transistor M13 is equal to 013And drain current I of NMOS transistor M1414Is I13＝I14＝(sl1+sl2+sl3)×N×I3Wherein, sl is1Is the digital signal level of the signal input SL1, SL2Is the digital signal level of the signal input SL2, SL3Is the digital signal level, I, of the signal input SL33Is the drain current of the NMOS transistor M3.
Further, the charge pump core circuit includes: NMOS transistor M15, NMOS transistor M16, PMOS transistor M17, PMOS transistor M18, NMOS transistor M18, PMOS transistor M18, error amplifier op 18 and error amplifier op 18, wherein the source of PMOS transistor M18 is connected to external power VDD, the drain of PMOS transistor M18 is connected to the source of PMOS transistor M18, the drain of NMOS transistor M18 and the source of PMOS transistor M18, the gate of PMOS transistor M18 is connected to signal input terminal UP, the gate of NMOS transistor M18 is connected to the gate of NMOS transistor M18 and signal input terminal UPN, the drain of PMOS transistor M18 is connected to the source of NMOS transistor M18, the equidirectional input terminal of error amplifier op 4, the drain of error amplifier 18, the source of NMOS transistor M18 and the source of PMOS transistor M18, the drain of PMOS transistor M18 and the source of NMOS transistor M18, the gate of PMOS transistor M18 are connected to the gate of PMOS transistor M18, the signal input terminal DN, and the gate of PMOS transistor M18 are connected to the gate of PMOS transistor M18, the gate of signal input terminal M18, and the gate of PMOS transistor M18, the gate of PMOS transistor M18 are connected to the gate of the signal input terminal M18, and the gate of the signal input terminal M18, and the gate of the PMOS transistor M18, the signal input terminal M18, and the gate of the signal input terminal M18, and the drain of the gate of the signal input terminal M18 are connected to the PMOS transistor M18, respectively, and the drain of the PMOS transistor M18, the drain of the transistor M18, the PMOS transistor M18, and the drain of the signal input terminal M18, and the signal input terminal M18, the gate of the signal input terminal M18 are connected to the signal input terminal M18, the gate of the drain of the transistor M18, and the gate of the signal input terminal M18, and the drain of the signal input terminal M18, and the gate of the drain of the signal input terminal M18, and the gate of the transistor M18, the signal input terminal M18, and the drain of the gate of the drain of the signal input terminal M18, and the transistor M18, and the drain of the signal input terminal M18, and the gate of the transistor M18, and the, The drain electrode of the PMOS tube M18, the source electrode of the NMOS tube M19 and the drain electrode of the NMOS tube M15 are connected, the source electrode of the NMOS tube M15 is connected with an external ground GND, the grid electrode of the PMOS tube M23 is connected with a signal input end UP, the source electrode of the NMOS tube M22 is respectively connected with the drain electrode of the PMOS tube M23, the source electrode of the NMOS tube M18, the drain electrode of the PMOS tube M19, the grid electrode of the NMOS tube M3, the inverting input end of the error amplifier op1, the output end of the error amplifier op1, the inverting input end of the error amplifier op2, the output end of the error amplifier op2 and the output end VC of the charge pump, and the grid electrode of the NMOS tube M19 is connected with the signal input end DN.
Furthermore, in the charge pump core circuit, the error amplifier op1 and the error amplifier op2 are connected by unity gain, and are connected with the switching MOS transistors including the NMOS transistor M16, the PMOS transistor M17, the PMOS transistor M18, the NMOS transistor M19, the PMOS transistor M20, the NMOS transistor M21, the NMOS transistor M22, and the PMOS transistor M23 to achieve a "bootstrap" technique to eliminate the charge sharing effect of the charge pump, and meanwhile, the error amplifier op1 and the error amplifier op2 are connected in parallel to improve the current driving capability, the PMOS transistor M24 and the PMOS transistor M12 have the same channel width-length ratio, and the NMOS transistor M15 and the NMOS transistor M14 have the same channel width-length ratio.
Further, when the digital signal at the signal input end EN is controlled to be low level "0", the charging current I flowing through the PMOS transistor M24UPAnd the discharge current I flowing through the NMOS transistor M15DNIs IUP＝IDNWhen the digital signal at the signal input terminal EN is controlled to be high level "1", the digital signal flows through the PMOS transistor M24Charging current IUPAnd the discharge current I flowing through the NMOS transistor M15DNIs composed of
Figure BDA0002887474510000041
Wherein, sl is1Is the digital signal level of the signal input SL1, SL2Is the digital signal level of the signal input SL2, SL3The digital signal level of the signal input end SL3 is N, the ratio of the width-to-length ratio of the channel of the PMOS tube M2 to the width-to-length ratio of the channel of the PMOS tube M1 is munFor electron mobility, CoxIs the unit area gate oxide capacitance (W/L)3Is the channel width-length ratio, V, of the NMOS transistor M3CIs the voltage, V, of the output VC of the charge pumpTHnThe threshold voltage of the NMOS tube is the voltage V of VC at the output end of the charge pumpCThe direct feedback to the grid electrode of an NMOS tube M3 in the adjustable self-adaptive bias circuit (1) realizes the charging current I of a charge pumpUPAnd a discharge current IDNDynamically tracking the voltage of the output end VC of the charge pump, and realizing the charging current I through the signals of the input ends including the signal input end SL1, the signal input end SL2 and the signal input end SL3 in the adjustable self-adaptive bias circuit (1)UPAnd a discharge current IDNTrimming characteristics of (1).
The invention has the following advantages and beneficial effects:
the invention provides a current adjustable self-adaptive self-bias charge pump, wherein an adjustable self-adaptive bias circuit generates a bias current of an output voltage of a self-adaptive charge pump by adopting the technology that a grid electrode of an NMOS (N-channel metal oxide semiconductor) tube M3 is connected with an output end VC of the charge pump, so that a charging/discharging current of a core circuit of the charge pump dynamically tracks the output voltage of the charge pump, and the grid electrode of an NMOS tube M8, the grid electrode of an NMOS tube M9 and the grid electrode of the NMOS tube M10 are respectively controlled by adopting a signal input end SL1, a signal input end SL2 and a signal input end SL3 to generate the adjustable bias current, so that the charging current and the discharging current of the charge pump have adjustability; in the charge pump core circuit, the error amplifier op1 and the error amplifier op2 are connected by unity gain, and realize a 'bootstrap' technology together with a switch MOS transistor including an NMOS transistor M16, a PMOS transistor M17, a PMOS transistor M18, an NMOS transistor M19, a PMOS transistor M20, an NMOS transistor M21, an NMOS transistor M22 and a PMOS transistor M23 to eliminate a charge sharing effect of the charge pump, and simultaneously the error amplifier op1 and the error amplifier op2 adopt a parallel connection technology to improve current driving capability, so that the current adjustable self-adaptive self-bias charge pump is realized.
Drawings
FIG. 1 is a schematic diagram of a conventional charge pump in accordance with a preferred embodiment of the present invention;
FIG. 2 is a schematic diagram of a current trimmable adaptive self-biasing charge pump in accordance with a preferred embodiment of the present invention;
fig. 3 is a simulation diagram of the charging characteristics of a current trimmable adaptive self-biased charge pump according to a preferred embodiment of the present invention.
Fig. 4 is a simulation diagram of the discharge characteristics of a current trimmable adaptive self-biased charge pump according to a preferred embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described in detail and clearly with reference to the accompanying drawings. The described embodiments are only some of the embodiments of the present invention.
The technical scheme for solving the technical problems is as follows:
in the embodiment of the application, the adjustable self-adaptive bias circuit generates a bias current of an output voltage of a self-adaptive charge pump by adopting a technology that a grid electrode of an NMOS (N-channel metal oxide semiconductor) tube M3 is connected with an output end VC of the charge pump, so that a charging/discharging current of a core circuit of the charge pump dynamically tracks the output voltage of the charge pump, and the adjustable bias current is generated by respectively controlling a grid electrode of an NMOS tube M8, a grid electrode of an NMOS tube M9 and a grid electrode of the NMOS tube M10 by adopting a signal input end SL1, a signal input end SL2 and a signal input end SL3, so that the charging current and the discharging current of the charge pump have adjustability; in the charge pump core circuit, the error amplifier op1 and the error amplifier op2 are connected by unity gain, and realize a 'bootstrap' technology together with a switch MOS transistor including an NMOS transistor M16, a PMOS transistor M17, a PMOS transistor M18, an NMOS transistor M19, a PMOS transistor M20, an NMOS transistor M21, an NMOS transistor M22 and a PMOS transistor M23 to eliminate a charge sharing effect of the charge pump, and simultaneously the error amplifier op1 and the error amplifier op2 adopt a parallel connection technology to improve current driving capability, so that the current adjustable self-adaptive self-bias charge pump is realized.
In order to better understand the technical solutions, the technical solutions will be described in detail below with reference to the drawings and specific embodiments.
Examples
A current adjustable self-adaptive bias charge pump is shown in FIG. 2, and comprises an adjustable self-adaptive bias circuit 1, a charge pump core circuit 2;
wherein, the signal output end of the adjustable self-adapting bias circuit 1 is connected with the signal input end of the charge pump core circuit 2, and the signal output end of the charge pump core circuit 2 is connected with the signal input end of the adjustable self-adapting bias circuit 1; the adjustable self-adaptive bias circuit 1 provides adjustable bias current for the charge pump core circuit 2, and the charge pump core circuit 2 provides charge/discharge current for the filter capacitor of the post-stage circuit.
As a preferred technical solution, as shown in fig. 2, the adjustable adaptive bias circuit 1 includes: a PMOS transistor M1, a PMOS transistor M2, an NMOS transistor M3, an NMOS transistor M4, an NMOS transistor M5, an NMOS transistor M6, an NMOS transistor M7, an NMOS transistor M8, an NMOS transistor M9, an NMOS transistor M10, a PMOS transistor M11, a PMOS transistor M12, a PMOS transistor M13 and an NMOS transistor M14, wherein a source of the PMOS transistor M1 is connected to a source of the PMOS transistor M2, a source of the PMOS transistor M11, a source of the PMOS transistor M12, a source of the PMOS transistor M13 and an external power supply VDD, a gate of the PMOS transistor M1 is connected to a gate of the PMOS transistor M2, a drain of the PMOS transistor M1 and a drain of the NMOS transistor M3, a source of the NMOS transistor M3 is connected to a source of the NMOS transistor M3, a drain of the NMOS transistor M3 and an external ground, a gate of the PMOS transistor M3 is connected to a gate of the NMOS transistor M3, a gate of the PMOS transistor M3, a drain of the NMOS transistor M3, a drain of the transistor M3, a gate of the NMOS transistor M3, a drain of the transistor M3, a gate of the transistor M3, a drain of the NMOS transistor M3, a drain of the transistor M3, a gate of the transistor M3, a drain of the transistor M3, a transistor 3, a drain of the transistor M3, a gate of the transistor M3, a drain of the transistor M3, a gate of the transistor 3, a transistor M3, a gate of the transistor M3, a gate of the transistor 3, a transistor M3, a transistor M3, a transistor 3, a gate of a transistor M3, a transistor M, The grid electrode of the PMOS tube M24, the drain electrode of the PMOS tube M12, the drain electrode of the PMOS tube M11, the drain electrode of the NMOS tube M8, the drain electrode of the NMOS tube M9 and the drain electrode of the NMOS tube M10 are connected, the grid electrode of the NMOS tube M8 is connected with a signal input end SL1, the grid electrode of the NMOS tube M9 is connected with a signal input end SL2, the grid electrode of the NMOS tube M10 is connected with a signal input end SL3, the source electrode of the NMOS tube M8 is connected with the drain electrode of the NMOS tube M5, the source electrode of the NMOS tube M9 is connected with the drain electrode of the NMOS tube M6, the source electrode of the NMOS tube M10 is connected with the drain electrode of the NMOS tube M7, and the drain electrode of the PMOS tube M13 is respectively connected with the grid electrode of the NMOS tube M14, the drain electrode of the NMOS tube M14, the grid electrode of the NMOS tube M15, a bias end Vb1 of the error amplifier 1 and a bias end Vb2 of the error amplifier 2;
the charge pump core circuit 2 includes: NMOS transistor M15, NMOS transistor M16, PMOS transistor M17, PMOS transistor M18, NMOS transistor M18, PMOS transistor M18, error amplifier op 18 and error amplifier op 18, wherein the source of PMOS transistor M18 is connected to external power VDD, the drain of PMOS transistor M18 is connected to the source of PMOS transistor M18, the drain of NMOS transistor M18 and the source of PMOS transistor M18, the gate of PMOS transistor M18 is connected to signal input terminal UP, the gate of NMOS transistor M18 is connected to the gate of NMOS transistor M18 and signal input terminal UPN, the drain of PMOS transistor M18 is connected to the source of NMOS transistor M18, the equidirectional input terminal of error amplifier op 4, the drain of error amplifier 18, the source of NMOS transistor M18 and the source of PMOS transistor M18, the drain of PMOS transistor M18 and the source of NMOS transistor M18, the gate of PMOS transistor M18 are connected to the gate of PMOS transistor M18, the signal input terminal DN, and the gate of PMOS transistor M18 are connected to the gate of PMOS transistor M18, the gate of signal input terminal M18, and the gate of PMOS transistor M18, the gate of PMOS transistor M18 are connected to the gate of the signal input terminal M18, and the gate of the signal input terminal M18, and the gate of the PMOS transistor M18, the signal input terminal M18, and the gate of the signal input terminal M18, and the drain of the gate of the signal input terminal M18 are connected to the PMOS transistor M18, respectively, and the drain of the PMOS transistor M18, the drain of the transistor M18, the PMOS transistor M18, and the drain of the signal input terminal M18, and the signal input terminal M18, the gate of the signal input terminal M18 are connected to the signal input terminal M18, the gate of the drain of the transistor M18, and the gate of the signal input terminal M18, and the drain of the signal input terminal M18, and the gate of the drain of the signal input terminal M18, and the gate of the transistor M18, the signal input terminal M18, and the drain of the gate of the drain of the signal input terminal M18, and the transistor M18, and the drain of the signal input terminal M18, and the gate of the transistor M18, and the, The drain electrode of the PMOS tube M18, the source electrode of the NMOS tube M19 and the drain electrode of the NMOS tube M15 are connected, the source electrode of the NMOS tube M15 is connected with an external ground GND, the grid electrode of the PMOS tube M23 is connected with a signal input end UP, the source electrode of the NMOS tube M22 is respectively connected with the drain electrode of the PMOS tube M23, the source electrode of the NMOS tube M18, the drain electrode of the PMOS tube M19, the grid electrode of the NMOS tube M3, the inverting input end of the error amplifier op1, the output end of the error amplifier op1, the inverting input end of the error amplifier op2, the output end of the error amplifier op2 and the output end VC of the charge pump, and the grid electrode of the NMOS tube M19 is connected with the signal input end DN.
The gate of the NMOS transistor M3 in the trimmable adaptive bias circuit 1 is connected to the output end VC of the charge pump, so that the drain current I of the NMOS transistor M33Dynamically tracking charge/discharge current of charge pump (i.e. drain current I of NMOS transistor M3)3Dynamically tracking the voltage at the output terminal VC of the charge pump), the drain current I of the NMOS transistor M33Is provided with
Figure BDA0002887474510000081
In the formula, munFor electron mobility, CoxIs the unit area gate oxide capacitance (W/L)3Is the channel width-length ratio, V, of the NMOS transistor M3cIs the voltage, V, of the output VC of the charge pumpTHnThe charge pump charge/discharge current can be modified and adjusted by setting the threshold voltage of the NMOS transistor, the channel width-length ratio of the PMOS transistor M2 to be N times that of the PMOS transistor M1, the channel width-length ratios of the NMOS transistor M4, the NMOS transistor M5, the NMOS transistor M6 and the NMOS transistor M7 to be the same, the input signals of the signal input end SL1, the signal input end SL2 and the signal input end SL3 are all digital signals, the signal input end SL1, the signal input end SL2 and the signal input end SL3 respectively control the voltages of the grid of the NMOS transistor M8, the grid of the NMOS transistor M9 and the grid of the NMOS transistor M10, the PMOS transistor M13 and the PMOS transistor M12 are completely the same, the grid of the PMOS transistor M11 is controlled by the digital signal of the signal input end EN, and when the digital signal of the signal input end EN is controlled to be low level "0", the drain current I of the PMOS transistor M1313And drain current I of NMOS transistor M1414Is shown as I13＝I14When the digital signal at the signal input end EN is controlled to be at high level "1", the drain current I of the PMOS transistor M13 is equal to 013And drain current I of NMOS transistor M1414Is composed of
Figure BDA0002887474510000091
In the formula, sl1Is the digital signal level, SL, of the signal input SL12Is the digital signal level of the signal input SL2, SL3Is the digital signal level of the signal input terminal SL 3.
In the charge pump core circuit 2, the error amplifier op1 and the error amplifier op2 are prior art.
In the charge pump core circuit 2, the low-frequency gains of the error amplifier op1 and the error amplifier op2 are far greater than 1, the error amplifier op1 and the error amplifier op2 are connected by unit gain, and are connected with the switch MOS transistors including the NMOS transistor M16, the PMOS transistor M17, the PMOS transistor M18, the NMOS transistor M19, the PMOS transistor M20, the NMOS transistor M21, the NMOS transistor M22 and the PMOS transistor M23 to eliminate the charge sharing effect of the charge pump by a 'bootstrap' technology, meanwhile, the error amplifier op1 and the error amplifier op2 are connected in parallel to improve the current driving capability, the PMOS transistor M24 and the PMOS transistor M12 have the same channel width-length ratio, the NMOS transistor M15 and the NMOS transistor M14 have the same channel width-length ratio, and when the digital signal of the signal input end EN is controlled to be low level '0', the charging current I flowing through the PMOS transistor M24UPAnd the discharge current I flowing through the NMOS transistor M15DNIs IUP＝IDNWhen the digital signal at the signal input terminal EN is controlled to be at high level "1", the charging current I flowing through the PMOS transistor M24 is equal to 0UPAnd the discharge current I flowing through the NMOS transistor M15DNIs composed of
Figure BDA0002887474510000092
As shown in equation (3), the direct feedback of the output end VC of the charge pump to the gate of the NMOS transistor M3 in the trimmable adaptive bias circuit 1 realizes the charging current I of the charge pumpUPAnd a discharge current IDNDynamically tracking the voltage of the output end VC of the charge pump, and realizing the charging current I through the signals of the input ends of the signal input end SL1, the signal input end SL2, the signal input end SL3 and the like in the adjustable self-adaptive bias circuit 1UPAnd a discharge current IDNTrimming characteristics of (1).
Fig. 3 is a simulation curve of the charging characteristic of the current trimmable adaptive self-biased charge pump of the present invention, and fig. 4 is a simulation curve of the discharging characteristic of the current trimmable adaptive self-biased charge pump of the present invention, wherein the abscissa is time and the ordinate is the voltage at the output terminal VC of the charge pump. Simulation results show that the output voltage of the charge pump generates burrs on the capacitor of the filter, the burrs are smaller than 134 muV, and the voltage jitter is smaller than 29 muV.
In the above embodiments of the present application, a current trimmable adaptive self-biased charge pump includes a trimmable adaptive bias circuit and a charge pump core circuit. The adjustable self-adaptive bias circuit generates the bias current of the output voltage of the self-adaptive charge pump by adopting the technology that the grid of an NMOS (N-channel metal oxide semiconductor) tube M3 is connected with the output end VC of the charge pump, so that the charging/discharging current of a core circuit of the charge pump dynamically tracks the output voltage of the charge pump, and the adjustable bias current is generated by respectively controlling the grid of an NMOS tube M8, the grid of an NMOS tube M9 and the grid of the NMOS tube M10 by adopting a signal input end SL1, a signal input end SL2 and a signal input end SL3, so that the charging current and the discharging current of the charge pump have adjustability; in the charge pump core circuit, the error amplifier op1 and the error amplifier op2 are connected by unity gain, and realize a 'bootstrap' technology together with a switch MOS transistor including an NMOS transistor M16, a PMOS transistor M17, a PMOS transistor M18, an NMOS transistor M19, a PMOS transistor M20, an NMOS transistor M21, an NMOS transistor M22 and a PMOS transistor M23 to eliminate a charge sharing effect of the charge pump, and simultaneously the error amplifier op1 and the error amplifier op2 adopt a parallel connection technology to improve current driving capability, so that the current adjustable self-adaptive self-bias charge pump is realized.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in the process, method, article, or apparatus that comprises the element.
The above examples are to be construed as merely illustrative and not limitative of the remainder of the disclosure. After reading the description of the invention, the skilled person can make various changes or modifications to the invention, and these equivalent changes and modifications also fall into the scope of the invention defined by the claims.

Claims (7)

1. A current trimmable adaptive self-biasing charge pump, comprising: the adjustable self-adaptive bias circuit comprises an adjustable self-adaptive bias circuit (1) and a charge pump core circuit (2), wherein a signal output end of the adjustable self-adaptive bias circuit (1) is connected with a signal input end of the charge pump core circuit (2), a signal output end of the charge pump core circuit (2) is connected with a signal input end of the adjustable self-adaptive bias circuit (1), the adjustable self-adaptive bias circuit (1) provides a bias signal for the charge pump core circuit (2) through a grid electrode of a PMOS (P-channel metal oxide semiconductor) tube M12 and a grid electrode of an NMOS (N-channel metal oxide semiconductor) tube M14, and the charge pump core circuit (2) provides charging/discharging current for a filter capacitor of a VC (voltage regulator) rear-stage circuit through an output end;
the adjustable self-adaptive bias circuit generates a bias current of the output voltage of the self-adaptive charge pump by adopting the technology that the grid electrode of an NMOS tube M3 is connected with the output end VC of the charge pump, so that the charging/discharging current of a core circuit of the charge pump dynamically tracks the output voltage of the charge pump, and the signal input end SL1, the signal input end SL2 and the signal input end SL3 are respectively used for controlling the grid electrode of the NMOS tube M8, the grid electrode of the NMOS tube M9 and the grid electrode of the NMOS tube M10 to generate an adjustable bias current, so that the charging current and the discharging current of the charge pump have adjustable performance.
2. A current trimmable adaptive self-biasing charge pump according to claim 1, wherein the trimmable adaptive biasing circuit (1) comprises: a PMOS transistor M1, a PMOS transistor M2, an NMOS transistor M3, an NMOS transistor M4, an NMOS transistor M5, an NMOS transistor M6, an NMOS transistor M7, an NMOS transistor M8, an NMOS transistor M9, an NMOS transistor M10, a PMOS transistor M11, a PMOS transistor M12, a PMOS transistor M13 and an NMOS transistor M14, wherein a source of the PMOS transistor M1 is connected to a source of the PMOS transistor M2, a source of the PMOS transistor M11, a source of the PMOS transistor M12, a source of the PMOS transistor M13 and an external power supply VDD, a gate of the PMOS transistor M1 is connected to a gate of the PMOS transistor M2, a drain of the PMOS transistor M1 and a drain of the NMOS transistor M3, a source of the NMOS transistor M3 is connected to a source of the NMOS transistor M3, a drain of the NMOS transistor M3 and an external ground, a gate of the PMOS transistor M3 is connected to a gate of the NMOS transistor M3, a gate of the PMOS transistor M3, a drain of the NMOS transistor M3, a drain of the transistor M3, a gate of the NMOS transistor M3, a drain of the transistor M3, a gate of the transistor M3, a drain of the NMOS transistor M3, a drain of the transistor M3, a gate of the transistor M3, a drain of the transistor M3, a transistor 3, a drain of the transistor M3, a gate of the transistor M3, a drain of the transistor M3, a gate of the transistor 3, a transistor M3, a gate of the transistor M3, a gate of the transistor 3, a transistor M3, a transistor M3, a transistor 3, a gate of a transistor M3, a transistor M, The grid electrode of the PMOS tube M24, the drain electrode of the PMOS tube M12, the drain electrode of the PMOS tube M11, the drain electrode of the NMOS tube M8, the drain electrode of the NMOS tube M9 and the drain electrode of the NMOS tube M10 are connected, the grid electrode of the NMOS tube M8 is connected with the signal input end SL1, the grid electrode of the NMOS tube M9 is connected with the signal input end SL2, the grid electrode of the NMOS tube M10 is connected with the signal input end SL3, the source electrode of the NMOS tube M8 is connected with the drain electrode of the NMOS tube M5, the source electrode of the NMOS tube M9 is connected with the drain electrode of the NMOS tube M6, the source electrode of the NMOS tube M10 is connected with the drain electrode of the NMOS tube M7, and the drain electrode of the PMOS tube M13 is respectively connected with the grid electrode of the NMOS tube M14, the drain electrode of the NMOS tube M14, the grid electrode of the NMOS tube M15, the bias end Vb1 of the error amplifier 1 and the bias end Vb2 of the error amplifier 2.
3. The adaptive self-bias charge pump according to claim 2, wherein the gate of the NMOS transistor M3 in the adaptive bias circuit (1) is connected to the output terminal VC of the charge pump, so that the drain current I of the NMOS transistor M3 is equal to the drain current I of the NMOS transistor M33Dynamically tracking charge/discharge current of charge pump, i.e. drain current I of NMOS transistor M33Dynamically tracking voltage V of output VC of charge pumpCAnd the drain current I of the NMOS transistor M33Is provided with
Figure FDA0003364672180000021
Wherein, munFor electron mobility, CoxIs the unit area gate oxide capacitance (W/L)3Is the channel width-length ratio, V, of the NMOS transistor M3THnIs the threshold voltage of the NMOS transistor.
4. A current trimmable adaptive self-bias charge pump according to claim 3, wherein the trimmable adaptive bias circuit (1) comprises a PMOS transistor M2 with a channel width-to-length ratio N times that of the PMOS transistor M1, an NMOS transistor M4, an NMOS transistor M5, an NMOS transistor M6 with a channel width-to-length ratio M7, a signal input SL1,The input signals of the signal input end SL2 and the signal input end SL3 are digital signals, the signal input end SL1, the signal input end SL2 and the signal input end SL3 respectively control the voltages of the grid electrode of the NMOS tube M8, the grid electrode of the NMOS tube M9 and the grid electrode of the NMOS tube M10 to realize the adjustability of charge pump charge/discharge current, the PMOS tube M13 is completely the same as the PMOS tube M12, the grid electrode of the PMOS tube M11 is controlled by the digital signal of the signal input end EN, and when the digital signal of the signal input end EN is controlled to be low level '0', the drain current I of the PMOS tube M13 is controlled by the drain current I of the PMOS tube M1313And drain current I of NMOS transistor M1414Is I13＝I14When the digital signal at the signal input end EN is controlled to be high level "1", the drain current I of the PMOS transistor M13 is equal to 013And drain current I of NMOS transistor M1414Is I13＝I14＝(sl1+sl2+sl3)×N×I3Wherein, sl is1Is the digital signal level of the signal input SL1, SL2Is the digital signal level of the signal input SL2, SL3Is the digital signal level, I, of the signal input SL33Is the drain current of the NMOS transistor M3.
5. A current trimmable adaptive self-biasing charge pump according to one of claims 1 to 4, wherein the charge pump core circuit (2) comprises: NMOS transistor M15, NMOS transistor M16, PMOS transistor M17, PMOS transistor M18, NMOS transistor M18, PMOS transistor M18, error amplifier op 18 and error amplifier op 18, wherein the source of PMOS transistor M18 is connected to external power VDD, the drain of PMOS transistor M18 is connected to the source of PMOS transistor M18, the drain of NMOS transistor M18 and the source of PMOS transistor M18, the gate of PMOS transistor M18 is connected to signal input terminal UP, the gate of NMOS transistor M18 is connected to the gate of NMOS transistor M18 and signal input terminal UPN, the drain of PMOS transistor M18 is connected to the source of NMOS transistor M18, the equidirectional input terminal of error amplifier op 4, the drain of error amplifier 18, the source of NMOS transistor M18 and the source of PMOS transistor M18, the drain of PMOS transistor M18 and the source of NMOS transistor M18, the gate of PMOS transistor M18 are connected to the gate of PMOS transistor M18, the signal input terminal DN, and the gate of PMOS transistor M18 are connected to the gate of PMOS transistor M18, the gate of signal input terminal M18, and the gate of PMOS transistor M18, the gate of PMOS transistor M18 are connected to the gate of the signal input terminal M18, and the gate of the signal input terminal M18, and the gate of the PMOS transistor M18, the signal input terminal M18, and the gate of the signal input terminal M18, and the drain of the gate of the signal input terminal M18 are connected to the PMOS transistor M18, respectively, and the drain of the PMOS transistor M18, the drain of the transistor M18, the PMOS transistor M18, and the drain of the signal input terminal M18, and the signal input terminal M18, the gate of the signal input terminal M18 are connected to the signal input terminal M18, the gate of the drain of the transistor M18, and the gate of the signal input terminal M18, and the drain of the signal input terminal M18, and the gate of the drain of the signal input terminal M18, and the gate of the transistor M18, the signal input terminal M18, and the drain of the gate of the drain of the signal input terminal M18, and the transistor M18, and the drain of the signal input terminal M18, and the gate of the transistor M18, and the, The drain electrode of the PMOS tube M18, the source electrode of the NMOS tube M19 and the drain electrode of the NMOS tube M15 are connected, the source electrode of the NMOS tube M15 is connected with an external ground GND, the grid electrode of the PMOS tube M23 is connected with a signal input end UP, the source electrode of the NMOS tube M22 is respectively connected with the drain electrode of the PMOS tube M23, the source electrode of the NMOS tube M18, the drain electrode of the PMOS tube M19, the grid electrode of the NMOS tube M3, the inverting input end of the error amplifier op1, the output end of the error amplifier op1, the inverting input end of the error amplifier op2, the output end of the error amplifier op2 and the output end VC of the charge pump, and the grid electrode of the NMOS tube M19 is connected with the signal input end DN.
6. The current trimmable adaptive self-bias charge pump according to claim 5, wherein in the charge pump core circuit (2), the error amplifier op1 and the error amplifier op2 are connected by unity gain, and together with the switching MOS transistors including the NMOS transistor M16, the PMOS transistor M17, the PMOS transistor M18, the NMOS transistor M19, the PMOS transistor M20, the NMOS transistor M21, the NMOS transistor M22, and the PMOS transistor M23, a "bootstrap" technique is implemented to eliminate the charge sharing effect of the charge pump, and meanwhile, the error amplifier op1 and the error amplifier op2 are connected in parallel to improve the current driving capability, the PMOS transistor M24 and the PMOS transistor M12 have the same channel width-length ratio, and the NMOS transistor M15 and the NMOS transistor M14 have the same channel width-length ratio.
7. The adaptive self-bias charge pump according to claim 6, wherein when the digital signal at the signal input terminal EN is controlled to "0" level, the charging current I flowing through the PMOS transistor M24 is controlled to be "0UPAnd the discharge current I flowing through the NMOS transistor M15DNIs IUP＝IDNWhen the digital signal at the signal input terminal EN is controlled to be at high level "1", the charging current I flowing through the PMOS transistor M24 is equal to 0UPAnd the discharge current I flowing through the NMOS transistor M15DNIs composed of
Figure FDA0003364672180000041
Wherein, sl is1Is the digital signal level of the signal input SL1, SL2For signal transmissionDigital signal level SL into SL23The digital signal level of the signal input end SL3 is N, the ratio of the width-to-length ratio of the channel of the PMOS tube M2 to the width-to-length ratio of the channel of the PMOS tube M1 is munFor electron mobility, CoxIs the unit area gate oxide capacitance (W/L)3Is the channel width-length ratio, V, of the NMOS transistor M3CIs the voltage, V, of the output VC of the charge pumpTHnThe threshold voltage of the NMOS tube is the voltage V of VC at the output end of the charge pumpCThe direct feedback to the grid electrode of an NMOS tube M3 in the adjustable self-adaptive bias circuit (1) realizes the charging current I of a charge pumpUPAnd a discharge current IDNDynamically tracking the voltage of the output end VC of the charge pump, and realizing the charging current I through the signals of the input ends including the signal input end SL1, the signal input end SL2 and the signal input end SL3 in the adjustable self-adaptive bias circuit (1)UPAnd a discharge current IDNTrimming characteristics of (1).
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