CN112786618B

CN112786618B - Semiconductor device with a semiconductor device having a plurality of semiconductor chips

Info

Publication number: CN112786618B
Application number: CN202010817820.5A
Authority: CN
Inventors: 戴名柔; 蔡嘉豪
Original assignee: Innolux Display Corp
Current assignee: Innolux Corp
Priority date: 2019-11-06
Filing date: 2020-08-14
Publication date: 2023-06-13
Anticipated expiration: 2040-08-14
Also published as: CN112786618A

Abstract

Embodiments of the present disclosure provide a semiconductor device including a substrate, a polysilicon semiconductor layer, and a conductive line. The polysilicon semiconductor layer is disposed on the substrate. The wire is arranged on the substrate. The conductive line contacts the polysilicon semiconductor layer through the contact portion. The contact portions of the polysilicon semiconductor layer and the conductive lines have side edges aligned with each other, respectively. The semiconductor device of the present disclosure has good electrical connection, improves contact problems, increases reliability, reduces resistivity, increases driving capability, or improves display quality.

Description

Semiconductor device with a semiconductor device having a plurality of semiconductor chips

Technical Field

Embodiments of the present disclosure relate to an electronic device, and more particularly, to an electronic device including a semiconductor device providing good electrical connection.

Background

Flat display panels have been widely used in electronic devices such as mobile phones, televisions, monitors, tablet computers, displays for vehicles, wearable devices, and desktop computers. With the rapid development of electronic products, the requirements for the display quality on the electronic products are higher and higher, so that the electronic devices for display are continuously improved towards larger and higher resolution display effects.

Disclosure of Invention

The present disclosure provides a semiconductor device having good electrical connection, improving contact problem, improving reliability, reducing resistivity, increasing driving capability, or improving display quality.

According to an embodiment of the present disclosure, a semiconductor device includes a substrate, a polysilicon semiconductor layer, and a conductive line. The polysilicon semiconductor layer is disposed on the substrate. The wire is arranged on the substrate. The conductive line contacts the polysilicon semiconductor layer through the contact portion. The contact portions of the polysilicon semiconductor layer and the conductive lines have side edges aligned with each other, respectively.

In summary, in the semiconductor device according to the embodiments of the disclosure, the side edge of the contact portion of the conductive line is aligned with the side edge of the polysilicon semiconductor layer in the first opening, so that the contact portion and the polysilicon semiconductor layer have good electrical connection. The semiconductor device has excellent technical effects of improving contact problems, improving reliability, or improving display quality. In addition, the semiconductor device can reduce the load of the circuit, increase the driving capability, or improve the display quality.

Drawings

The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The accompanying drawings illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

FIG. 1 is a schematic top view of a semiconductor device according to an embodiment of the disclosure;

FIG. 2 is a schematic cross-sectional view of the semiconductor device of FIG. 1 along section line A-A';

FIG. 3 is a partially enlarged schematic top view of the region R1 of FIG. 1;

FIG. 4 is a schematic cross-sectional view of the section line M-M' of FIG. 3;

FIG. 5 is a schematic top view of a semiconductor device in a non-display area according to an embodiment of the disclosure;

FIG. 6 is an enlarged partial top view of region R2 of FIG. 5;

FIG. 7 is a schematic cross-sectional view of the semiconductor device of FIG. 6 along section line B-B';

fig. 8 is a schematic top view of a semiconductor device according to another embodiment of the present disclosure;

fig. 9 is a schematic cross-sectional view of a semiconductor device according to still another embodiment of the present disclosure.

Detailed Description

The present disclosure may be understood by referring to the following detailed description in conjunction with the accompanying drawings, it being noted that, in order to facilitate the understanding of the reader and for the sake of brevity of the drawings, various drawings in the present disclosure depict only a portion of an electronic device, and specific elements in the drawings are not drawn to actual scale. Furthermore, the number and size of the elements in the drawings are illustrative only and are not intended to limit the scope of the present disclosure.

Certain terms are used throughout the description and following claims to refer to particular components. Those skilled in the art will appreciate that electronic device manufacturers may refer to a same component by different names. It is not intended to distinguish between components that differ in function but not name. In the following description and claims, the terms "include," comprise, "" have, "and the like are open-ended terms, and thus should be interpreted to mean" include, but not limited to. Thus, the terms "comprises," "comprising," "includes," and/or "including," when used in the description of the present disclosure, specify the presence of stated features, regions, steps, operations, and/or components, but do not preclude the presence or addition of one or more other features, regions, steps, operations, and/or components.

Directional terms mentioned herein, such as: "upper", "lower", "front", "rear", "left", "right", etc., are merely directions with reference to the drawings. Thus, the directional terminology is used for purposes of illustration and is not intended to be limiting of the disclosure. In the drawings, the various figures illustrate the general features of methods, structures and/or materials used in certain embodiments. However, these drawings should not be construed as defining or limiting the scope or nature of what is covered by these embodiments. For example, the relative dimensions, thicknesses, and locations of various layers, regions, and/or structures may be reduced or exaggerated for clarity.

It will be understood that when an element or film is referred to as being "connected to" another element or film, it can be directly connected to the other element or film or intervening elements or films may be present. When an element is referred to as being "directly connected to" another element or film, there are no intervening elements or films present therebetween. In addition, when an element is referred to as being "coupled to" another element (or variant thereof), it can be directly connected to the other element or be indirectly connected (e.g., electrically connected) to the other element(s) through one or more elements.

In the present disclosure, the length and width may be measured by an optical microscope, and the thickness may be measured by a cross-sectional image in an electron microscope, but not limited thereto. In addition, any two values or directions used for comparison may have some error.

The terms "about," "equal," or "identical," "substantially," or "substantially" are generally interpreted as being within 20% of a given value or range, or as being within 1O, 5%, 3%, 2%, 1%, or O.5% of a given value or range.

The present disclosure describes a structure (or layer, component, substrate) located on another structure (or layer, element, substrate) and may refer to two structures being adjacent and directly connected, or may refer to two structures being adjacent and not directly connected, and not directly connected refers to two structures having at least one intervening structure (or intervening layer, intervening component, intervening substrate, intervening space) therebetween, wherein the lower surface of one structure is adjacent or directly connected to the upper surface of the intervening structure, the upper surface of the other structure is adjacent or directly connected to the lower surface of the intervening structure, and the intervening structure may be a single-layer or multi-layer solid structure or a non-solid structure. In the present disclosure, when a structure is disposed "on" another structure, it may mean that the structure is "directly" on the other structure, or that the structure is "indirectly" on the other structure, that is, at least one structure is further interposed between the structure and the other structure.

"first," "second," etc. within the specification may be used herein to describe various elements, components, regions, layers and/or sections, but these elements, components, regions, and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, the terms "first element," "component," "region," "layer," or "portion" as discussed below are intended to be separate from "second element," "component," "region," "layer," or "portion" and are not intended to limit the order or to define a particular element, component, region, layer, and/or portion.

The electronic device may achieve a display effect through the semiconductor device according to the embodiments of the present disclosure, where the electronic device may include a display device, an antenna device, a sensing device, a splicing device, or a transparent display device, but is not limited thereto. The electronic device may be a rollable, stretchable, bendable or flexible electronic device. The electronic device may include, for example, a liquid crystal (liquid crystal), a light emitting diode (light emitting diode, LED), a Quantum Dot (QD), a fluorescent (fluorescent), a phosphorescent (phosphorescent), or other suitable materials, and the materials may be arranged in any combination or other suitable display medium, or a combination of the foregoing; the light emitting diode may include, for example, an organic light emitting diode (organic light emitting diode, OLED), a millimeter/sub-millimeter light emitting diode (mini LED), a micro LED, or a Quantum Dot (QD), which may be, for example, but not limited to, a QLED, QDLED). The antenna device may be, for example, a liquid crystal antenna, but is not limited thereto. The splicing device can be, for example, a display splicing device or an antenna splicing device, but is not limited to this. It should be noted that the electronic device may be any of the above arrangements, but is not limited thereto. Furthermore, the shape of the electronic device may be rectangular, circular, polygonal, a shape with curved edges, or other suitable shape. The electronic device may have a driving system, a control system, a light source system, a layer rack system, etc. peripheral systems to support the display device, the antenna device, or the splice device. The disclosure will be described with reference to semiconductor devices, but the disclosure is not limited thereto.

In the present disclosure, various embodiments described below may be used in combination without departing from the spirit and scope of the disclosure, for example, some features of one embodiment may be combined with some features of another embodiment to form another embodiment.

Reference will now be made in detail to the exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

Fig. 1 is a schematic top view of a semiconductor device according to an embodiment of the disclosure. For clarity of the drawing and ease of illustration, fig. 1 omits a number of elements. Fig. 2 is a schematic cross-sectional view of the semiconductor device of fig. 1 along section line A-A'. Fig. 3 is a partially enlarged schematic top view of the region R1 in fig. 1. Referring to fig. 1 and 2, the semiconductor device 1O of the present embodiment is, for example, a display device suitable for displaying images, but the disclosure is not limited thereto. The semiconductor device 1O includes a substrate 100, a polysilicon semiconductor layer 130, and a wire 150. The polysilicon semiconductor layer 130 is disposed on the substrate 100. The conductive line 150 is disposed on the substrate 100. The conductive line 150 has a contact portion 152, and the conductive line 150 contacts the polysilicon semiconductor layer 130 through the contact portion 152 at the first opening H1. In the top view of the embodiment, since the side 131 of the polysilicon semiconductor layer 130 and the side 154 of the contact portion 152 of the conductive line 150 can be aligned with each other, the conductive line 150 and the polysilicon semiconductor layer 130 can have good electrical connection. In addition, the semiconductor device 1O of the present embodiment has excellent technical effects of improving contact problems, improving reliability, reducing resistivity, increasing driving capability, or improving display quality.

Specifically, as shown in fig. 1 and 2, the semiconductor device 1O includes a substrate 100. The substrate 100 may comprise a rigid substrate, a flexible substrate, or a combination thereof. For example, the material of the substrate 100 may include glass, quartz, sapphire (sapphire), ceramic, polycarbonate (PC), polyimide (PI), polyethylene terephthalate (polyethylene terephthalate, PET), other suitable substrate materials, or a combination of the foregoing, but is not limited thereto.

The light shielding layer 11O is provided on the substrate 100. The plurality of light shielding layers 11O may be arranged side by side in a row along the first direction X, and the plurality of light shielding layers 11O may be arranged in a row along the second direction Y, as viewed in a normal direction (for example, a top view direction, which may also be referred to as a third direction Z) of the substrate 100. In the present embodiment, the first direction X, the second direction Y, and the third direction Z are different directions, for example, the first direction X is, for example, an extending direction of the scan line SL (for example, from left to right in fig. 1), the second direction Y is, for example, an extending direction of the conductive line 150, the third direction Z is, for example, a normal direction of the substrate, and the third direction Z is perpendicular to the first direction X and the second direction Y, respectively, but the present embodiment is not limited thereto. The material of the light shielding layer 11O may include molybdenum or other suitable light shielding materials, which is not limited in this embodiment.

In the present embodiment, the light shielding layer 11O is disposed corresponding to an active layer (active device) of a Thin Film Transistor (TFT), for example, to reduce the photo leakage current or improve the flicker problem. The configuration of the thin film transistor TFT will be briefly described below.

As shown in fig. 1 and 2, the semiconductor device 1O further includes a buffer layer 120, a gate insulating layer 140, an interlayer dielectric layer 160, a first insulating layer 180, a second insulating layer 190, a plurality of thin film transistors TFTs, and a plurality of wires 150 disposed on the substrate 100. Specifically, the buffer layer 120 is disposed on the substrate 100 and covers the plurality of light shielding layers 11O. The gate insulating layer 140 is disposed on the buffer layer 120. An interlayer dielectric layer 160 is disposed on the gate insulating layer 140. The first insulating layer 180 is disposed on the interlayer dielectric layer 160. The second insulating layer 190 is disposed on the first insulating layer 180. In this embodiment, the buffer layer 120, the gate insulating layer 140, the interlayer dielectric layer 160, the first insulating layer 180, and the second insulating layer 190 may have a single-layer or multi-layer structure, and may include, for example, an organic material, an inorganic material, or a combination of the foregoing, where the organic material may include, but is not limited to, polyethylene terephthalate (polyethylene terephthalate, PET), polyethylene (PE), polyethersulfone (PEs), polycarbonate (PC), polymethyl methacrylate (PMMA), polyimide (PI), photosensitive polyimide (photo sensitive polyimide, PSPI), or a combination of the foregoing.

In the present embodiment, the thin film transistor is disposed on the substrate, and the thin film transistor may be composed of the polysilicon semiconductor layer 130, the gate electrode GE, the source pattern and the drain pattern 151. The polysilicon semiconductor layer 130 is disposed on the buffer layer 120. Under the above-mentioned configuration, the polysilicon semiconductor layer 130 may have a shape like a U, but is not limited thereto. In this embodiment, the material of the polysilicon semiconductor layer 130 is, for example, low temperature polysilicon (lOw temperature po ysilon, LTPS).

Referring to the schematic cross-sectional view of fig. 2, the gate insulating layer 140 is disposed on the polysilicon semiconductor layer 130. The scan line SL is disposed on the gate insulating layer 140. In the present embodiment, the scan line SL may extend along the first direction X and overlap the polysilicon semiconductor layer 130 in the third direction Z. The portion of the scan line SL overlapping the polysilicon semiconductor layer 130 may be defined as a gate electrode GE.

In the present embodiment, the thin film transistor further includes a dielectric layer IL disposed between the gate electrode GE and the gate insulating layer 140, but the present embodiment is not limited thereto. The dielectric layer IL may have a single-layer or multi-layer structure, and may include, for example, an organic material, an inorganic material (such as silicon nitride, etc.), or a combination of the foregoing, but is not limited thereto. The organic material may include polyethylene terephthalate (polyethylene terephthalate, PET), polyethylene (PE), polyethersulfone (PEs), polycarbonate (PC), polymethyl methacrylate (PMMA), polyimide (PI), photosensitive polyimide (photo sensitive polyimide, PSPI), or a combination thereof, and the inorganic material may include silicon nitride, silicon oxide, silicon oxynitride, or a combination thereof, but is not limited thereto.

The interlayer dielectric layer 160 is disposed on the scan lines SL. The conductive line 150 is disposed on the interlayer dielectric layer 160. As shown in the top view of fig. 1, the conductive line 150 extends along the second direction Y, and as shown in the cross-sectional view of fig. 2, the conductive line 150 partially overlaps the polysilicon semiconductor layer 130 in the third direction Z. The polysilicon semiconductor layer 130 includes, for example, a first segment 130A, a second segment 130B, and a third segment 130C. The second section 130B is connected to the first section 130A and the third section 130C. In the cross-sectional schematic view of the present embodiment, the conductive line 150 partially overlaps the first segment 130A of the polysilicon semiconductor layer 130 in the third direction Z perpendicular to the substrate 100. With continued reference to the cross-sectional view of fig. 2, the drain pattern 151 is disposed on the interlayer dielectric 160, and the drain pattern 151 partially overlaps the third segment 130C of the polysilicon semiconductor layer 130 in the third direction Z perpendicular to the substrate 100. In other words, the conductive line 150 and the drain pattern 151 do not overlap the second section 130B of the polysilicon semiconductor layer 130 in the third direction Z perpendicular to the substrate 100, but the disclosure is not limited thereto.

The conductive line 150 is, for example, a data line, but not limited to this. In the present embodiment, the interlayer dielectric layer 160 has a first opening H1, and the first opening H1 penetrates the gate insulating layer 140 and is located on the first section 130A of the conductive line 150 overlapping the polysilicon semiconductor layer 130. In detail, in the third direction Z, the first opening H1 overlaps the first segment 130A of the portion of the polysilicon semiconductor layer 130. The contact portion 152 of the conductive line 150 passes through the first opening H1 to contact the polysilicon semiconductor layer 130. Thereby, the contact 152 may be applied as a source pattern of the thin film transistor TFT. The interlayer dielectric layer 160 further has a second opening H2 on the third section 130C of the drain pattern 151 overlapping the third section 130C, in detail, in the third direction Z, the second opening H2 overlaps a portion of the third section 130C of the polysilicon semiconductor layer 130.

Referring to fig. 3, fig. 3 is a partial enlarged view of the region R1 in fig. 1. In the partial enlarged view of fig. 3, the drain pattern 151 may pass through the second opening H2 to contact the polysilicon semiconductor layer 130. In the top view schematic of the present embodiment, the drain pattern 151 has a side 153, the side 153 is parallel to the first direction X, the polysilicon semiconductor layer 130 has a side 131', the side 131' is also parallel to the first direction X, and the side 153 of the drain pattern 151 and the side 131' of the polysilicon semiconductor layer 130 are aligned with each other. In this embodiment, the mutual alignment of side 153 and side 131' may be defined as: in the top view of the present embodiment, as shown in fig. 3, the distance D between the side 153 and the side 131 'in the second direction Y is less than or equal to 1 micrometer, or in the cross-sectional view of the present embodiment, as shown in fig. 4, fig. 4 is a cross-sectional view of a section line M-M' of fig. 3, and the distance D between the side 153 and the side 131 in the second direction Y is less than or equal to 1 micrometer.

In the present embodiment, the conductive line 150, the contact portion 152 and the drain pattern 151 are formed of molybdenum (Mo), titanium (Ti) or a combination thereof, but not limited thereto. In some embodiments, the materials of the conductive line 150, the contact 152, and the drain pattern 151 may further include tantalum (Ta), niobium (Nb), hafnium (hafnium, hf), nickel (Ni), chromium (Cr), cobalt (cobalt, co), zirconium (Zr), tungsten (W), other suitable metals, or alloys or combinations of the above materials, but not limited thereto.

In some embodiments, please refer to the schematic cross-sectional diagram of fig. 4, and the drain pattern 151 is illustrated as the drain pattern 151, and the drain pattern 151 may be a stacked structure formed by stacking a plurality of metal layers in the third direction Z. In detail, the drain pattern 151 may include a metal layer 1511, a metal layer 1512, and a metal layer 1513. The metal layer 1512 is disposed between the metal layer 1511 and the metal layer 1513. The metal layer 1511 contacts the polysilicon semiconductor layer 130 in the second opening H2. The material of the metal layer 1511 and the metal layer 1513 is, for example, titanium. The material of the metal layer 1512 is, for example, molybdenum, but the embodiment of the disclosure is not limited thereto.

With continued reference to fig. 1, in order to further reduce the resistivity (resistivity) of the conductive line 150, the semiconductor device 1O further includes an auxiliary conductive line 170, and the auxiliary conductive line 170 extends along the second direction Y substantially corresponding to the conductive line 150. And as shown in the schematic cross-sectional view of fig. 2, the auxiliary conductive line 170 is disposed on the first insulating layer 180 and overlaps the conductive line 150 in the third direction Z, wherein the auxiliary conductive line 170 may be, for example, a data line.

In this embodiment, as shown in the schematic cross-sectional view of fig. 2, the first insulating layer 180 is disposed between the conductive line 150 and the auxiliary conductive line 170, and the first insulating layer 180 has a first opening O1. The auxiliary conductive line 170 is electrically connected to the conductive line 150 through the first opening O1. Thereby, the auxiliary conductive line 170 can be electrically connected to the conductive line 150. In the present embodiment, the first opening O1 has a first minimum width W1 in the second direction Y. The first minimum width W1 may be defined as the width of the first opening O1 closest to the conductive line 150 in the second direction Y, and in detail, the minimum width of the opening or aperture referred to in the present disclosure is measured as follows: along the second direction Y, the smallest distance between the two sides of the opening or aperture. Under the above arrangement, the semiconductor device 1O of the present disclosure can electrically connect the auxiliary conductive line 170 through the conductive line 150 to achieve a dual-layer data line structure, thereby reducing the resistivity of the circuit.

In some embodiments, in the third direction Z (i.e., the normal direction) perpendicular to the substrate 100, the width W5 of the auxiliary wire 170 along the first direction X, the width W6 of the wire 150 along the first direction X, and in detail, the wire width or the auxiliary wire width referred to in the present disclosure is measured as follows: in the first direction X, the minimum distance of the two sides of the wire or auxiliary wire. In an embodiment of the disclosure, the width W5 is equal to or greater than O.5 times W6 and equal to or less than 1.5 times W6. When the width W5 is smaller than O.5 times the width W6, the effect of reducing the resistivity of the wire 150 cannot be effectively provided. When the width W5 is greater than 1.5 times the width W6, the aperture ratio of the pixel is affected. In the above arrangement, the profile of the wire 150 may be located within the profile of the auxiliary wire 170 or the profile of the auxiliary wire 170 may be located within the profile of the wire 150 in the third direction Z, depending on the needs of the user.

It should be noted that, since the auxiliary wire 170 is made of gold (Au), silver (Ag), copper (Cu), aluminum (Al), or other suitable metals, or alloys or combinations thereof, the auxiliary wire 170 has good resistivity. Compared to the conductive wire 150, the resistivity of the auxiliary conductive wire 170 in the present embodiment is smaller than that of the conductive wire 150, specifically, the resistivity of the conductive wire 150 is 53.4nΩ·m and the resistivity of the auxiliary conductive wire 170 is 28.2nΩ·m at the temperature of 20 ℃, but not limited thereto. In addition, the semiconductor device 1O can be electrically connected to the auxiliary conductive line 170 through the conductive line 150 to achieve a dual-layer data line structure, so that the resistivity of the circuit of the semiconductor device 1O can be further reduced. Specifically, when the display panel with small pixel size still has high resolution, the load (Loading) of the data line is significantly higher than that of the data line of the display panel with large pixel size, and thus the display of the picture may be abnormal due to the excessive load of the data line. Therefore, according to the teachings of the present embodiment, the dual-layer data line is disposed in the display panel with small pixel size and the electrical connection design of the dual-layer data line can reduce the impedance or increase the driving capability of the panel to meet the display requirement of small pixel size or high resolution. In this way, the dual-layer data line of the semiconductor device 1O can be designed to reduce the resistivity of the line, so that the load can be reduced, thereby increasing the driving capability of the semiconductor device 1O or improving the display quality.

Referring to fig. 2, a second insulating layer 190 is disposed on the auxiliary conductive line 170. The second insulating layer 190 has a second opening O2. In addition, the semiconductor device 1O further includes a pixel electrode PE disposed on the insulating layer 190, a protective layer 192 disposed on the pixel electrode PE, and a common electrode CE disposed on the protective layer 192. The pixel electrode PE is electrically connected to the drain pattern 151 through the second opening O2. In addition, the protection layer 192 and the common electrode CE may also be partially disposed in the second opening O2. The material of the pixel electrode PE and the common electrode CE includes a transparent conductive material, such as Indium Tin Oxide (ITO), but is not limited thereto.

In the present embodiment, the second opening O2 has a second minimum width W2 in the second direction Y. The second minimum width W2 may be defined as a width of the second opening O2 closest to the drain pattern 151 in the second direction Y. In the present embodiment, the first minimum width W1 is smaller than the second minimum width W2. With the above arrangement, the second opening O2 may provide enough space for the pixel electrode PE to be electrically connected to the drain pattern 151 to ensure good electrical connection. In this way, the semiconductor device 1O has good electrical connection, improved contact problem, increased reliability or improved display quality, but the disclosure is not limited thereto.

In some embodiments, the first opening H1 has a third minimum width W3 in the second direction Y. The third minimum width W3 may be defined as a width of the first opening H1 closest to the polysilicon semiconductor layer 130 in the second direction Y. In the present embodiment, the second minimum width W2 is larger than the third minimum width W3. In this way, the contact portion 152 can be electrically connected to the polysilicon semiconductor layer 130 through the first opening H1, or the aperture ratio of the pixel is not affected, but the disclosure is not limited thereto.

In some embodiments, in a normal direction (e.g., the third direction Z) of the substrate 100, a minimum width W4 of the light shielding layer 11O in the second direction Y is greater than the second minimum width W2. In detail, in the schematic cross-sectional view of the present embodiment, the minimum width W4 along the second direction Y of the two sides of the light shielding layer 11O is greater than the second minimum width W2. Therefore, the light shielding layer 11O can prevent the light from directly irradiating the channel region CH2 under the substrate 100 from generating the light leakage current, or prevent the drain pattern 151, the pixel electrode PE or the common electrode CE from being affected, but the disclosure is not limited thereto.

Fig. 5 is a schematic top view of a semiconductor device in a non-display area according to an embodiment of the disclosure. For clarity of the drawing and ease of illustration, fig. 5 omits several elements. Fig. 6 is an enlarged partial top view of the region R2 of fig. 5. Fig. 7 is a schematic cross-sectional view of the semiconductor device of fig. 6 along section line B-B'. Referring to fig. 5, the semiconductor device 1O of the present embodiment includes a display region 11 and a non-display region 13 surrounding the display region 11 defined on a substrate 100. The display region 11 is provided with the thin film transistor TFT, the wiring 150, and the auxiliary wiring 170 described above. The conductive lines 150 and the auxiliary conductive lines 170 may extend from the display region 11 to the non-display region 13 to electrically connect with the electronic devices 300 in the non-display region 13. The electronic device 300 is exemplified by, but not limited to, an integrated circuit (integrated circuit, IC), an integrated drive and touch IC (TDDI), a chip, a flexible printed circuit (flexible printed circuit, FPC), or a Chip On Film (COF) for providing driving signals.

It should be noted that the semiconductor device 1O of the present embodiment further includes the conductive line 250 and the auxiliary conductive line 270 disposed in the non-display region 13. As shown in fig. 7, the

conductive lines

150 and 250 are disposed on the interlayer dielectric 160. The auxiliary

conductive lines

170 and 270 are disposed on the first insulating layer 180, and the first insulating layer 180 is located between the conductive lines 150 (or the conductive lines 250) and 170 (or the auxiliary conductive lines 270). The first insulating layer 180 further includes a plurality of third openings V, and the auxiliary conductive line 170 is electrically connected to the conductive line 250 through one of the third openings V, or the conductive line 150 is electrically connected to the auxiliary conductive line 270 through one of the third openings V. Accordingly, the wires 150 and the auxiliary wires 170 extending from the display area 11 can be connected to the electronic device 300 through the wires 250 and the auxiliary wires 270 to increase the margin of the circuit layout of the semiconductor device 1O, or the semiconductor device can meet the requirement of narrow frame or no frame, but the disclosure is not limited thereto. In addition, the structure of the double-layered data line of the auxiliary wire 170 (or the auxiliary wire 270) and the wire 150 (or the wire 250) can reduce the resistivity of the line. The semiconductor device 1O has an excellent technical effect of increasing driving capability or improving display quality.

As shown in the region R2 of fig. 5 and 6, the plurality of third openings V are staggered along the first direction X in the normal direction of the substrate 100. For example, the plurality of third openings V includes a plurality of third openings V1 aligned along the first direction X, and a plurality of third openings V2 aligned along the first direction X. In the second direction Y, one row of the plurality of third openings V1 is close to the electronic component 300, and another row of the plurality of third openings V2 is close to the display area 11. That is, the third openings V1 and V are staggered in the second direction Y and staggered along the second direction. It should be noted that fig. 5 and fig. 6 show the third openings V in two rows, but the disclosure is not limited thereto. In other embodiments, the number of rows of the third openings V may not be limited thereto, but may be arranged in three, four or more rows, depending on the needs of the user.

With the above arrangement, when applied to a small-sized high-resolution display device, the semiconductor device 1O can avoid short circuits by contacting the third openings V arranged at high wiring accuracy by the staggered third openings V, and the reliability of the semiconductor device 1O can be improved.

In short, in the top view of the embodiment, in the semiconductor device 1O, the side 154 of the contact portion 152 is aligned with the side 131 of the polysilicon semiconductor layer 130 in the first opening H1, so that the contact portion 152 and the polysilicon semiconductor layer 130 have good electrical connection, the contact problem of the semiconductor device 1O can be improved, and further the reliability can be improved or the excellent technical effect of the display quality can be improved. In addition, the semiconductor device 1O can be electrically connected to the auxiliary conductive line 170 through the conductive line 150 to achieve a dual-layer data line structure, thereby reducing the resistivity of the circuit. Since the resistivity of the auxiliary wire 170 is smaller than that of the wire 150, the resistivity of the double-layered data line of the semiconductor device 1O may be further reduced. In this way, the semiconductor device 1O can reduce the load of the double-layer data line, increase the driving capability, or improve the display quality. In addition, since the first minimum width W1 of the first opening is smaller than the second minimum width W2 of the second opening O2, and the second minimum width W2 is larger than the third minimum width W3 of the connection portion 152. Therefore, the semiconductor device 1O can ensure good electrical connection or does not affect the aperture ratio of the pixel. The width W4 of the light shielding layer 11O is larger than the second minimum width W2. Thus, the light shielding layer 11O can prevent the generation of light leakage current or influence the display effect. In addition, the semiconductor device 100 further includes a conductive line 250 and an auxiliary conductive line 270 that are disposed in the non-display region 13 in a layered manner, and a plurality of third openings V that are disposed in a staggered manner. Thus, the wirings 250 and the auxiliary wirings 270 are layered to improve the margin of the wirings in the non-display region 13. The staggered third openings V can avoid short circuits or improve reliability. The measured widths are all widths in the second direction Y.

Other examples will be listed below as illustration. It should be noted that the following embodiments use the element numbers and part of the content of the foregoing embodiments, where the same numbers are used to denote the same or similar elements, and descriptions of the same technical content are omitted. For the description of the omitted parts, reference is made to the foregoing embodiments, and the following embodiments are not repeated.

Fig. 8 is a schematic top view of a semiconductor device according to another embodiment of the disclosure. For clarity of the drawing and ease of illustration, fig. 8 omits several elements. The semiconductor device 10A of the present embodiment is substantially similar to the semiconductor device 1O of fig. 1, and therefore the same and similar components in the two embodiments are not repeated here. The present embodiment differs from the semiconductor device 1O mainly in that the width of the auxiliary wire 170A in the first direction X is greater than or equal to O.5 times the width of the wire 150 in the first direction X and less than the width of the wire 150 in the first direction X in the normal direction of the substrate 100. Thereby, the semiconductor device 10A has an effect of reducing the resistivity of the conductive line 150 or does not affect the aperture ratio of the pixel. In addition, the semiconductor device 10A can also achieve excellent technical effects similar to those of the above-described embodiments.

Fig. 9 is a schematic cross-sectional view of a semiconductor device according to still another embodiment of the present disclosure. The semiconductor device 1OB of the present embodiment is substantially similar to the semiconductor device 1O of fig. 2, and therefore the same and similar components in the two embodiments are not repeated here. The present embodiment is different from the semiconductor device 1O mainly in that the thickness T2 of the auxiliary wire 170B in the third direction Z is different from the thickness T1 of the wire 150. For example, the thickness T2 may be greater than the thickness T1 and less than or equal to 3 times the thickness T1, but is not limited thereto. Since the resistivity of the auxiliary conductive line 170B is smaller than that of the conductive line 150, in some embodiments, the resistivity of the double-layer data line may be further reduced when the thickness T2 of the auxiliary conductive line 170B in the third direction Z is greater than the thickness T1 of the conductive line 150. When the thickness T2 of the auxiliary wire 170B in the third direction Z is greater than 3 times the thickness T1, the subsequent lamination may be cracked or discontinuous, for example, the second insulating layer 190 may be cracked or discontinuous, which affects the stability of the electrical connection. With the above arrangement, the auxiliary wire 170B can further reduce the resistivity, reduce the load of the double-layer data line, increase the driving capability of the semiconductor device 1OB, or improve the display quality. The thickness referred to in this disclosure is the minimum distance between the bottom to top of the element along the third direction Z. Further, the semiconductor device 1OB can also achieve excellent technical effects similar to those of the above-described embodiments.

In summary, in the semiconductor device according to the embodiments of the disclosure, the side edge of the contact portion is aligned with the side edge of the polysilicon semiconductor layer in the first opening, so that the contact portion and the polysilicon semiconductor layer have good electrical connection. The semiconductor device has excellent technical effects of improving contact problems, improving reliability, or improving display quality. In addition, the semiconductor device can be electrically connected with the auxiliary wire through the wire to achieve the structure of the double-layer data wire, so that the resistivity of the wire is reduced. Since the resistivity of the auxiliary wire is smaller than that of the wire, the resistivity of the double-layered data line of the semiconductor device can be further reduced. Thus, the semiconductor device can reduce the load of the double-layer data line, increase the driving capability or improve the display quality. In addition, the semiconductor device can ensure good electrical connection through the size of the opening, or the opening ratio of the pixel is not affected. In addition, the light shielding layer can avoid the generation of light leakage current or influence the display effect. In addition, the semiconductor device further comprises a third opening which is formed in the non-display area and is provided with wires, auxiliary wires and a plurality of staggered third openings in a layering mode. Thus, the wires and the auxiliary wires arranged in layers can improve the margin of the wiring in the non-display area. The staggered third openings can avoid short circuits or improve reliability. In addition, the semiconductor device disclosed by the invention can also reduce the resistivity by assisting the widths of the wires or the thicknesses of the wires or not influencing the aperture ratio of the pixels.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims

1. A semiconductor device, comprising:

a substrate;

a polysilicon semiconductor layer disposed on the substrate; and

a wire disposed on the substrate, the wire contacting the polysilicon semiconductor layer through a contact portion;

an auxiliary wire electrically connected to the wire;

the first insulating layer is arranged between the wire and the auxiliary wire, wherein the first insulating layer is provided with a first opening, the auxiliary wire is electrically connected with the wire through the first opening, and the first opening is provided with a first minimum width along a second direction;

a second insulating layer disposed on the auxiliary conductive line, wherein the second insulating layer has a second opening with a second minimum width along the second direction, and the first minimum width is smaller than the second minimum width,

wherein the contact portion has a third minimum width in the second direction, and the second minimum width is greater than the third minimum width,

wherein the polysilicon semiconductor layer and the contact portion of the conductive line have side edges aligned with each other, respectively.

2. The semiconductor device according to claim 1, wherein the wire is composed of molybdenum, titanium, or a combination thereof.

3. The semiconductor device according to claim 1, wherein a resistivity of the auxiliary wire is smaller than a resistivity of the wire.

4. The semiconductor device of claim 1, wherein the auxiliary conductive line is comprised of gold, silver, copper, aluminum, or a combination thereof.

5. The semiconductor device according to claim 1, wherein a width of the auxiliary wire in a first direction in a normal direction of the substrate is 0.5 to 1.5 times a width of the wire in the first direction.

6. The semiconductor device according to claim 1, further comprising a plurality of third openings, the auxiliary conductive line being electrically connected to the conductive line through one of the plurality of third openings, wherein the plurality of third openings are staggered in the first direction in a normal direction of the substrate.

7. The semiconductor device according to claim 1, wherein a thickness of the auxiliary wire is different from a thickness of the wire.