CN112769405B - Full-bridge power amplification and pi-shaped low-pass filter circuit topological structure based on SPWM technology - Google Patents
Full-bridge power amplification and pi-shaped low-pass filter circuit topological structure based on SPWM technology Download PDFInfo
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- CN112769405B CN112769405B CN202110020028.1A CN202110020028A CN112769405B CN 112769405 B CN112769405 B CN 112769405B CN 202110020028 A CN202110020028 A CN 202110020028A CN 112769405 B CN112769405 B CN 112769405B
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- 238000003199 nucleic acid amplification method Methods 0.000 title claims abstract description 37
- 238000005516 engineering process Methods 0.000 title claims abstract description 13
- 239000003990 capacitor Substances 0.000 claims abstract description 29
- 238000000034 method Methods 0.000 claims abstract description 13
- 238000010521 absorption reaction Methods 0.000 claims description 9
- 230000001629 suppression Effects 0.000 claims description 9
- 230000006872 improvement Effects 0.000 description 9
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- 230000009471 action Effects 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
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Abstract
The application discloses a full-bridge power amplification and n-type low-pass filter circuit topological structure based on the SPWM technology in the field of sinusoidal signal power amplification circuits, which comprises two half-bridge power amplification circuits which are identical in structure and are cascaded, and also comprises an n-type low-pass filter circuit, wherein the n-type low-pass filter circuit comprises a first inductor, a second inductor and a fifth capacitor, two ends of the fifth capacitor are respectively connected with the second ends of the first inductor and the second inductor, pulse width modulation signals input by the two half-bridge power amplification circuits are opposite in polarity, and output voltage signals are identical in amplitude and opposite in polarity. The application uses two half-bridge power amplifier circuits to form a full-bridge power amplifier circuit together, realizes power amplification of voltage/current, designs a pi-shaped low-pass filter circuit to demodulate a high-power sinusoidal signal, and demodulates the sinusoidal voltage with the output current unchanged and the output increased by one time under the same H-bridge direct-current power supply voltage condition compared with the conventional half-bridge power amplifier and LC filter design method, so that the output power is doubled.
Description
Technical Field
The application relates to the field of sinusoidal signal power amplification circuits, in particular to a full-bridge power amplification and n-type low-pass filter circuit topological structure based on an SPWM technology.
Background
The sinusoidal signal power amplifying circuit is widely applied to national defense electronic fields such as aerospace, aviation, ships, weapons and the like and civil electronic fields such as communication, medical treatment, industrial automation and the like, and the common topological structures of the sinusoidal signal power amplifying circuit comprise a linear power amplifier circuit topology and a pulse width modulation power amplifier circuit topology. The linear power amplifier has the advantages of high precision, small distortion degree, low efficiency and suitability for low-power design; the pulse width modulation power amplifier has the advantages of high efficiency, suitability for medium and high power design, higher technical difficulty, and dependence on the H-bridge direct current supply voltage on the output voltage amplitude, and how to increase the output voltage and the output power as much as possible under the condition of unchanged supply voltage becomes a problem to be studied.
Disclosure of Invention
The application aims to provide a full-bridge power amplification and n-shaped low-pass filter circuit topological structure based on SPWM technology so as to solve the technical problems.
In order to achieve the above purpose, the present application provides the following technical solutions:
the full-bridge power amplification and pi-type low-pass filter circuit topological structure based on the SPWM technology comprises two half-bridge power amplification circuits which are identical in structure and are in cascade connection, and further comprises a pi-type low-pass filter circuit, wherein the pi-type low-pass filter circuit comprises a first inductor, a second inductor and a fifth capacitor, two ends of the fifth capacitor are respectively connected with the second ends of the first inductor and the second inductor, the output end of one half-bridge power amplification circuit is connected with the first end of the first inductor, the output end of the other half-bridge power amplification circuit is connected with the first end of the second inductor, pulse width modulation signals input by the two half-bridge power amplification circuits are opposite in polarity, and output voltage signals are identical in amplitude and opposite in polarity.
As an improvement scheme of the application, the half-bridge power amplifier circuit comprises a first NMOS tube, a second NMOS tube, a first resistor, a second resistor, a fourth resistor and a fifth resistor, wherein the grid electrodes of the first NOMS tube and the second NMOS tube are respectively connected with the second resistor and the fifth resistor through the first resistor and the fourth resistor for inputting pulse width modulation high-voltage signals and pulse width modulation low-voltage signals; the source electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube, the source electrode of the first NMOS tube is connected with the power end, the drain electrode is used as the output end to be connected with the n-shaped low-pass filter circuit, and the drain electrode of the second NMOS tube is grounded.
As an improvement scheme of the application, the grid electrode of the first NMOS tube is connected with a first reverse overvoltage protection circuit.
As an improvement scheme of the application, the first reverse overvoltage protection circuit comprises a first diode connected in parallel with two ends of the first resistor, and the anode of the first diode is connected with the grid electrode of the first NMOS tube.
As an improvement scheme of the application, the grid electrode of the second NMOS tube is connected with a second reverse overvoltage protection circuit.
As an improvement scheme of the application, the second reverse overvoltage protection circuit comprises a second diode connected in parallel with two ends of the fourth resistor, and the anode of the second diode is connected with the grid electrode of the second NMOS tube.
As an improvement scheme of the application, a first peak voltage absorption suppression circuit is connected between the source electrode and the drain electrode of the first NOMOS tube.
As an improvement of the application, the first spike voltage absorption suppression circuit comprises a third resistor and a first capacitor which are connected in series.
As an improvement scheme of the application, a second peak voltage absorption suppression circuit is connected between the source electrode and the drain electrode of the second NOMOS tube.
As an improvement of the application, the second spike voltage absorption suppression circuit comprises a sixth resistor and a second capacitor which are connected in series.
The beneficial effects are that: the application uses two half-bridge power amplifier circuits to form a full-bridge power amplifier circuit together, realizes power amplification of voltage/current, designs a pi-shaped low-pass filter circuit to demodulate a high-power sinusoidal signal, and demodulates the sinusoidal voltage with the output current unchanged and the output increased by one time under the same H-bridge direct-current power supply voltage condition compared with the conventional half-bridge power amplifier and LC filter design method, so that the output power is doubled.
Drawings
Fig. 1 is a schematic circuit diagram of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The full-bridge power amplification and pi-type low-pass filter circuit topological structure based on the SPWM technology comprises two half-bridge power amplification circuits which are identical in structure and are in cascade connection, namely a forward half-bridge power amplification circuit 1 and a reverse half-bridge power amplification circuit 2; the output end of the forward half-bridge power amplification circuit 1 is connected with the first end of the first inductor L1, the output end of the reverse half-bridge power amplification circuit 2 is connected with the first end of the second inductor L2, the polarities of pulse width modulation signals input by the forward half-bridge power amplification circuit 1 and the reverse half-bridge power amplification circuit 2 are opposite, the voltage signals output to the reverse half-bridge low-pass filter circuit 3 are identical in amplitude and opposite in polarity, and differential high-power signal output is generated on the fifth capacitor C5, so that compared with the conventional half-bridge power amplification and LC filter design method, the output power is doubled.
Specifically, the forward half-bridge power amplifier circuit 1 includes a first NMOS V1, a second NMOS V2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first diode D1, a second diode D2, a first capacitor C1, and a second capacitor C2.
The grid electrode of the first NMOS tube V1 receives a pulse width modulation high-voltage end signal input from the outside through a first resistor R1 and is used as a starting voltage of the first NMOS tube V1, a second resistor R2 is connected between the grid electrode and a drain electrode of the first NMOS tube V1, and a third resistor R3 and a first capacitor C1 which are connected in series are connected between the source electrode and the drain electrode. The grid electrode of the second NMOS tube V2 receives a pulse width modulation low-voltage end signal input from the outside through a fourth resistor R4, a fifth resistor R5 is connected between the grid electrode and the drain electrode of the second NMOS tube V2, and a sixth resistor R6 and a second capacitor C2 which are connected in series are connected between the source electrode and the drain electrode.
In order to solve the problems of reverse overvoltage protection and peak voltage absorption suppression of the MOS field effect transistor in the high-frequency switching process, the third resistor R3, the first capacitor C1, the sixth resistor R6 and the second capacitor C2 form an RC network, and the RC network is respectively used for absorbing peak voltages generated between the drain electrode and the source electrode when the first NMOS transistor V1 and the second NMOS transistor V2 are turned off. The second resistor R2 and the fifth resistor R5 respectively form a charge drain channel between the gates and the sources of the first NMOS transistor V1 and the second NMOS transistor V2. The first diode D1 is in inverse parallel connection with the first resistor R1, the second diode D2 is in inverse parallel connection with the fourth resistor R4, and the first diode D2 and the fourth diode D2 are used for realizing rapid release of reverse voltage.
The drain electrode of the first NMOS tube V1 is connected with the externally input direct current high voltage +E, the source electrode of the first NMOS tube V2 is connected with the drain electrode of the second NMOS tube V2 and the first end of the first inductor L1, and the source electrode of the second NMOS tube V2 is connected with the direct current high voltage ground. The forward half-bridge power amplifier circuit 1 outputs a forward pulse width modulation signal to the first inductor L1 of the pi-shaped low-pass filter circuit 3, and the first inductor L1 receives the forward pulse width modulation signal and is connected to the upper end of the fifth capacitor C5.
The reverse half-bridge power amplifier circuit 2 has the same structure as the forward half-bridge power amplifier circuit 1, and specifically includes a first NMOS transistor V3, a second NMOS transistor V4, a first resistor R7, a second resistor R8, a third resistor R9, a fourth resistor R10, a fifth resistor R11, a sixth resistor R12, a first diode D3, a second diode D4, a first capacitor C3, and a second capacitor C4.
The grid electrode of the first NMOS tube V3 receives an externally input pulse width modulation high-voltage end reverse signal through a first resistor R7 and is used as a starting voltage of the first NMOS tube V3, a second resistor R8 is connected between the grid electrode and the drain electrode of the first NMOS tube V3, and a third resistor R9 and a first capacitor C3 which are connected in series are connected between the source electrode and the drain electrode. The grid electrode of the second NMOS tube V4 receives an externally input pulse width modulation low-voltage end reverse signal through a fourth resistor R10, a fifth resistor R11 is connected between the grid electrode and the drain electrode of the second NMOS tube V4, and a sixth resistor R12 and a second capacitor C4 which are connected in series are connected between the source electrode and the drain electrode.
The third resistor R9, the first capacitor C3, the sixth resistor R12, and the second capacitor C4 are respectively configured to absorb peak voltages generated between the drain and the source when the first NMOS V3 and the second NMOS V4 are turned off. The second resistor R8 and the fifth resistor R11 respectively form a charge drain channel between the gates and sources of the first NMOS transistor V3 and the second NMOS transistor V4. The first diode D3 is reversely connected with the first resistor R7 in parallel, and the second diode D4 is reversely connected with the fourth resistor R10 in parallel, so that the rapid release of reverse voltage is realized, and the working reliability of the first NMOS tube V3 and the second NMOS tube V4 is improved.
The drain electrode of the first NMOS V3 and the drain electrode of the first NOMS V1 are both connected to the externally input dc high voltage +e, that is, since the SPWM adopts bipolar pulse width modulation, only one external input power +e is needed in this embodiment. The source electrode of the first NMOS tube V3 is connected with the drain electrode of the second NMOS tube V4 and the first end of the second inductor L2, and the source electrode of the second NMOS tube V4 is connected with the direct-current high-voltage ground. The reverse half-bridge power amplifier circuit 2 outputs a reverse pulse width modulation signal to the second inductor L2 of the pi-shaped low-pass filter circuit 3, and the second inductor L2 receives the reverse pulse width modulation signal and is connected to the lower end of the fifth capacitor C5.
In the implementation of the embodiment, in the forward half-bridge power amplifier circuit 1, an externally input pulse width modulation high-voltage end signal drives the drain electrode and the source electrode of the first NMOS tube V1 to be turned on and off, an externally input pulse width modulation low-voltage end signal drives the drain electrode and the source electrode of the second NMOS tube V2 to be turned on and off, and a sine signal kV with amplified power is output at the upper end of the fifth capacitor C5 after being filtered by the first inductor L1 and the fifth capacitor C5; in the reverse half-bridge power amplifier circuit 2, an externally input pulse width modulation high-voltage end reverse signal drives the drain electrode and the source electrode of the first NMOS tube V3 to be turned on and off, an externally input pulse width modulation low-voltage end reverse signal drives the drain electrode and the source electrode of the second NMOS tube V3 to be turned on and off, and a sine signal-kV with amplified power is output at the lower end of the fifth capacitor C5 after being filtered by the second inductor L2 and the fifth capacitor C5;
the amplitude of the two paths of sine signals at the upper end and the lower end of the fifth capacitor C5 are equal, the polarities are opposite (180 degrees different), and finally, differential high-power sine signal output is generated at the two ends of the fifth capacitor C5: kV- (-kV) =2×kv.
The application uses the forward half-bridge power amplifier circuit and the reverse half-bridge power amplifier circuit to form the full-bridge power amplifier circuit together, realizes the power amplification of voltage/current, designs the pi-shaped low-pass filter circuit to demodulate high-power sinusoidal signals, and demodulates sinusoidal voltage with output current unchanged and output increased by one time under the same H-bridge direct-current power supply voltage condition compared with the conventional half-bridge power amplifier and LC filter design method, thereby doubling the output power.
Although the present disclosure describes embodiments, not every embodiment is described in terms of a single embodiment, and such description is for clarity only, and one skilled in the art will recognize that the embodiments described in the disclosure as a whole may be combined appropriately to form other embodiments that will be apparent to those skilled in the art.
In the description of the present application, it should be noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Therefore, the above description is not intended to limit the scope of the application; all changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.
Claims (9)
1. The full-bridge power amplification and pi-type low-pass filter circuit topological structure based on the SPWM technology comprises two half-bridge power amplification circuits which are identical in structure and are in cascade connection, and is characterized in that each half-bridge power amplification circuit comprises a first NMOS tube, a second NMOS tube, a first resistor, a second resistor, a fourth resistor and a fifth resistor, the grid electrodes of the first NMOS tube and the second NMOS tube are respectively connected with a second resistor and the fifth resistor through the first resistor and the fourth resistor, and pulse width modulation high-voltage signals and pulse width modulation low-voltage signals are respectively input into the grid electrodes of the first NMOS tube and the drain electrodes of the first NMOS tube, and the grid electrodes of the second NMOS tube and the drain electrodes of the second NMOS tube are respectively connected with the second resistor and the fifth resistor; the source electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube, the source electrode of the first NMOS tube is connected with the power end, the drain electrode is used as the output end to be connected with the n-shaped low-pass filter circuit, and the drain electrode of the second NMOS tube is grounded; the output end of one half-bridge power amplifier circuit is connected with the first end of the first inductor, the output end of the other half-bridge power amplifier circuit is connected with the first end of the second inductor, the polarities of pulse width modulation signals input by the two half-bridge power amplifier circuits are opposite, and the output voltage signals are identical in amplitude and opposite in polarity.
2. The full-bridge power amplification and pi-type low-pass filter circuit topology structure based on the SPWM technique of claim 1, wherein the grid electrode of the first NMOS tube is connected with a first reverse overvoltage protection circuit.
3. The full-bridge power amplification and pi-type low-pass filter circuit topology based on SPWM technology according to claim 2, wherein the first reverse overvoltage protection circuit comprises a first diode connected in parallel across the first resistor, and an anode of the first diode is connected to a gate of the first NMOS.
4. A full-bridge power amplification and pi-type low-pass filter circuit topology structure based on SPWM technology according to claim 2 or 3, wherein the gate of the second NMOS transistor is connected with a second reverse overvoltage protection circuit.
5. The full-bridge power amplification and pi-type low-pass filter circuit topology based on SPWM technology of claim 4, wherein said second reverse overvoltage protection circuit comprises a second diode connected in parallel across a fourth resistor, and an anode of the second diode is connected to a gate of a second NMOS.
6. The full-bridge power amplification and pi-type low-pass filter circuit topology based on SPWM technology according to claim 3 or 5, wherein a first spike voltage absorption suppression circuit is connected between the source and drain of the first NMOS transistor.
7. The SPWM technique based full bridge power amplification and pi low pass filter circuit topology of claim 6, wherein said first spike voltage absorption suppression circuit comprises a third resistor and a first capacitor in series.
8. The full-bridge power amplification and pi-type low-pass filter circuit topology based on SPWM technology of claim 6, wherein a second spike voltage absorption suppression circuit is connected between the source and drain of the second NMOS transistor.
9. The full-bridge power amplification and pi-type low-pass filter circuit topology according to claim 8, wherein said second spike voltage absorption suppression circuit comprises a sixth resistor and a second capacitor in series.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110020028.1A CN112769405B (en) | 2021-01-07 | 2021-01-07 | Full-bridge power amplification and pi-shaped low-pass filter circuit topological structure based on SPWM technology |
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| CN112769405B true CN112769405B (en) | 2023-12-12 |
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