CN112768486A

CN112768486A - Magnetic random access memory architecture

Info

Publication number: CN112768486A
Application number: CN201910998241.2A
Authority: CN
Inventors: 夏文斌; 吕玉鑫; 戴瑾
Original assignee: Shanghai Ciyu Information Technologies Co Ltd
Current assignee: Shanghai Ciyu Information Technologies Co Ltd
Priority date: 2019-10-21
Filing date: 2019-10-21
Publication date: 2021-05-07
Anticipated expiration: 2039-10-21
Also published as: CN112768486B

Abstract

The application provides a magnetic random access memory architecture, which comprises a plurality of memory cells, wherein the memory cells are respectively arranged on bit lines and word lines which are parallel to each other and are positioned in the intersection areas of the bit lines and the word lines and gate lines respectively. The plurality of memory cells form a plurality of repeatable unit groups and at least one group of substrate contact units; at least one source connecting unit is also arranged in each repeating unit group along the bit line direction; at least one gate connection unit is arranged in each repeating unit group along the word line direction. The memory cell array structure is beneficial to simplifying the manufacturing process of the memory through the design of the repeated cell group, and the vertical field effect transistor can be compatibly used in a fin-shaped design, meanwhile, the memory cell forming density of the memory is improved, and the memory capacity of the memory is improved.

Description

Magnetic random access memory architecture

Technical Field

The present invention relates to the field of memory technology, and more particularly to magnetic random access memory architectures.

Background

Magnetic Random Access Memory (MRAM) is applied to an embedded memory structure, and basically, a Complementary Metal-Oxide Semiconductor (CMOS) process of a logic chip is still required, and the area of one mos is much larger than that of a Dynamic Random Access Memory (DRAM), while a fin field effect transistor (FINFET) technology has a channel with a three-dimensional, source and drain electrodes are planar layout, and the problem of large tube size is more prominent, so that the large size of the mos has a consequence that capacity increase is limited and cost is increased. By using the prior art, the area can be greatly reduced if the metal oxide semiconductor tube is made into a vertical structure. But are not suitable for use in magnetic random access memories and are not compatible with complementary mos processes.

Disclosure of Invention

In order to solve the above-mentioned problems, an objective of the present invention is to provide a magnetic random access memory architecture based on vertical metal oxide semiconductor (mos) transistors, which is compatible and applicable to a fin field effect transistor (FinFet) design process through the design of the vertical field effect transistor.

The purpose of the application and the technical problem to be solved are realized by adopting the following technical scheme.

According to the present application, a magnetic random access memory architecture is provided, which comprises a plurality of memory cells, wherein the memory cells are respectively arranged on bit lines and word lines which are parallel to each other and are positioned in the intersection regions of the bit lines and the word lines and gate lines respectively, each memory cell comprises a vertical field effect transistor and a magnetic tunnel junction which are combined with a fin structure, wherein the memory cells form a plurality of repeatable cell groups and at least one group of substrate contact cells; at least one source connecting unit is configured in each repeating unit group along the bit line direction; at least one gate connection unit is arranged in each repeating unit group along the word line direction.

The technical problem solved by the application can be further realized by adopting the following technical measures.

In an embodiment of the present application, the connection units are configured according to each group of repeating units, and refer to all the parts for realizing the source and gate connections.

In one embodiment of the present application, each memory cell includes: a semiconductor region of a first doping type; the fin-shaped structure is arranged on the semiconductor region, the fin part of the fin-shaped structure is of a second doping type, the top end of the fin-shaped structure is of a first doping type and is used as a drain, and the bottom end of the fin-shaped structure is contacted with a source formed by the semiconductor region; the grid electrode is arranged on two sides of the fin-shaped structure and isolates the fin-shaped structure from the semiconductor region through an insulating medium; the semiconductor region, the fin structure, and the gate form a fin vertical field effect transistor structure; and a magnetic tunnel junction connected to the drain by a conductive element.

In an embodiment of the present application, a plurality of repeating unit groups are connected to the same word line in a repeating configuration, each repeating unit group includes the plurality of memory cells, one end of the repeating unit group occupies a space of one memory cell for generating a gate connection unit, and a metal layer is disposed at a top end of the gate connection unit instead of a magnetic tunnel junction; the plurality of repeating unit groups are divided by the gate connecting unit, the gates are connected along the fins to form the same word line, and the sources of the semiconductor regions of the plurality of memory cells are connected to form a source line.

In an embodiment of the present application, the gate connection unit is disposed at both ends of the repeating unit group at the end of the same word line, or disposed at any end thereof.

In an embodiment of the present application, the fin structure serves as a conductive channel, and the gate controls the conductive channel to be turned on or off.

In one embodiment of the present application, the word lines are formed such that the gates are connected along the fins.

In an embodiment of the present application, the semiconductor region of each memory cell includes a source, and the sources of the semiconductor regions of the plurality of memory cells are connected to form a source line.

In an embodiment of the present application, the source connection unit and the gate connection unit are connected out through a metal layer of the conductive assembly.

In an embodiment of the present application, the magnetic tunnel junction top contacts the bit line.

In one embodiment of the present application, the conductive element is a via or a contact and the material thereof includes titanium, tantalum, tungsten, titanium nitride, tantalum nitride, and combinations thereof.

In an embodiment of the present application, a substrate contact unit and a plurality of repeating unit groups arranged repeatedly are arranged in parallel to a same bit line direction, and the substrate contact unit is not connected to the same bit line, and the substrate contact unit is arranged at one end of the same bit line, including: a semiconductor region; a fin structure disposed on the semiconductor region, a top end of the fin structure connecting a conductive component, a bottom end of the fin structure contacting the semiconductor region; a gate disposed on two sides of the fin structure, the gate isolating the fin structure from the semiconductor region by an insulating medium; a metal layer connecting conductive elements, wherein the semiconductor region and the fin structure are of a second doping type; each repeating unit group comprises a plurality of storage units, one end of each repeating unit group occupies one storage unit space and is used for generating a source electrode connecting unit, a metal layer replaces a magnetic tunnel junction and is arranged at the top end of the source electrode connecting unit, and a fin of the source electrode connecting unit is replaced by a first doping type; wherein the plurality of repeating unit groups are demarcated by the source connecting unit, and sources of the semiconductor regions of the plurality of repeating unit groups are connected to form a source line.

In an embodiment of the present application, the source connection unit is disposed at both ends of the repeating unit group at the end of the same bit line or disposed at any end thereof.

In an embodiment of the present application, the substrate contact unit is disposed at an end of the same bit line end or disposed at any end thereof.

In an embodiment of the present application, the first doping type is N + + type, and the second doping type is P type.

In an embodiment of the present application, the semiconductor region is formed in the semiconductor substrate by an ion implantation method.

In an embodiment of the present application, a bottom of the fin structure is formed by etching the semiconductor region.

In an embodiment of the present application, in the step of etching the insulating medium and the gate of the portion, the portion to be etched is a corresponding bit line.

In an embodiment of the present application, the step of filling the etching small hole with a conductive material to form the conductive component further includes: and polishing the surface of the conductive component.

In one embodiment of the present application, the gate and the conductive element are formed of conductive materials, including polysilicon or conductive metal materials.

In an embodiment of the present application, the material of each of the aforementioned semiconductors includes a silicon (Si) material or a silicon carbide (SiC) material.

In one embodiment of the present application, the insulating medium and the dielectric may be selectively made of insulating materials including silicon dioxide or benzocyclobutene (BCB) or Polyimide (PI), a composite layer of silicon dioxide and other materials, such as a composite layer of silicon dioxide and silicon nitride, a composite layer … of silicon dioxide and Polyimide (PI), and the like.

The design of the repeated unit group is favorable for simplifying the manufacturing process of the memory, and the vertical field effect transistor can be compatibly used in a fin-shaped design, meanwhile, the memory cell forming density of the memory is improved, and the memory capacity of the memory is favorably improved.

Drawings

FIG. 1 is a schematic diagram of an exemplary MRAM cell structure;

FIG. 2 is a schematic diagram of an exemplary magnetic tunnel junction structure in an MRAM memory cell;

FIG. 3 is a schematic diagram of an exemplary 3 MRAM cell structure;

FIG. 4 is an exemplary MRAM chip architecture diagram;

FIG. 5 is a schematic diagram of an exemplary FINFET technology 3D MRAM cell structure;

FIGS. 6A and 6B are conceptual diagrams of a memory array structure according to an embodiment of the present disclosure;

FIG. 7A is a schematic diagram of a memory cell of an embodiment of the present invention;

FIG. 7B is a cross-sectional view of a memory cell perpendicular to a word line according to an embodiment of the present invention;

FIG. 7C is a side view of an embodiment of a MRAM cell parallel to a word line;

FIG. 7D is a side view of an MRAM cell according to an embodiment of the present application, taken parallel to a word line;

FIG. 7E is a side view of a MRAM memory cell according to an embodiment of the present application, taken parallel to the bit lines;

fig. 8A to 8G are schematic structural changes in the manufacturing process of the memory cell according to the embodiment of the present application.

Description of the symbols

Low resistance state 01; 02, high resistance state; 03, a memory layer; 04 a tunnel barrier layer; 05 reference layer; 06: Bit lines (NMOS gate; Bit lines); 07 Magnetic Tunnel Junction (MTJ); 08: Word lines (Word lines); 09 source line connection point; 10 through holes/connection points; an N + doped region; a P-type substrate (P-type semiconductor substrate); MRAM array 13; a column address decoder 14; 15, column address interface device; address acquisition; 17, reading and writing control; 18, output and input control; source (Source); drain (Drain) 20; 21: Gate (Gate); 22 a fin structure; 23, a fin-shaped structure; 24, a contact; 25: N + + region; 26 dielectric (oxide layer; oxide insulating layer); 27 source line; 28, long groove (trench); 29, small holes; 30, a gate connection unit; 31, a metal layer; 32, a drain electrode; 33, a gate contact; 34 substrate contact unit; 35 source electrode connecting unit; 36 memory cells (bit lines); 37 memory cells (word lines); 38: a silicon wafer; s01, address; s02, other signals; s03 data

Detailed Description

The following description of the embodiments refers to the accompanying drawings for illustrating the specific embodiments in which the invention may be practiced. In the present invention, directional terms such as "up", "down", "front", "back", "left", "right", "inner", "outer", "side", etc. refer to directions of the attached drawings. Accordingly, the directional terminology is used for the purpose of describing and understanding the invention and is in no way limiting.

The drawings and description are to be regarded as illustrative in nature, and not as restrictive. In the drawings, elements having similar structures are denoted by the same reference numerals. In addition, the size and thickness of each component shown in the drawings are arbitrarily illustrated for understanding and ease of description, but the present invention is not limited thereto.

In the drawings, the range of configurations of devices, systems, components, circuits is exaggerated for clarity, understanding, and ease of description. It will be understood that when an element is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present.

In addition, in the description, unless explicitly described to the contrary, the word "comprise" will be understood to mean that the recited components are included, but not to exclude any other components. Further, in the specification, "on.

To further illustrate the technical means and effects of the present invention adopted to achieve the predetermined objects, a magnetic random access memory architecture according to the present invention, and its specific embodiments, structures, features and effects thereof are described in detail below with reference to the accompanying drawings and specific embodiments.

FIG. 1 is a schematic diagram of an exemplary MRAM cell structure. As shown in FIG. 1, a schematic diagram of a magnetic tunnel junction in low resistance state 01 and high resistance state 02 is shown. The Magnetic Random Access Memory (MRAM) includes a memory layer 03, a tunnel barrier layer 04, and a reference layer 05, and the process of reading the Magnetic Random Access Memory (MRAM) is to measure the resistance of a magnetic tunnel junction 07 (MTJ). Using the newer STT-MRAM technology, writing the magnetic tunnel junction 07 is also simpler: a stronger current than reading is used for writing across the magnetic tunnel junction 07. A bottom-up current sets the variable magnetization layer in a direction parallel to the fixed layer, and a top-down circuit sets it in an anti-parallel direction.

FIG. 2 is a schematic diagram of an exemplary magnetic tunnel junction structure in an MRAM memory cell. As shown in fig. 2, the most basic Magnetic Random Access Memory (MRAM) cell consists of a magnetic tunnel junction 07 and a MOS transistor. The gate of the MOS transistor is connected to the word line 08 of the chip to turn on or off the cell, and the magnetic tunnel junction 07 and the MOS transistor are connected in series to the bit line 06 of the chip. Read and write operations are performed on bit line 06.

FIG. 3 is a schematic diagram of an exemplary 3 MRAM cell structure. As shown in fig. 3, the mos transistor is typically an NMOS transistor fabricated by a standard etching process, using a P-type semiconductor substrate 12 as a base, a magnetic tunnel junction 07 connected to a drain 20 through a via/contact 10, the drain 20 and a source 19 both being N + doped regions 11, the other end of the magnetic tunnel junction 07 connected to a bit line 06, the N + doped region 11 located on the P-type semiconductor substrate 12.

FIG. 4 is an exemplary MRAM chip architecture diagram. As shown in fig. 4, a Magnetic Random Access Memory (MRAM) chip is comprised of one or more arrays 13 of MRAM memory cells, each array 13 having a number of external circuits, such as: the row address decoder 15: changing the received address S01 to the selection of word line 06, column address decoder 14: change the received address S01 to the selection of the bit line 06, the read/write control 17: controls read (measure) write (add current) operations on bit line 06, input output control 18: and external exchange data S03.

FIG. 5 is a schematic diagram of an exemplary FINFET technology 3D MRAM cell structure. As shown in fig. 5, FINFET technology (14 nm or less) has been adopted for higher process node mos technology, and mos transistors have been semi-stereoscopically formed to provide satisfactory performance at smaller planar dimensions. The channel of the FINFET metal oxide semiconductor transistor is built on a cubic Fin 22, with a gate 21 surrounding the Fin 22 on three sides.

Fig. 6A and 6B are conceptual diagrams of a memory array structure according to an embodiment of the present application, and the following diagrams are shown in advance for understanding. The memory array structure comprises a plurality of memory cells, wherein the memory cells are respectively arranged on a bit line 06 and a word line 08 which are parallel to each other and are positioned in the intersection regions of the bit line 06 and the word line 08 and a gate line 21 respectively, each memory cell comprises a vertical field effect transistor and a magnetic tunnel junction 07 which are combined with a fin structure, and the memory cells form a plurality of repeatable unit groups and at least one group of substrate contact cells; at least one source connecting unit 35 is arranged for each repeating unit group in the bit line 06 direction; at least one gate connection unit 30 is arranged in each repeating unit group along the word line 08 direction.

In some embodiments, the connection units are configured according to each group of repeating units, and refer to all parts for realizing source and gate connection.

The bottom of the memory array structure is a semiconductor region 25, the semiconductor region 25 is divided into a plurality of regions, the middle is an effective region of the memory array, the effective region is arranged at the position of the array formed by the memory cells, and the effective region is an N-type doped region. The upper and lower sides are P-type doped regions, which are mainly arranged as the positions of the substrate contact unit 34. One memory cell space of the repeating cell group connected to the same word line 08 is occupied to form the gate connecting unit 30. In general, the word line 08, the bit line 06 and the source line 27 are designed in parallel and perpendicular to the gate line 21 (including the dummy gate line). In the fabrication, the memory cell (repeating unit group), the gate connecting unit 30 and the substrate contact unit 34 are formed in the same process.

FIG. 7A is a schematic diagram of a memory cell of an embodiment of the present invention, and FIG. 7B is a cross-sectional view of the memory cell perpendicular to a word line, for understanding. The magnetic random access memory architecture includes a plurality of memory cells, each memory cell including: a semiconductor region 25 of a first doping type; a fin structure 23 disposed on the semiconductor region 25, a fin portion of the fin structure 23 being of the second doping type, a top end of the fin structure 23 being of the first doping type and serving as a drain 32, and a bottom end of the fin structure 23 contacting a source formed by the semiconductor region 25; a gate 21 disposed on two sides of the fin structure 23, wherein the gate 21 isolates the fin structure 23 from the semiconductor region 25 through an insulating medium 26; the semiconductor region 25, the fin structure 23, and the gate 21 form a fin-shaped vertical field effect transistor structure; wherein, the insulating medium is silicon oxide; and a magnetic tunnel junction 07 connected to the drain 32 by the conductive component 24.

In some embodiments, the first doping type is N + + type and the second doping type is P-type.

In some embodiments, the semiconductor region 25 is constructed on a silicon wafer 38.

In some embodiments, the source connection unit 35 and the gate connection unit 30 are connected out through a metal layer of the conductive assembly 24.

In some embodiments, the fin structure 23 serves as a conductive channel with P-type doping inside. The gate 21, the fin-shaped structure 23 and the semiconductor region 25 form a metal oxide semiconductor field effect transistor (MOSFET, abbreviated as MOS transistor) with a vertical structure. The gate 21 controls the conduction channel of the MOS transistor to be turned on or off.

In some embodiments, the semiconductor regions 25 of a plurality of memory cells are connected to form a source line 27. The source line 27 can be formed by selectively using: (1) a plurality of memory cells, wherein the fin structures 23 are parallel and can be connected to the same bit line 06 as being in the same column; the semiconductor regions 25 of the memory cells in the same column are connected to each other to form source lines 27 corresponding to the memory cells in the same column; (2) several columns of semiconductor regions 25 may be connected to form a common source line 27.

FIG. 7C is a side view of a MRAM cell according to an embodiment of the present application, taken parallel to a word line. In some embodiments, one of the fin structures 23 may be elongated to form one row structure.

In some embodiments, the word line 08 is formed by connecting the gate 21 along the fin portion of the fin structure 23. As mentioned above, the gate 21 is extended from the fin structure 23, and the gate 21 of each memory cell can be considered as being connected to each other.

The difference between the present application and a conventional Fin-like Field Effect Transistor (FINFET) is that the gate and Fin structure of the FINFET are perpendicular to each other, the gate 21 disclosed in the present application is grown along the Fin structure 23, the semiconductor region 25 on the silicon chip is connected to form a source line 27, and the bit line 06 is perpendicular to the Fin structure 23 and the word line 08. In the memory cell, the gate 21 is on both sides of the fin structure 23.

As shown in fig. 7A-7C, in some embodiments, the top of the magnetic tunnel junction 07 contacts the bit line 06 and is electrically connected to the top of the fin 23, i.e., the drain, via the conductive element 24.

In some embodiments, the conductive element 24 is a via or contact of a material including titanium, tantalum, tungsten, titanium nitride, tantalum nitride, and combinations thereof.

FIG. 7D is a side view of an embodiment of a MRAM cell parallel to a word line. In one embodiment of the present application, a plurality of repeating unit groups are connected to the same word line 08 in a repeating configuration, each repeating unit group includes the plurality of memory cells (bit lines) 36, one end of the repeating unit group occupies the space of one memory cell 36 for generating the gate connection unit 30, and the metal layer 31 is disposed on the top end of the gate connection unit 30 instead of the magnetic tunnel junction 07; wherein the plurality of repeating unit groups are demarcated by the gate connection unit 30, the gates 21 are connected along the fin to form the same word line 08, and the sources of the semiconductor regions of the memory cells (bit lines) 36 are connected to form a source line 27.

That is, in the case of a fixed memory cell capacity, the density of gate connection points can be changed by adjusting the number of tubes in the memory cell, thereby improving the resistance on the gate line.

In some embodiments, the gate connection unit 30 is disposed at both ends of the repeating unit group at the end of the same word line 08, or the gate connection unit 30 is disposed at any end thereof, which is used to reduce the impedance on the gate line.

FIG. 7E is a side view of an embodiment of a MRAM cell parallel to bit lines.

In an embodiment of the present application, the substrate contact unit 34 and the plurality of repeating unit groups that are repeatedly configured are configured in parallel to a same bit line 06 direction, and the substrate contact unit 34 is not connected to the same bit line 06, and the substrate contact unit 34 is disposed at one end of the same bit line 34, and includes: the semiconductor region 25 is provided on a substrate (silicon wafer 38). A fin structure 23 disposed on the semiconductor region 25, wherein a top end of the fin structure 23 is connected to a conductive element (contact 24), and a bottom end of the fin structure 23 contacts the semiconductor region 25; a gate 21 disposed on two sides of the fin structure 23, wherein the gate 21 isolates the fin structure 23 from the semiconductor region 25 by an insulating medium; and a metal layer 31 connecting conductive elements (contacts 24), wherein the semiconductor region 25 and the fin structure 23 are of a second doping type.

Each repeating unit group comprises a memory unit group region 37 having the plurality of memory units, one end of the repeating unit group occupies one memory unit space for generating a source connection unit 35, a metal layer 31 is disposed on the top end of the source connection unit 35 instead of the magnetic tunnel junction 07, and the fin of the source connection unit 35 is replaced by a first doping type; wherein the plurality of repeating unit groups are demarcated by the source connecting unit 35, and the sources of the semiconductor regions 225 of the plurality of repeating unit groups are connected to form a source line 27. In some embodiments, the number of pipes in the memory cell bank area may be adjusted based on circuit performance metrics.

In an embodiment of the present application, the source connection unit 35 is disposed at both ends of the repeating unit group at the end of the same bit line 06 or the source connection unit 35 is disposed at any end thereof, thereby adjusting the electrical characteristics of the chip.

In some embodiments, the substrate contact unit 34 is disposed at the end of the same bit line end.

In some embodiments, the source connecting unit 35 needs to be doped with a high concentration of N-type strong ion implantation to change the P-doped region into an N-doped region.

In some embodiments, the substrate contact unit 34 and the source connection unit 35 are connected out through the metal layer 31 at the top for interconnection.

Fig. 8A to 8G are schematic structural changes in the manufacturing process of the memory cell according to the embodiment of the present application. Method for manufacturing a magnetic random access memory, comprising at least the following steps:

as shown in fig. 8A, a semiconductor region 25 of the first doping type is formed in the semiconductor substrate 12 of the second doping type. In some embodiments, the semiconductor region 25 is formed in the semiconductor substrate 12 by ion implantation.

As shown in fig. 8B, the semiconductor substrate 12 is etched, and a fin structure 23 is formed on the surface of the semiconductor substrate 12. In some embodiments, the bottom of the fin structure 23 is formed by etching the semiconductor region 25.

As shown in fig. 8C, an insulating dielectric 26 is formed on the surface of the fin structure 23. A gate 21 is formed at the periphery of the fin structure 23, and the fin structure 23 is isolated from the fin structure 23 and the semiconductor region 25 by the insulating medium 26.

As shown in fig. 8D, the semiconductor region 25 and the fin structure 23 are covered by an insulating dielectric 26. The insulating medium is made of insulating materials and dielectric materials such as silicon oxide. Wherein the semiconductor region 25, the fin structure 23 and the gate 21 form a fin-shaped vertical field effect transistor structure.

As shown in fig. 8E to 8G, a portion of the insulating dielectric 26 and the gate 21 are etched, and then the insulating dielectric 26 is filled, so as to form an etched small hole 29 exposing a portion of the fin structure 23.

As shown in fig. 8E, in some embodiments, the step of etching the portions of the insulating medium 26 and the gate 21 is to etch the portions corresponding to the bit lines 06. At the location of the bit line 06 is an etched elongated slot, which is etched to expose a portion of the gate 21 (word line).

As illustrated in fig. 8F, in some embodiments, the gate 21 is further selectively etched within the etching trenches such that a small portion of the fin structure 23 is exposed.

As shown in fig. 8G, in some embodiments, an etched slot is filled with an insulating dielectric 26 (or dielectric) to fill the exposed portions of the fin structure 23 and the gate 21, and an etched hole 29 is formed in the etched slot where a conductive element is to be formed to expose the fin structure 23.

Conductive elements 24 are formed in the etched holes 29. In some embodiments, the step of forming the conductive element 24 in the etched hole 29 further comprises: doping the fin-shaped structure 23 exposed by the etching small hole 29 with a first doping type (e.g., N + +); and filling the etched holes 29 with a conductive material to form the conductive elements 24. However, if necessary, the surface of the conductive element may be polished, for example, by Chemical Mechanical Polishing (CMP) to polish the surface of the conductive element 24.

Thereafter, a magnetic tunnel junction 07 is formed over the conductive element 24, and the magnetic tunnel junction 07 is connected by a bit line 06, as shown in fig. 7A-7C.

Referring to fig. 7A to 7C, a magnetic random access memory architecture of the present application includes a plurality of memory cells, each memory cell disposed at a crossing of a bit line 06 and a word line 08, wherein each memory cell includes: a semiconductor region 25 doped in an N + + type, the semiconductor region 25 of the plurality of memory cells being adjacent to form a source line 27; a P-type doped fin structure 23 disposed above the semiconductor region 25, wherein a top end of the fin structure 23 is a drain and a bottom end of the fin structure 23 contacts a source formed by the semiconductor region 25; a gate 21 disposed partially around the fin structure 23, wherein an opening is disposed at a top end of the gate 21 for the drain to contact the conductive element 24, the gate 21 isolates the fin structure 23, the conductive element 24 and the semiconductor region 25 through an insulating medium such as silicon oxide, a source formed by the gate 21, the fin structure 23 and the semiconductor region 25 constitutes a vertical field effect transistor, the gate 21 controls a conductive channel of the vertical field effect transistor to be opened or closed, and the gates 21 of the plurality of memory cells are adjacent to each other to form the word line 08; and a magnetic tunnel junction 07 disposed above the fin structure 23 to connect the bit line 06 and to connect the conductive element 24.

Fig. 6A and 6B are schematic conceptual views of a memory array structure according to an embodiment of the present invention, please refer to fig. 7A to 8G for understanding. As described above, the semiconductor region 25 is divided into several regions, the middle region is an effective region of the memory array, and the middle region is an N-type doped region disposed at the position of the array formed by the memory cells. The upper and lower sides are P-type doped regions, which are mainly arranged as the positions of the substrate contact unit 34. One memory cell space of the repeating unit group connected to the same word line is occupied to form the gate connecting unit 30. In general, the word lines, bit lines and source lines are designed in parallel and perpendicular to the gate lines (virtual gate lines). In the manufacturing process, the memory unit (the repeating unit group), the grid connecting unit and the substrate contact unit are formed in the same process. Please refer to fig. 6A to fig. 8G and the above description to understand the following process descriptions:

referring to fig. 8A and 8B, N-type and P-type semiconductor regions are formed as the N-type active region and the P-type edge region, and fin structures are formed thereon.

Referring to fig. 8C and 8D, gates are formed on both sides of the fin structure, and the semiconductor region, the fin structure and the gates form a fin-shaped vertical field effect transistor structure.

Referring to fig. 8E-8G, conductive elements and magnetic tunnel junctions are formed, and thus, in conjunction with fig. 8A-8G, the approximate structure of the memory cells (repeating unit groups), gate connection cells, and substrate contact cells has been formed. After that, metal layout of bit lines, word lines and source lines is performed, that is, a memory array structure example shown in fig. 6B is formed.

The gate is formed along the fin-shaped structure, so that the vertical field effect transistor is compatible to be used in a fin-shaped design, the forming density of the memory unit of the memory is improved, and the memory capacity of the memory is improved.

The terms "in one embodiment of the present application" and "in various embodiments" are used repeatedly. The phrases generally do not refer to the same embodiment; it may also refer to the same embodiment. The terms "comprising," "having," and "including" are synonymous, unless the context dictates otherwise.

Although the present application has been described with reference to specific embodiments, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the application, and all changes, substitutions and alterations that fall within the spirit and scope of the application are to be understood as being covered by the following claims.

Claims

1. A magnetic random access memory architecture comprising a plurality of memory cells disposed on bit lines and word lines, respectively, parallel to each other and located at intersection regions of the bit lines and the word lines, respectively, with gate lines, each memory cell comprising a vertical field effect transistor and a magnetic tunnel junction combined in a fin structure, comprising:

the plurality of memory cells form a plurality of repeatable unit groups and at least one group of substrate contact units;

at least one source connecting unit is configured in each repeating unit group along the bit line direction;

at least one gate connection unit is arranged in each repeating unit group along the word line direction.

2. The MRAM architecture of claim 1, wherein a plurality of repeating unit groups are connected to a same word line in a repeating configuration, each repeating unit group comprises the plurality of memory cells, one end of the repeating unit group occupies a space of one memory cell for generating a gate connection unit, and a metal layer is disposed on top of the gate connection unit instead of a magnetic tunnel junction;

the plurality of repeating unit groups are divided by the gate connecting unit, gates are connected along fins to form the same word line, and sources of semiconductor regions of the plurality of memory cells are connected to form a source line.

3. The MRAM architecture of claim 2, wherein the gate connection unit is disposed at both ends or at either end of the repeating unit group at the end of the same word line.

4. The MRAM architecture of claim 1, wherein the semiconductor region of each memory cell comprises a source, the sources of the semiconductor regions of the plurality of memory cells being connected to form a source line.

5. The MRAM architecture of claim 1, wherein the source connection unit and the gate connection unit are routed through a metal layer of a conductive element.

6. The magnetic random access memory architecture of claim 1 wherein a substrate contact cell and a plurality of repeating cell groups in a repeating configuration are arranged parallel to a same bit line direction, and the substrate contact cell is not connected to the same bit line;

the substrate contact unit is arranged at one end of the same bit line and comprises: a semiconductor region; a fin structure disposed on the semiconductor region, a top end of the fin structure being connected to a conductive element, a bottom end of the fin structure contacting the semiconductor region; the grid electrode is arranged on two sides of the fin-shaped structure and isolates the fin-shaped structure from the semiconductor region through an insulating medium; a metal layer connecting the conductive elements, wherein the semiconductor region and the fin structure are of a second doping type; and

each repeating unit group comprises a plurality of storage units, one end of each repeating unit group occupies one storage unit space and is used for generating a source electrode connecting unit, a metal layer replaces a magnetic tunnel junction and is arranged at the top end of the source electrode connecting unit, and a fin of the source electrode connecting unit is replaced by a first doping type; wherein the plurality of repeating unit groups are demarcated by the source connecting unit, and sources of the semiconductor regions of the plurality of repeating unit groups are connected to form a source line.

7. The MRAM architecture of claim 6, wherein the repeating unit group at the end of the same bit line has the source connecting unit disposed at both ends or at either end.

8. The MRAM architecture of claim 6, wherein the substrate contact cell is disposed at an end of the same bit line end or at either end.