CN112768446A - Integrated chip and preparation method thereof - Google Patents
Integrated chip and preparation method thereof Download PDFInfo
- Publication number
- CN112768446A CN112768446A CN201910998781.0A CN201910998781A CN112768446A CN 112768446 A CN112768446 A CN 112768446A CN 201910998781 A CN201910998781 A CN 201910998781A CN 112768446 A CN112768446 A CN 112768446A
- Authority
- CN
- China
- Prior art keywords
- layer
- chip
- monocrystalline silicon
- silicon layer
- dielectric layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002360 preparation method Methods 0.000 title abstract description 9
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 145
- 229910052751 metal Inorganic materials 0.000 claims abstract description 80
- 239000002184 metal Substances 0.000 claims abstract description 80
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 28
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 14
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 14
- 239000010410 layer Substances 0.000 claims description 363
- 230000000149 penetrating effect Effects 0.000 claims description 23
- 239000011241 protective layer Substances 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 17
- 238000002955 isolation Methods 0.000 claims description 14
- 229910002601 GaN Inorganic materials 0.000 claims description 9
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 230000008569 process Effects 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 238000007740 vapor deposition Methods 0.000 claims description 3
- 238000002161 passivation Methods 0.000 claims 2
- 239000004065 semiconductor Substances 0.000 description 6
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 5
- 229910010271 silicon carbide Inorganic materials 0.000 description 5
- 230000010354 integration Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910003465 moissanite Inorganic materials 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
- H01L27/0694—Integrated circuits having a three-dimensional layout comprising components formed on opposite sides of a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/8258—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213, H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention relates to the technical field of chips, and discloses an integrated chip and a preparation method thereof, wherein the integrated chip comprises the following components: the wafer layer comprises a first monocrystalline silicon layer, a second monocrystalline silicon layer and a silicon dioxide medium layer in the middle, and a first chip is formed on the first monocrystalline silicon layer; the first metal part is electrically connected with the corresponding electric connection part of the first chip through a through hole; the second chip device layer forms a second chip, and the second metal part is electrically connected with the corresponding electric connection part of the second chip through a through hole; the second metal part is electrically connected with the corresponding first metal part through the through hole. The integrated chip integrates a plurality of same or different chips on two sides of the wafer, simplifies the connection between the chips and has small volume.
Description
Technical Field
The invention relates to the technical field of chips, in particular to an integrated chip and a preparation method thereof.
Background
With the rapid development of devices, manufacturing processes and device physics of wide bandgap semiconductor materials (i.e. third generation semiconductor materials) represented by SiC and GaN, SiC and GaN-based power electronic devices gradually become important development directions of power semiconductor devices, and have gradually entered into market applications, wherein devices such as GaN Schottky Barrier Diodes (SBD), GaN High Electron Mobility Transistors (HEMT), silicon carbide junction Barrier diodes (JBS), silicon carbide field effect transistors (MOSFET) are mainly used, because the third generation semiconductor power devices have the characteristics of High breakdown electric field, High saturation Electron velocity, High thermal conductivity, High Electron density, High Mobility, low power loss, and the like, and are widely applied in the fields of power electronics, new energy sources, and the like.
At present, a power chip and a device used by an Intelligent Power Module (IPM) are still mainly silicon devices, a few silicon devices are mixed with GaN devices or SiC devices, the packaging design of the module is still based on the structure of the traditional silicon-based device, and the devices are connected in a circuit mode through a routing mode, so that the Intelligent Power Module (IPM) has the advantages of large volume, more packaging leads and incapability of effectively playing the role of a third-generation semiconductor power device.
Disclosure of Invention
The invention provides an integrated chip and a preparation method thereof, wherein the integrated chip integrates a plurality of chips on two sides of a wafer, simplifies the connection among the chips and has small volume.
In order to achieve the purpose, the invention provides the following technical scheme:
an integrated chip, comprising:
the wafer layer comprises a first monocrystalline silicon layer, a second monocrystalline silicon layer and a silicon dioxide dielectric layer arranged between the first monocrystalline silicon layer and the second monocrystalline silicon layer, the first monocrystalline silicon layer comprises a groove area, the groove area divides the first monocrystalline silicon layer into a middle area and an edge area, and a first chip is formed at the position, located in the middle area, of the first monocrystalline silicon layer;
the first dielectric layer is formed on one side, away from the second monocrystalline silicon layer, of the first monocrystalline silicon layer;
a first metal part formed on the first dielectric layer and away from the first monocrystalline silicon layer, wherein the first metal part is electrically connected with the corresponding electric connection part of the first chip through a through hole;
a second chip device layer formed on one side of the second monocrystalline silicon layer, which is far away from the first monocrystalline silicon layer, wherein the second chip device layer forms a second chip;
the second dielectric layer is formed on one side, away from the second monocrystalline silicon layer, of the second chip device layer;
the second metal part is formed on one side, away from the second chip device layer, of the second dielectric layer, and the second metal part is electrically connected with the corresponding electric connection part of the second chip through a through hole; the second metal part is electrically connected with the corresponding first metal part through a via hole penetrating through the second dielectric layer, the second chip device layer, the wafer layer and the first dielectric layer.
The integrated chip comprises a wafer layer, wherein the wafer layer comprises a first monocrystalline silicon layer, a second monocrystalline silicon layer and a silicon dioxide medium layer arranged between the first monocrystalline silicon layer and the second monocrystalline silicon layer, the first monocrystalline silicon layer comprises a groove area, the groove area divides the first monocrystalline silicon layer into a middle area and an edge area, a first chip is formed at the position of the first monocrystalline silicon layer, which is positioned in the middle area, and the groove area is positioned in the peripheral area of the first chip, so that the electrical isolation of the first chip is realized; the integrated chip also comprises a first dielectric layer formed on one side of the first monocrystalline silicon layer, which is far away from the second monocrystalline silicon layer, and a first metal part formed on the first dielectric layer, which is far away from the first monocrystalline silicon layer, wherein the first dielectric layer realizes the electrical isolation of the first chip; the integrated chip further comprises a second chip device layer formed on one side, away from the first monocrystalline silicon layer, of the second monocrystalline silicon layer, a second dielectric layer formed on one side, away from the second monocrystalline silicon layer, of the second chip device layer, and a second metal part formed on one side, away from the second chip device layer, of the second dielectric layer, wherein the second chip device layer forms a second chip, the second metal part is electrically connected with the corresponding electric connection part of the second chip through a through hole, and each second chip is electrically connected with other parts through the through hole and the second metal part; the second metal part is electrically connected with the corresponding first metal part through a through hole penetrating through the second medium layer, the second chip device layer, the wafer layer and the first medium layer, so that the electrical connection between a second chip electrically connected with the second chip and a first chip electrically connected with the first metal part is realized; the integrated chip realizes the integration of different chips on the wafer layer and the electrical connection, and is beneficial to reducing the volume of the chip and simplifying the electrical connection between different chips.
Preferably, the protective layer further comprises a first protective layer formed on one side of the first metal part, which faces away from the first monocrystalline silicon layer, and a second protective layer formed on one side of the second metal part, which faces away from the second monocrystalline silicon layer.
Preferably, a lead terminal is arranged on a surface of one side of the first protection layer, which is far away from the first monocrystalline silicon layer, and the lead terminal is electrically connected with the first metal part through a via hole penetrating through the first protection layer.
Preferably, the semiconductor device further comprises a buffer layer formed between the second chip device layer and the second single crystal silicon layer.
Preferably, the chip further comprises an isolation structure formed in the second chip device layer for isolating adjacent second chips.
Preferably, the first chip is a driving chip, and the second chip is a gallium nitride high electron mobility transistor.
Preferably, the chip further comprises an insulating layer arranged on the side wall of the via hole penetrating through the second dielectric layer, the second chip device layer, the wafer layer and the first dielectric layer.
Preferably, the insulating layer is a silicon dioxide layer.
The invention also provides a preparation method of the integrated chip, which comprises the following steps:
providing a wafer layer, wherein the wafer layer comprises a first monocrystalline silicon layer, a second monocrystalline silicon layer and a silicon dioxide dielectric layer arranged between the first monocrystalline silicon layer and the second monocrystalline silicon layer;
forming a groove region on the first single crystal silicon layer to separate the first single crystal silicon layer into a middle region and an edge region;
forming a first chip in the middle area of the first monocrystalline silicon layer;
forming a first dielectric layer on one side of the first monocrystalline silicon layer, which is far away from the second monocrystalline silicon layer;
forming a second chip device layer on one side of the second monocrystalline silicon layer, which is far away from the first monocrystalline silicon layer, wherein the second chip device layer forms a second chip;
forming a second dielectric layer on one side of the second chip device layer, which is far away from the second monocrystalline silicon layer;
forming a through hole in the second dielectric layer at a position opposite to the electric connection part of the second chip, and forming a through hole in the first dielectric layer at a position opposite to the electric connection part of the first chip;
forming a through hole penetrating through the second dielectric layer, the second chip device layer, the wafer layer and the first dielectric layer at a part opposite to the edge region in the first monocrystalline silicon;
forming a first metal part on one side of the first dielectric layer, which is far away from the first monocrystalline silicon layer, wherein the first metal part is electrically connected with the corresponding electric connection part of the first chip through a through hole; forming a second metal part on one side of the second dielectric layer, which is far away from the second chip device layer, wherein the second metal part is electrically connected with the corresponding electric connection part of the second chip through a through hole; the second metal part is electrically connected with the corresponding first metal part through a via hole penetrating through the second dielectric layer, the second chip device layer, the wafer layer and the first dielectric layer.
Preferably, the method further comprises forming a buffer layer on the side of the second single crystal silicon layer, which faces away from the first single crystal silicon layer, by using a vapor deposition method.
Preferably, an isolation structure is formed between every two adjacent second chips in the second chip device layer by adopting an ion implantation process.
Preferably, the method further comprises forming an insulating layer on the side wall of the via hole penetrating through the second dielectric layer, the second chip device layer, the wafer layer and the first dielectric layer by using a chemical vapor deposition method.
Preferably, the method further comprises forming a first protective layer on a side of the first metal portion facing away from the first single crystal silicon layer, and forming a second protective layer on a side of the second metal portion facing away from the second single crystal silicon layer.
Drawings
Fig. 1 to fig. 8 are schematic diagrams illustrating changes of a film layer in a manufacturing process of an integrated chip according to the present invention.
Icon:
1-a first single crystal silicon layer; 2-a groove region; 3-the middle region; 4-edge area; 5-a second single crystal silicon layer; 6-a silicon dioxide dielectric layer; 7-a first dielectric layer; 8-a first metal portion; 9-a first protective layer; 10-a second chip device layer; 11-a second dielectric layer; 12-a second metal portion; 13-a second protective layer; 14-a buffer layer; 15-an isolation structure; 16-a lead terminal; 17-an insulating layer; 18-via.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, the present invention provides an integrated chip, including:
the wafer layer comprises a first monocrystalline silicon layer 1, a second monocrystalline silicon layer 5 and a silicon dioxide dielectric layer 6 arranged between the first monocrystalline silicon layer 1 and the second monocrystalline silicon layer 5, the first monocrystalline silicon layer 1 comprises a groove area 2, the groove area 2 divides the first monocrystalline silicon layer 1 into a middle area 3 and an edge area 4, and a first chip is formed at the position, located in the middle area 3, of the first monocrystalline silicon layer 1;
a first dielectric layer 7 formed on the side of the first monocrystalline silicon layer 1 away from the second monocrystalline silicon layer 5;
a first metal part 8 formed on the first dielectric layer 7 and departing from the first monocrystalline silicon layer 1, wherein the first metal part 8 is electrically connected with the corresponding electric connection part of the first chip through a through hole 18;
a second chip device layer 10 formed on the second monocrystalline silicon layer 5 at the side away from the first monocrystalline silicon layer 1, the second chip device layer 10 forming a second chip;
a second dielectric layer 11 formed on the second chip device layer 10 at the side away from the second monocrystalline silicon layer 5;
the second metal part 12 is formed on one side, away from the second chip device layer 10, of the second dielectric layer 11, and the second metal part 12 is electrically connected with the corresponding electric connection part of the second chip through a through hole 18; the second metal part 12 is electrically connected with the corresponding first metal part 8 through a via hole 18 penetrating through the second dielectric layer 11, the second chip device layer 10, the wafer layer and the first dielectric layer 7.
The integrated chip comprises a wafer layer, wherein the wafer layer comprises a first monocrystalline silicon layer 1, a second monocrystalline silicon layer 5 and a silicon dioxide medium layer 6 arranged between the first monocrystalline silicon layer 1 and the second monocrystalline silicon layer 5, the first monocrystalline silicon layer 1 comprises a groove region 2, the groove region 2 divides the first monocrystalline silicon layer 1 into a middle region 3 and an edge region 4, a first chip is formed at the position of the first monocrystalline silicon layer 1, which is positioned in the middle region 3, and the groove region 2 is positioned in the peripheral region of the first chip, so that the electrical isolation of the first chip is realized; the integrated chip further comprises a first dielectric layer 7 formed on one side, away from the second monocrystalline silicon layer 5, of the first monocrystalline silicon layer 1, wherein the first dielectric layer 7 realizes electrical isolation of the first chip, and the integrated chip further comprises a first metal part 8 formed on the first dielectric layer 7, away from the first monocrystalline silicon layer 1, the first metal part 8 is electrically connected with an electric connection part of the corresponding first chip through a through hole 18, and the first chip is electrically connected with other parts through the through hole 18 and the first metal part 8; the integrated chip further comprises a second chip device layer 10 formed on one side of the second monocrystalline silicon layer 5, which is far away from the first monocrystalline silicon layer 1, a second dielectric layer 11 formed on one side of the second chip device layer 10, which is far away from the second monocrystalline silicon layer 5, and a second metal part 12 formed on one side of the second dielectric layer 11, which is far away from the second chip device layer 10, wherein the second chip device layer 10 forms a second chip, and the second metal part 12 is electrically connected with an electric connection part of the corresponding second chip through a through hole 18, that is, each second chip is electrically connected with other parts through the through hole 18 and the second metal part 12; the second metal part 12 is electrically connected with the corresponding first metal part 8 through a via hole 18 penetrating through the second dielectric layer 11, the second chip device layer 10, the wafer layer and the first dielectric layer 7, so that the electrical connection between a second chip electrically connected with the second chip and a first chip electrically connected with the first metal part 8 is realized; the integrated chip realizes the integration of different chips on the wafer layer and the electrical connection, and is beneficial to reducing the volume of the chip and simplifying the electrical connection between different chips.
The trench region may be filled with an insulating material, such as silicon dioxide, to achieve electrical isolation of the periphery of the first chip.
Specifically, the first protective layer 9 formed on the side of the first metal portion 8 away from the first single crystal silicon layer 1 and the second protective layer 13 formed on the side of the second metal portion 12 away from the second single crystal silicon layer 5 are also included.
The integrated chip further comprises a first protective layer 9 and a second protective layer 13 which are formed on the surfaces of the two sides of the chip, namely the first metal part 8 deviates from one side of the first monocrystalline silicon layer 1 and the second metal part 12 deviates from one side of the second monocrystalline silicon layer 5, so that the internal structure of the chip is protected, the service life of the integrated chip is prolonged, and the integrated chip is more attractive.
Specifically, a side surface of the first protective layer 9 facing away from the first monocrystalline silicon layer 1 is provided with a lead terminal 16, and the lead terminal 16 is electrically connected to the first metal portion 8 through a via hole 18 penetrating through the first protective layer 9.
A lead terminal 16 is arranged on the surface of the first protective layer 9 on the side away from the first monocrystalline silicon layer 1, one end of the lead terminal 16 is electrically connected with the first metal part 8 through a via hole 18 penetrating through the first protective layer 9, and the other end is used for realizing connection with other devices in the using process.
Specifically, a buffer layer 14 formed between the second chip device layer 10 and the second single crystal silicon layer 5 is further included.
A buffer layer 14 is arranged between the second chip component layer 10 and the second monocrystalline silicon layer 5, which provides a transition between the second monocrystalline silicon layer 5 and the second chip component layer 10.
Specifically, an isolation structure 15 formed in the second chip device layer 10 for isolating adjacent second chips is further included.
When a plurality of second chips are formed on the second chip device layer 10, an isolation structure 15 is disposed between adjacent second chips to electrically isolate the adjacent second chips, so as to prevent the adjacent second chips from interfering with each other and affecting the performance of the second chips.
Specifically, in one embodiment, the first chip is a driving chip, the second chip is a gallium nitride high electron mobility transistor, and the integrated chip realizes integration of the driving chip and the gallium nitride high electron mobility transistor; in another embodiment, the first chip and the second chip may be two parts of a large-area chip after being decomposed, and the integrated chip realizes that the large-area chip is decomposed to be arranged on two sides of the wafer layer, so that the area of the chip is reduced, and the miniaturization packaging of the device is realized.
Specifically, the chip further comprises an insulating layer 17 arranged on the side wall of the via hole 18 penetrating through the second dielectric layer 11, the second chip device layer 10, the wafer layer and the first dielectric layer 7, the insulating layer 17 arranged on the side wall of the via hole 18 penetrating through the second dielectric layer 11, the second chip device layer 10, the wafer layer and the first dielectric layer 7 is beneficial to realizing electrical isolation of the first chip and the second chip, and the performance of the chip is prevented from being influenced, and the insulating layer 17 is a silicon dioxide layer or other material layers with insulating performance.
The invention also provides a preparation method of the integrated chip, which comprises the following steps:
firstly, as shown in fig. 1, a groove is prepared in a wafer layer to form a groove region 2, the wafer layer includes a first monocrystalline silicon layer 1, a second monocrystalline silicon layer 5 and a silicon dioxide dielectric layer 6 arranged between the first monocrystalline silicon layer 1 and the second monocrystalline silicon layer 5, the groove region 2 is formed in the first monocrystalline silicon layer 1 to separate the first monocrystalline silicon layer 1 into a middle region 3 and an edge region 4;
then, a first chip is formed in the middle region 3 of the first single crystal silicon layer 1;
then, as shown in fig. 1, a first dielectric layer 7 is formed on the side of the first single crystal silicon layer 1 facing away from the second single crystal silicon layer 5;
then, as shown in fig. 2, a buffer layer 14 is formed on the side of the second single crystal silicon layer 5 facing away from the first single crystal silicon layer 1;
then, as shown in fig. 2, a second chip device layer 10 is formed on the side of the buffer layer 14 away from the first single crystal silicon layer 1, and the second chip device layer 10 forms a second chip;
then, as shown in fig. 3, a second dielectric layer 11 is formed on the side of the second chip device layer 10 away from the second monocrystalline silicon layer 5;
then, as shown in fig. 4, a via hole 18 is formed in the second dielectric layer 11 at a portion opposite to the electrical connection portion of the second chip, and a via hole 18 is formed in the first dielectric layer 7 at a portion opposite to the electrical connection portion of the first chip;
then, as shown in fig. 5, a via hole 18 penetrating through the second dielectric layer 11, the second chip device layer 10, the wafer layer, and the first dielectric layer 7 is formed at a portion opposite to the edge region 4 in the first single crystal silicon;
then, as shown in fig. 6, an insulating layer 17 is formed on the sidewall of the via hole 18 penetrating through the second dielectric layer 11, the second chip device layer 10, the wafer layer, and the first dielectric layer 7;
then, as shown in fig. 7, a first metal portion 8 is formed on a side of the first dielectric layer 7 away from the first monocrystalline silicon layer 1, and the first metal portion 8 is electrically connected with the corresponding electrical connection portion of the first chip through a via 18; forming a second metal part 12 on one side of the second dielectric layer 11, which is far away from the second chip device layer 10, wherein the second metal part 12 is electrically connected with the corresponding electric connection part of the second chip through a through hole 18; the second metal part 12 is electrically connected with the corresponding first metal part 8 through a through hole 18 penetrating through the second dielectric layer 11, the second chip device layer 10, the wafer layer and the first dielectric layer 7;
then, as shown in fig. 8, a first protective layer 9 is formed on the side of the first metal portion 8 facing away from the first single crystal silicon layer 1, and a second protective layer 13 is formed on the side of the second metal portion 12 facing away from the second single crystal silicon layer 5.
In the preparation method of the integrated chip, the first chip is prepared in the central area of the first monocrystalline silicon of the wafer layer, the second chip is prepared on the side, away from the first monocrystalline silicon layer 1, of the second monocrystalline silicon layer 5 of the wafer layer, the integration of the first chip and the second chip is realized, the effect of reducing the mention of the chips is achieved, the first metal part 8 electrically connected with the electric connection part of the first chip is prepared on the side, away from the wafer layer, of the first chip, the second metal part 12 electrically connected with the electric connection part of the second chip is prepared on the side, away from the wafer layer, of the second chip, and the first metal part 8 is electrically connected with the second metal part 12 through the through hole 18 penetrating through the wafer layer, so that the electric connection between the first chip and the second chip is simplified.
Specifically, in the above preparation method, the buffer layer 14 is formed on the side of the second single crystal silicon layer 5 away from the first single crystal silicon layer 1 by vapor deposition; as shown in fig. 3, an isolation structure 15 is formed between every two adjacent second chips in the second chip device layer 10 by using an ion implantation process, an insulating layer 17 is formed on the sidewall of the via hole 18 penetrating through the second dielectric layer 11, the second chip device layer 10, the wafer layer and the first dielectric layer 7 by using a chemical vapor deposition method, and the insulating layer 17 is formed on the sidewall of the via hole 18 by using a chemical vapor deposition method, so that the forming method is simple and has a good effect.
It will be apparent to those skilled in the art that various changes and modifications may be made in the embodiments of the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (14)
1. An integrated chip, comprising:
the wafer layer comprises a first monocrystalline silicon layer, a second monocrystalline silicon layer and a silicon dioxide dielectric layer arranged between the first monocrystalline silicon layer and the second monocrystalline silicon layer, the first monocrystalline silicon layer comprises a groove area, the groove area divides the first monocrystalline silicon layer into a middle area and an edge area, and a first chip is formed at the position, located in the middle area, of the first monocrystalline silicon layer;
the first dielectric layer is formed on one side, away from the second monocrystalline silicon layer, of the first monocrystalline silicon layer;
a first metal part formed on the first dielectric layer and away from the first monocrystalline silicon layer, wherein the first metal part is electrically connected with the corresponding electric connection part of the first chip through a through hole;
a second chip device layer formed on one side of the second monocrystalline silicon layer, which is far away from the first monocrystalline silicon layer, wherein the second chip device layer forms a second chip;
the second dielectric layer is formed on one side, away from the second monocrystalline silicon layer, of the second chip device layer;
the second metal part is formed on one side, away from the second chip device layer, of the second dielectric layer, and the second metal part is electrically connected with the corresponding electric connection part of the second chip through a through hole; the second metal part is electrically connected with the corresponding first metal part through a via hole penetrating through the second dielectric layer, the second chip device layer, the wafer layer and the first dielectric layer.
2. The integrated chip of claim 1, further comprising a first protective layer formed on a side of the first metal portion facing away from the first single crystal silicon layer and a second protective layer formed on a side of the second metal portion facing away from the second single crystal silicon layer.
3. The integrated chip of claim 2, wherein a surface of the first passivation layer facing away from the first single crystal silicon layer is provided with a lead terminal, and the lead terminal is electrically connected to the first metal portion through a via hole penetrating through the first passivation layer.
4. The integrated chip of claim 1, further comprising a buffer layer formed between the second chip device layer and the second single crystal silicon layer.
5. The integrated chip of claim 1, further comprising an isolation structure formed in the second chip device layer for isolating adjacent second chips.
6. The integrated chip of claim 1, wherein the first chip is a driver chip.
7. The integrated chip of claim 1, wherein the second chip is a gallium nitride high electron mobility transistor.
8. The integrated chip of claim 1, further comprising an insulating layer disposed on a sidewall of a via hole through the second dielectric layer, the second chip device layer, the wafer layer, and the first dielectric layer.
9. The integrated chip of claim 8, wherein the insulating layer is a silicon dioxide layer.
10. A method for manufacturing an integrated chip, comprising:
providing a wafer layer, wherein the wafer layer comprises a first monocrystalline silicon layer, a second monocrystalline silicon layer and a silicon dioxide dielectric layer arranged between the first monocrystalline silicon layer and the second monocrystalline silicon layer;
forming a groove region on the first single crystal silicon layer to separate the first single crystal silicon layer into a middle region and an edge region;
forming a first chip in the middle area of the first monocrystalline silicon layer;
forming a first dielectric layer on one side of the first monocrystalline silicon layer, which is far away from the second monocrystalline silicon layer;
forming a second chip device layer on one side of the second monocrystalline silicon layer, which is far away from the first monocrystalline silicon layer, wherein the second chip device layer forms a second chip;
forming a second dielectric layer on one side of the second chip device layer, which is far away from the second monocrystalline silicon layer;
forming a through hole in the second dielectric layer at a position opposite to the electric connection part of the second chip, and forming a through hole in the first dielectric layer at a position opposite to the electric connection part of the first chip;
forming a through hole penetrating through the second dielectric layer, the second chip device layer, the wafer layer and the first dielectric layer at a part opposite to the edge region in the first monocrystalline silicon;
forming a first metal part on one side of the first dielectric layer, which is far away from the first monocrystalline silicon layer, wherein the first metal part is electrically connected with the corresponding electric connection part of the first chip through a through hole; forming a second metal part on one side of the second dielectric layer, which is far away from the second chip device layer, wherein the second metal part is electrically connected with the corresponding electric connection part of the second chip through a through hole; the second metal part is electrically connected with the corresponding first metal part through a via hole penetrating through the second dielectric layer, the second chip device layer, the wafer layer and the first dielectric layer.
11. The method according to claim 10, further comprising forming a buffer layer on a side of the second single crystal silicon layer facing away from the first single crystal silicon layer by vapor deposition.
12. The method of claim 10, further comprising forming an isolation structure between every two adjacent second chips in the second chip device layer by using an ion implantation process.
13. The method according to claim 10, further comprising forming an insulating layer on sidewalls of the via hole penetrating through the second dielectric layer, the second chip device layer, the wafer layer, and the first dielectric layer by chemical vapor deposition.
14. The method of claim 10, further comprising forming a first protective layer on a side of the first metal portion facing away from the first single crystal silicon layer and forming a second protective layer on a side of the second metal portion facing away from the second single crystal silicon layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910998781.0A CN112768446A (en) | 2019-10-21 | 2019-10-21 | Integrated chip and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910998781.0A CN112768446A (en) | 2019-10-21 | 2019-10-21 | Integrated chip and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112768446A true CN112768446A (en) | 2021-05-07 |
Family
ID=75691545
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910998781.0A Pending CN112768446A (en) | 2019-10-21 | 2019-10-21 | Integrated chip and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112768446A (en) |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030001232A1 (en) * | 2001-06-12 | 2003-01-02 | Hideomi Koinuma | Composite integrated circuit and its fabrication method |
| US20030140317A1 (en) * | 2001-09-28 | 2003-07-24 | Brewer Peter D. | Process for assembling three-dimensional systems on a chip and structure thus obtained |
| KR20060116540A (en) * | 2005-05-10 | 2006-11-15 | 삼성전자주식회사 | Semiconductor element comprising single crystalline silicon layer, semiconductor device and flat pannel display comprising the same, and method of manufacturing the same |
| US20100291749A1 (en) * | 2009-04-14 | 2010-11-18 | NuPGA Corporation | Method for fabrication of a semiconductor device and structure |
| US20140246782A1 (en) * | 2013-03-04 | 2014-09-04 | Jiyoung Kim | Semiconductor devices and methods for fabricating the same |
| CN108364948A (en) * | 2018-02-09 | 2018-08-03 | 上海珏芯光电科技有限公司 | Radio-frequency front-end micro-system module and its manufacturing method |
| CN108461467A (en) * | 2017-02-21 | 2018-08-28 | 株式会社村田制作所 | Semiconductor chip, semiconductor chip installation method and the module for being mounted with semiconductor chip |
| CN109314135A (en) * | 2016-07-01 | 2019-02-05 | 英特尔公司 | Grid pile stack for GaN E mode transistor performance designs |
| JP2019114851A (en) * | 2017-12-21 | 2019-07-11 | 國家中山科學研究院 | Multiband antenna package structure, manufacturing method thereof and communication device |
| CN110211931A (en) * | 2019-06-14 | 2019-09-06 | 上海先方半导体有限公司 | A kind of three-dimension packaging structure and its manufacturing method |
| CN210628308U (en) * | 2019-10-21 | 2020-05-26 | 珠海格力电器股份有限公司 | Integrated chip |
-
2019
- 2019-10-21 CN CN201910998781.0A patent/CN112768446A/en active Pending
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030001232A1 (en) * | 2001-06-12 | 2003-01-02 | Hideomi Koinuma | Composite integrated circuit and its fabrication method |
| US20030140317A1 (en) * | 2001-09-28 | 2003-07-24 | Brewer Peter D. | Process for assembling three-dimensional systems on a chip and structure thus obtained |
| KR20060116540A (en) * | 2005-05-10 | 2006-11-15 | 삼성전자주식회사 | Semiconductor element comprising single crystalline silicon layer, semiconductor device and flat pannel display comprising the same, and method of manufacturing the same |
| US20100291749A1 (en) * | 2009-04-14 | 2010-11-18 | NuPGA Corporation | Method for fabrication of a semiconductor device and structure |
| US20140246782A1 (en) * | 2013-03-04 | 2014-09-04 | Jiyoung Kim | Semiconductor devices and methods for fabricating the same |
| CN109314135A (en) * | 2016-07-01 | 2019-02-05 | 英特尔公司 | Grid pile stack for GaN E mode transistor performance designs |
| CN108461467A (en) * | 2017-02-21 | 2018-08-28 | 株式会社村田制作所 | Semiconductor chip, semiconductor chip installation method and the module for being mounted with semiconductor chip |
| JP2019114851A (en) * | 2017-12-21 | 2019-07-11 | 國家中山科學研究院 | Multiband antenna package structure, manufacturing method thereof and communication device |
| CN108364948A (en) * | 2018-02-09 | 2018-08-03 | 上海珏芯光电科技有限公司 | Radio-frequency front-end micro-system module and its manufacturing method |
| CN110211931A (en) * | 2019-06-14 | 2019-09-06 | 上海先方半导体有限公司 | A kind of three-dimension packaging structure and its manufacturing method |
| CN210628308U (en) * | 2019-10-21 | 2020-05-26 | 珠海格力电器股份有限公司 | Integrated chip |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP6691076B2 (en) | Semiconductor device having passivation layer and method of manufacturing the same | |
| WO2013018760A1 (en) | Semiconductor device, and manufacturing method for same | |
| US9324645B2 (en) | Method and system for co-packaging vertical gallium nitride power devices | |
| US8525253B2 (en) | Double-sided semiconductor structure and method for manufacturing same | |
| US20220406929A1 (en) | Silicon carbide mosfet device and cell structure thereof | |
| US8860126B2 (en) | Semiconductor device with a low ohmic current path | |
| US8871573B2 (en) | Method for forming a semiconductor device | |
| CN110379807B (en) | Microelectronic device and method for manufacturing same | |
| US8124983B2 (en) | Power transistor | |
| CN105283959A (en) | Transistor and method for producing a transistor | |
| JP6650431B2 (en) | Semiconductor device and manufacturing method thereof | |
| US20220384427A1 (en) | Driving chip, semiconductor structure and method for manufacturing the same | |
| US20230197788A1 (en) | Methods, devices, and systems related to forming semiconductor power devices with a handle substrate | |
| US10497784B2 (en) | Semiconductor device | |
| CN112185959B (en) | CMOS inverter monolithically integrated with GaN HEMT power electronic device and preparation method | |
| US10957685B2 (en) | Multi-trench semiconductor device and method of manufacture thereof | |
| CN113421927B (en) | Reverse conducting SiC MOSFET device and manufacturing method thereof | |
| CN210628308U (en) | Integrated chip | |
| US20230395455A1 (en) | Semiconductor device, electronic device, and semiconductor device preparation method | |
| US20050179096A1 (en) | Complimentary nitride transistors vertical and common drain | |
| JP7119422B2 (en) | VERTICAL SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING VERTICAL SEMICONDUCTOR DEVICE | |
| CN112768446A (en) | Integrated chip and preparation method thereof | |
| JP2019071312A (en) | Semiconductor device | |
| CN113690236A (en) | High electron mobility transistor chip and preparation method thereof | |
| CN111952282A (en) | Transistor and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |