CN112751637A - Time delay calculation method, related equipment and system - Google Patents

Abstract

The embodiment of the application discloses a time delay calculation method, related equipment and a system. The method of the embodiment of the application comprises the following steps. The first device receives a first frame sent by the second device through the second interface through the first interface. The first device generates a first timestamp upon detecting the first frame through the first interface. And analyzing the first frame to obtain a second frame, outputting the second frame through a third interface, wherein the second frame has the same type as a frame input from a fourth interface of the second equipment, and the frame encapsulated by the second equipment according to the frame input from the fourth interface has the same type as the first frame. The first device generates a second timestamp when detecting the second frame through the third interface. Timestamp information of the second device is obtained. And determining to obtain a target time delay according to the first time stamp, the second time stamp, the time stamp information and the link time delay, wherein the target time delay represents the time delay of the frame transmitted from the fourth interface to the third interface, and the link time delay is the transmission time delay between the first device and the second device.

Description

Time delay calculation method, related equipment and system

Technical Field

The present application relates to the field of service transmission delay, and in particular, to a delay calculation method, a related device, and a system.

Background

When a network carries customer traffic, it is necessary for the customer to know the delay experienced by the traffic in the network. The delay includes the delay of the traffic processing within the two end devices and the link transmission delay between the two end devices.

In one current implementation, device a first records a time t1 when the message is input to device a. Next, device a transmits the message and t1 to device B. Further, the device B records the time t2 when the message is output from the device B, and obtains the transmission delay between the device a and the device B by calculating t2-t 1. However, since there may be a time difference between the device a and the device B due to different geographical locations, it is necessary to synchronize the time adjustment of the device a and the device B and then calculate the time delay in the above manner. This implementation is complex and costly.

Disclosure of Invention

The embodiment of the application provides a time delay calculation method, related equipment and a system, the transmission time delay of a frame from second equipment to first equipment can be obtained without calculating the time difference between the first equipment and the second equipment, the step of time synchronization of the two equipment is omitted, and the implementation mode is simpler.

In a first aspect, an embodiment of the present application provides a time delay calculation method. The method comprises the following steps.

The first device (B device) receives, via the first interface, a first frame (B frame) transmitted by the second device (a device) via the second interface. Next, the first device generates a first timestamp (t3) that is the time at which the first interface detected the first frame. And then, the first device analyzes the first frame to obtain a second frame (A frame), and outputs the second frame through the third interface, wherein the second frame is the same as the frame type input from the fourth interface of the second device, and the frame encapsulated by the second device according to the frame input from the fourth interface is the same as the first frame type. The first device generates a second timestamp (t4) for a time when the third interface detects a frame of the same type as the second frame, wherein the frame of the same type as the second frame comprises the second frame. Thereafter, the first device acquires the time stamp information of the second device. And determining to obtain a target time delay according to the first time stamp, the second time stamp, the time stamp information and the link time delay, wherein the target time delay represents the time delay of the frame transmitted from the fourth interface to the third interface, and the link time delay is the transmission time delay between the first device and the second device.

In the embodiment, the first device and the second device do not need to perform time synchronization first, and then calculate the service transmission delay of the two devices, so that the implementation mode is simpler.

Optionally, in some possible embodiments, the timestamp information includes a third timestamp (t1) and a fourth timestamp (t2), the third timestamp being a time when the fourth interface detects a frame of the same type as the second frame, and the fourth timestamp being a time when the second interface detects the first frame. In this embodiment, one possible form of timestamp information is listed, improving the utility of the present solution.

Optionally, in some possible embodiments, determining the target latency according to the first timestamp, the second timestamp, the timestamp information, and the link latency includes:

the B device calculates a first time difference of the timestamp t4 minus the timestamp t3 and a second time difference of the timestamp t2 minus the timestamp t1, and sums the first time difference, the second time difference and the link delay to obtain a target delay. In the embodiment, a specific implementation method for calculating the target delay according to t1-t4 and the link delay is provided, so that the realizability of the scheme is improved.

Optionally, in some possible embodiments, the first frame carries a fourth timestamp and a third timestamp; or the first frame carries a fourth timestamp, and the frame of the same type as the second frame carries a third timestamp; alternatively, at least one frame transmitted after the first frame carries the fourth timestamp and the third timestamp. In this embodiment, various implementations in which the device a sends t1 and t2 to the device B are listed, and the extensibility of the scheme is improved.

Optionally, in some possible embodiments, the timestamp information includes a second time difference obtained by subtracting a third timestamp from a fourth timestamp, where the third timestamp is a time when the fourth interface detects a frame of the same type as the second frame, and the fourth timestamp is a time when the second interface detects the first frame. In this embodiment, another possible form of time stamp information is listed, which improves the flexibility of the scheme.

Optionally, in some possible embodiments, determining the target latency according to the first timestamp, the second timestamp, the timestamp information, and the link latency includes:

the device B calculates a first time difference obtained by subtracting the time stamp t3 from the time stamp t4, and sums the first time difference, the second time difference and the link delay to obtain a target delay. In this embodiment, the B device may directly calculate the target time delay according to the received second time difference, which reduces the computational complexity at the B device side.

Optionally, in some possible embodiments, the first frame carries a second time difference; alternatively, at least one frame transmitted after the first frame carries the second time difference. In this embodiment, various implementations are listed in which the device a sends the second time difference to the device B, so that the extensibility of the scheme is improved.

Optionally, in some possible embodiments, the first timestamp is a time when the first interface detects a first bit of a first frame, the fourth timestamp is a time when the second interface detects a first bit of the first frame, the second timestamp is a time when the third interface detects a second bit of a frame of the same type as the second frame, and the third timestamp is a time when the fourth interface detects a second bit of a frame of the same type as the second frame. In this embodiment, considering that the two interface types of the a device are different, the a device may record the first time stamp and the second time stamp based on the first bit and the second bit, respectively. That is, the second interface may recognize the first bit and the fourth interface may recognize the second bit. Therefore, the second interface does not need to be additionally designed to identify the second bit, and the interface is simpler to realize. In addition, the timestamp t1 and the timestamp t4 may be recorded according to the second frame, or the timestamp t1 and the timestamp t4 may be recorded according to other frames of the same type as the second frame, so that the expansibility of the scheme is improved.

Optionally, in some possible embodiments, the first frame includes a first flag for indicating position information of the first bit in the first frame, and the frame of the same type as the second frame includes a second flag for indicating position information of the second bit in the frame of the same type as the second frame. In this embodiment, the position information of the first bit and the second bit may be indicated by the first flag and the second flag, respectively, facilitating the opposite end to record a timestamp from the corresponding bit.

Optionally, in some possible embodiments, the type of the first frame includes an Optical Transport Unit (OTU) frame, a Flexible Ethernet (FlexE) frame, or a Metro Transport Network (MTN) frame, and the type of the second frame includes an OTU frame, a FlexE frame, an MTN frame, or an Ethernet packet. In the embodiment, some possible types of the A frame and the B frame are listed, and the application scene of the scheme is enriched.

Optionally, in some possible embodiments, the acquiring, by the B device, the link delay between the B device and the a device includes:

and the B equipment determines the link delay through a synchronous message of a 1588v2 protocol or a delay detection message of an ITU-T standard. In this embodiment, a specific implementation manner for obtaining the link delay is provided, and the realizability of the scheme is improved.

Optionally, in some possible implementations, the B device sends the timestamp t3, the timestamp t4, the timestamp t1, the timestamp t2, and the link latency to the controller. And calculating a first time difference of the timestamp t4 minus the timestamp t3 and a second time difference of the timestamp t2 minus the timestamp t1 by the controller, and summing the first time difference, the second time difference and the link delay to obtain the target delay. In this embodiment, the target time delay may be calculated by the controller. The expansibility of the scheme is improved.

In a second aspect, an embodiment of the present application provides a first device, including:

the system comprises a processor, a memory and a transceiver, wherein the processor, the memory and the transceiver are interconnected through lines;

the transceiver receives a first frame sent by second equipment through a second interface through a first interface;

the processor calls program code in the memory for performing the steps of:

generating a first timestamp, wherein the first timestamp is the moment when the first interface detects the first frame;

analyzing the first frame to obtain a second frame, outputting the second frame through a third interface, wherein the second frame is the same as a frame type input from a fourth interface of second equipment, and a frame encapsulated by the second equipment according to the frame input from the fourth interface is the same as the first frame type;

generating a second timestamp, wherein the second timestamp is the moment when the third interface detects a frame with the same type as the second frame;

acquiring timestamp information of the second device;

and determining to obtain a target time delay according to the first time stamp, the second time stamp, the time stamp information and the link time delay, wherein the target time delay represents the time delay of the frame transmitted from the fourth interface to the third interface, and the link time delay is the transmission time delay between the first device and the second device.

Optionally, in some possible embodiments, the timestamp information includes a third timestamp and a fourth timestamp, the third timestamp is a time when the fourth interface detects a frame of the same type as the second frame, and the fourth timestamp is a time when the second interface detects the first frame.

Optionally, in some possible embodiments, the processor is specifically configured to:

and calculating a first time difference obtained by subtracting the first time stamp from the second time stamp and a second time difference obtained by subtracting the third time stamp from the fourth time stamp, and summing the first time difference, the second time difference and the link delay to obtain the target delay.

Optionally, in some possible embodiments, the first frame carries a fourth timestamp and a third timestamp; or the first frame carries a fourth timestamp, and the frame of the same type as the second frame carries a third timestamp; alternatively, at least one frame transmitted after the first frame carries the fourth timestamp and the third timestamp.

Optionally, in some possible embodiments, the timestamp information includes a second time difference obtained by subtracting a third timestamp from a fourth timestamp, where the third timestamp is a time when the fourth interface detects a frame of the same type as the second frame, and the fourth timestamp is a time when the second interface detects the first frame.

Optionally, in some possible embodiments, the processor is specifically configured to:

and calculating a first time difference obtained by subtracting the first time stamp from the second time stamp, and summing the first time difference, the second time difference and the link delay to obtain the target delay.

Optionally, in some possible embodiments, the first frame carries a second time difference; alternatively, at least one frame transmitted after the first frame carries the second time difference.

Optionally, in some possible embodiments, the first timestamp is a time when the first interface detects a first bit of a first frame, the fourth timestamp is a time when the second interface detects a first bit of the first frame, the second timestamp is a time when the third interface detects a second bit of a frame of the same type as the second frame, and the third timestamp is a time when the fourth interface detects a second bit of a frame of the same type as the second frame.

Optionally, in some possible embodiments, the first frame includes a first flag for indicating position information of the first bit in the first frame, and the frame of the same type as the second frame includes a second flag for indicating position information of the second bit in the frame of the same type as the second frame.

Optionally, in some possible embodiments, the type of the first frame includes an Optical Transport Unit (OTU) frame, a Flexible Ethernet (FlexE) frame, or a Metro Transport Network (MTN) frame, and the type of the second frame includes an OTU frame, a FlexE frame, an MTN frame, or an Ethernet packet.

Optionally, in some possible embodiments, the processor is specifically configured to:

and determining the link delay through a synchronous message of a 1588v2 protocol or a delay detection message of an ITU-T standard.

Optionally, in some possible embodiments, the transceiver is further configured to:

and sending the first time stamp, the second time stamp, the time stamp information and the link delay to the controller.

In a third aspect, an embodiment of the present application provides a transmission system, including: the device comprises a device A, a device B and a controller;

the A device records a time stamp t1 and a time stamp t2, the time stamp t1 is the time when one interface of the A device detects an input A frame, the time stamp t2 is the time when the other interface of the A device detects a B frame, and the B frame is obtained by the A device according to A frame encapsulation. The a device transmits a B frame to the B device. The B device records a timestamp t3 and a timestamp t4, the timestamp t3 is the time when one interface of the B device detects the B frame, the timestamp t4 is the time when the other interface of the B device detects the A frame, and the B frame is analyzed by the B device. The A device sends its recorded timestamp t1 and timestamp t2 to the controller. The B device sends its recorded timestamp t3 and timestamp t4 to the controller. And, the a device or the B device transmits the link delay also to the controller. Further, the controller calculates a first time difference obtained by subtracting the time stamp t1 from the time stamp t2 and a second time difference obtained by subtracting the time stamp t3 from the time stamp t4, and sums the first time difference, the second time difference and the link delay to obtain a target delay.

In a fourth aspect, an embodiment of the present application provides a computer storage medium, which includes instructions, when executed on a computer, cause the computer to perform the latency calculation method in any implementation manner of the first aspect.

In a fifth aspect, the present application provides a computer program product containing instructions, which when run on a computer, causes the computer to execute the latency calculation method in any one of the embodiments of the first aspect.

According to the technical scheme, the embodiment of the application has the following advantages: and calculating a first time difference obtained by subtracting the first time stamp from the second time stamp, subtracting a second time difference obtained by subtracting the third time stamp from the fourth time stamp, and summing the first time difference, the second time difference and the link delay to obtain the transmission delay of the frame from the second equipment to the first equipment. By the method, the first device and the second device do not need to perform time synchronization firstly, and then service transmission time delay of the two devices is calculated, so that the realization method is simpler.

Drawings

Fig. 1 is a schematic diagram of a first network structure applied in the present application;

FIG. 2 is a schematic diagram of an embodiment of a delay calculation method according to the present application;

FIG. 3 is a schematic diagram of marking X bits in a frame;

fig. 4 is a schematic diagram of a second network structure applied in the present application;

fig. 5 is a schematic diagram of a third network structure applied in the present application;

fig. 6 is a schematic structural diagram of a possible B device according to the present application.

Detailed Description

The embodiment of the application provides a time delay calculation method, related equipment and a system. The first device and the second device do not need to perform time synchronization first, and then service transmission time delay of the two devices is calculated, so that the implementation mode is simpler.

It should be noted that the terms "first," "second," "third," and "fourth," etc. in the description and claims of this application and the above-mentioned drawings are used for distinguishing between similar elements and not necessarily for limiting a particular order or sequence. It is to be understood that the terms so described are interchangeable under appropriate circumstances such that the embodiments described herein are capable of operation in other sequences than described of illustrated herein. Furthermore, the terms "comprising" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements explicitly listed, but may include other steps or elements not explicitly listed or inherent to such process, method, article, or apparatus.

Fig. 1 is a schematic diagram of a first network structure applied in the present application. Traffic (a-frames in fig. 1) is transmitted through an a-device 101 to a B-device 102. The interface 101a and the interface 101b of the a device 101 are two interfaces different in type or interface rate. The interface 102a and the interface 102B of the B device 102 are also two interfaces that differ in type or interface rate. The type or interface rate of the interface 101a is the same as that of the interface 102b, and the type or interface rate of the interface 101b is the same as that of the interface 102 a. Specifically, the interface 101a of the a device 101 receives an input a frame. After that, the a device 101 processes the a frame to obtain a B frame meeting the transmission requirement of the interface 101B, and the interface 101B outputs the B frame. Next, the interface 102a of the B device 102 receives the B frame. Further, the B device processes the B frame to obtain an a frame meeting the transmission requirement of the interface 102B, and the interface 102B outputs the a frame.

In order to calculate the transmission delay experienced by the a-frame interface 101a to the interface 102b, the present application provides a delay calculation method.

Fig. 2 is a schematic diagram of an embodiment of the delay calculation method of the present application. In this embodiment, the time delay calculation method includes the following steps:

201. and the B device receives the B frame sent by the A device.

In this embodiment, the B device 102 receives the B frame transmitted from the interface 101B by the a device 101 through the interface 102 a. Specifically, the a device 101 processes an a frame input from the interface 101a to obtain a B frame. For example, the a frame may be an ethernet packet, and the a device 101 maps the a frame to a B frame so that the B frame conforms to the transmission requirements of the interface 101B. Or the a frame and the B frame are frames of the same type but different rates (for example, OTN frames), the a device 101 may obtain the B frame by multiplexing the a frame, so that the B frame meets the transmission requirement of the interface 101B. It should be understood that B frames may also be derived from a frames by mapping if of the same type. The present application is not limited thereto.

The selectable types of the a frame and the B frame include an Optical Transport Unit (OTU) frame, a Flexible Ethernet (FlexE) frame, a Metro Transport Network (MTN) frame, or the like. For example, the a frame is an OTU frame, and the B frame is a FlexE frame. Or, the a frame is an ethernet packet, and the B frame is an OTU frame or a FlexE frame. Or, the a frame and the B frame are both OTU frames, but the rates are different.

202. The B device generates a timestamp t 3.

In this embodiment, when the interface 102a detects a B frame, the B device 102 generates a timestamp t 3.

203. And B equipment analyzes the B frame to obtain an A frame.

In this embodiment, the B device 102 parses the B frame to obtain an a frame that meets the transmission requirement of the interface 102B, and outputs the a frame through the interface 102B. Specifically, if the a frame is an ethernet packet, the B device 102 may demap the B frame to obtain the a frame. If the type of the B frame is the same as that of the a frame but the rate is different, the B device may demultiplex the B frame to obtain the a frame.

Note that the a frame is the same type (including rate) as the a1 frame input from the interface 101a of the a device 101. For example, the a frame and the a1 frame are both messages. Alternatively, the a frame and the a1 frame are the same OTU frame, and the rate of the a frame and the a1 frame is the same.

204. The B device generates a timestamp t 4.

In this embodiment, when the interface 102B detects an a frame or an a1 frame of the same type as the a frame, the B device 102 generates a timestamp t 4.

205. The B device acquires the timestamp information of the a device.

In this embodiment, the timestamp information of the a device 101 may include a timestamp t1 and a timestamp t 2. Specifically, when the interface 101a detects an input a frame or an a1 frame of the same type as the a frame, the a device 101 generates a time stamp t 1. It is understood that if the a device 101 records the timestamp t1 according to the a frame, then the B device 102 also records the timestamp t4 according to the a frame. If the A device 101 records the timestamp t1 from the A1 frame, then the B device 102 also records the timestamp t4 from the A1 frame. When the interface 101B detects a B frame, the a device 101 generates a timestamp t 2. For example, the a device 101 may add a timestamp t1 to the a frame and a timestamp t2 to the B frame. Then, if the interface 102a detects a B frame, the B device 102 may obtain the timestamp t2 from the B frame. If the interface 102B detects an a-frame, the B-device 102 may obtain the timestamp t1 from the a-frame.

Optionally, the timestamp information of the a device 101 may also include a first time difference of the timestamp t2 minus the timestamp t 1. The a device 101 may add a first timestamp to the B frame. Then, if the interface 102a detects a B frame, the B device 102 may obtain the first time difference from the B frame.

Alternatively, the a device 101 may already be transmitting B frames in synchronization when the interface 101B detects B frames and records the time stamp t 2. Then the a device 101 may add the timestamp t2 or the first time difference to the C frame and send the C frame to the B device 102 when the interface 101B detects the C frame transmitted after the B frame. Then, if the interface 102a detects a C frame, the B device 102 may obtain the timestamp t2 or the first time difference from the C frame. It is understood that the C frame may be any one or more frames transmitted after the B frame, and is not limited herein.

In addition, for the time stamp t1, although the a device 101 has enough time to add the time stamp t1 to the a frame. In practical applications, the a device may further add the timestamp t1 to the D frame when the interface 101a detects the D frame transmitted after the a frame, which is not limited herein.

Optionally, the timestamp t1 may also be carried by a B frame or a C frame.

Note that, since the types (including the rates) of the a frame and the B frame are different, the a device 101 may not be able to record the time stamp t1 and the time stamp t2 based on the same bit. For example, the a frame is an ethernet packet, and the B frame is an OTU frame. The a device 101 records the timestamp t1 based on the bit in the ethernet packet, which will be mapped to the payload area of the OTU frame, and the interface 101b does not usually recognize the payload area of the OTU frame, then the a device 101 can no longer record the timestamp t2 based on the bit in the ethernet packet. Or, the a frame is an OTU1 frame, and the B frame is an OTU2 frame with a rate different from that of the OTU1 frame. The a device 101 records the timestamp t1 based on the frame header of the OTU1 frame, and the frame header of the OTU1 frame is different from the frame header of the OTU2 frame, so the a device 101 cannot record the timestamp t2 based on the frame header of the OTU1 frame. In summary, the a device 101 needs to record the time stamp t1 and the time stamp t2 based on different bits.

Specifically, the a device 101 may record the time stamp t1 based on the X bits of the a frame and the time stamp t2 based on the Y bits of the B frame. Likewise, the B device 102 records the time stamp t3 based on the Y bits of the B frame and records the time stamp t4 based on the X bits of the A frame. Wherein the X bits may include one or more bits. Similarly, the Y bits may also include one or more bits.

Optionally, the timestamps t4 and t3 need to be recorded in order for the B device 102 to know when an a frame and a B frame are detected, respectively. The a device 101 may also first mark the X bits of the a frame and second mark the Y bits of the B frame. The first flag is used to indicate the position information of X bits in the a frame, and when the B device 102 detects the first flag, the position information of X bits in the a frame is obtained, and a timestamp t4 is generated based on the X bits. The second flag is used to indicate the position information of the Y bit in the B frame, and when the B device 102 detects the second flag, the position information of the Y bit in the B frame is obtained, and the timestamp t3 is generated based on the Y bit.

Several possible ways of marking the X-bits or the Y-bits are described below:

first, taking an a frame as an ethernet packet as an example, the a device 101 may perform a first marking on X bits in a preamble area of the ethernet packet.

Specifically, one or more bytes are selected in the preamble region and modified into a special pattern as the first mark. The first flag is used to indicate X bits of a target area located in the ethernet packet, where the target area may be a Destination Address (DA) area located after a Start-of-Frame Delimiter (SFD) in the ethernet packet.

Second, the a device 101 may first mark X bits in the overhead area of the B frame.

Fig. 3 is a schematic diagram of marking X bits in a frame. Specifically, the a device 101 may perform the first marking with an offset indication in the overhead area of the B frame. The flag is used to indicate X bits of a target region located in a payload region of a B frame.

Alternatively, the second marking may be performed on the Y bits in the B frame using the marking scheme as shown in fig. 3. For example, the Y bit may be one or more bits located in the header of the B frame, and the second flag may indicate the Y bit located in the header of the B frame.

It is understood that the a device 101 and the B device 102 may also agree in advance on X bits and Y bits for recording the time stamp, and then the a device 101 does not need to mark the X bits and the Y bits.

206. And determining to obtain the target time delay according to the time stamp information, the time stamp t3, the time stamp t4 and the link time delay.

In this embodiment, if the timestamp information includes timestamp t1 and timestamp t2, B device 102 calculates a first time difference obtained by subtracting timestamp t1 from timestamp t2 and a second time difference obtained by subtracting timestamp t3 from timestamp t4, and sums the first time difference, the second time difference, and the link delay to obtain a target delay, where the target delay represents a delay of an a frame transmitted from interface 101a to interface 102B.

Optionally, the timestamp information may also include a first time difference of the timestamp t2 minus the timestamp t 1. Then the B device 102 only needs to calculate the second time difference first, and then sum the first time difference, the second time difference, and the link delay to obtain the target delay.

It is understood that there is a link delay in the transmission of the B frame from the a device 101 to the B device 102. For example, the present application may be applied to an Optical Transport Network (OTN), and there is a fiber delay in the transmission of the B frame from the a device 101 to the B device 102. Furthermore, the device B and the device a may determine the optical fiber delay through a synchronization message of a 1588v2 protocol or a delay detection message defined by an ITU-T standard.

The proof principle of calculating the target time delay is as follows:

assume that the time offset between the A device 101 and the B device 102 is Δ AB, the link Delay is FiberD-AB, and the target Delay is Delay. Then the following equation can be obtained:

from the above formula it can be further deduced that:

Delay＝(t4-t1)-(t3-t2)+FiberD-AB＝(t4-t3)+(t2-t1)+FiberD-AB

it can be understood that, the foregoing embodiment introduces a method for calculating a one-way delay, and then a reverse delay may also be calculated based on the calculation method, which is not described herein again in detail.

It can be seen from the above proof principle that the time delay calculation method in the embodiment of the present application does not need to calculate the time difference between the device a 101 and the device B102, and omits a step of time synchronization between the two devices, so that the implementation manner is simpler.

It should be noted that the above embodiment describes a scheme in which the B device 102 at the receiving end calculates the target time delay. In addition, the A device 101 and the B device 102 may collectively transmit the recording time stamps t1-t4 and the link latency to the controller. Further, the target latency is calculated by the controller from the timestamps t1-t4 and the link latency. Alternatively, the delay calculation step may be performed by sending the delay calculation step to any other device in the network. The present application is not limited thereto.

The network architecture including the controller is described below.

Fig. 4 is a schematic diagram of a second network structure applied in the present application. In this embodiment, unlike the first network configuration shown in fig. 1, the system includes a controller 103 in addition to the a device 101 and the B device 102. Specifically, the a device 101 transmits its recorded time stamp t1 and time stamp t2 to the controller 103, and the B device 102 transmits its recorded time stamp t3 and time stamp t4 to the controller 103. Further, the a device 101 or the B device 102 may also transmit the acquired link delay to the controller 103. Further, the controller 103 calculates a first time difference obtained by subtracting the timestamp t1 from the timestamp t2 and a second time difference obtained by subtracting the timestamp t3 from the timestamp t4, and sums the first time difference, the second time difference and the link delay to obtain a target delay.

Alternatively, the a device 101 may first calculate a first time difference of the timestamp t2 minus the timestamp t1 and send the first time difference to the controller 103. The B device 102 may first calculate a second time difference of the timestamp t4 minus the timestamp t3 and send the second time difference to the controller 103. Further, the controller 103 sums the first time difference, the second time difference, and the link delay to obtain the target delay.

In practical applications, there may also be at least one intermediate device between the a device 101 and the B device 102. And the interface types at the two ends of the intermediate equipment are the same and the interface rates are the same. It will be appreciated that the intermediate device need only forward B frames from the a device 101 to the B device 102. Then the time stamp t5 and the time stamp t6 can be recorded when the two interfaces of the intermediate device detect B frames, respectively. In turn, the intermediary may send the timestamp t5 and the timestamp t6 to the B device 102. The B device 102 also needs to calculate a third time difference of the timestamp t6 minus the timestamp t5, and sum the first time difference, the second time difference, the third time difference, and the link delay to obtain the target delay. The link delay includes a link delay between the a device 101 and the intermediate device and a link delay between the B device 102 and the intermediate device.

It should be noted that the types of interfaces or the interface rates at the two ends of the above-mentioned intermediate device may also be different. The intermediate device needs to process the received frame in addition to forwarding. The following is described in conjunction with a practical scenario:

fig. 5 is a schematic diagram of a third network structure applied in the present application. In this embodiment, the intermediate devices between the a device 101 and the B device 102 include a C device 104 and a D device 105. The message is input from the interface 101a of the a device 101. The a device maps the packet to the OTU1 frame, and outputs the OTU1 frame through the interface 101 b. The C device 104 receives OTU1 frames through the interface 104 a. Further, the C device multiplexes the OTU1 frame to obtain an OTU2 frame, and outputs the OTU2 frame through the interface 104 b. The D device 105 receives OTU2 frames through the interface 105 a. Further, the D device demultiplexes the OUT2 frame to obtain an OUT1 frame, and outputs the OTU1 frame through the interface 105 b. The B device 102 receives the OUT1 frame through the interface 102 a. Further, the B device 102 demaps the OTU1 frame to obtain a message, and outputs the message through the interface 102B.

Note that the interface 101a is the same type as the interface 102 b. The interfaces 101b, 104a, 105b are of the same type as the interface 102 a. The interface 104b is of the same type as the interface 105 a. The a device 101 generates a timestamp t1 based on the X bits of the packet and generates a timestamp t2 based on the Y bits of the OTU1 frame. The C device 104 generates a timestamp t5 based on the Y bits of the OTU1 frame and a timestamp t6 based on the Z bits of the OTU2 frame. The D device 105 generates a timestamp t7 based on the Z bits of the OTU2 frame and a timestamp t8 based on the Y bits of the OTU1 frame. The B device 102 generates a timestamp t3 based on the Y bits of the OTU1 frame and a timestamp t4 based on the X bits of the packet.

Then, the target delay for the transmission of the packet from the a device 101 to the B device 102 may be calculated as follows:

Delay＝(t8-t7)+(t6-t5)+(t4-t3)+(t2-t1)+FiberD-AC+FiberD-CD+FiberD-DB

where Delay represents the target latency, FiberD-AC represents the link latency between A device 101 and C device 104, FiberD-CD represents the link latency between C device 104 and D device 105, and FiberD-DB represents the link latency between D device 105 and B device 102.

Alternatively, the target latency may be calculated by the B device 102. Or, referring to fig. 5, the a device 101, the B device 102, the C device 104, and the D device 105 collectively transmit time stamps t1-t8 to the controller 103, and the controller 103 calculates a target time delay. In addition, the sending method of the timestamp and the marking method of the bit are similar to those described in the embodiment shown in fig. 2, and are not described herein again.

The above describes the time delay calculation method in the embodiment of the present application, and the following describes the device B in the embodiment of the present application.

Fig. 6 is a schematic structural diagram of a possible B device according to the present application. The B device includes a processor 601, a memory 602, and a transceiver 603. The processor 601, memory 602 and transceiver 603 are interconnected by wires. Memory 602 is used to store, among other things, program instructions and data. It should be noted that the B device may be the B device 102 implementing the time delay calculation method in the embodiment shown in fig. 2.

In one possible implementation, the memory 602 stores program instructions and data supporting the steps shown in fig. 2, and the processor 601 and the transceiver 603 are used to perform the method steps shown in fig. 2. Specifically, the processor 601 is configured to perform the step 202 and 206 shown in fig. 2, and the transceiver 603 is configured to perform the step 201 shown in fig. 2.

It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a random access memory, or the like. Specifically, for example: the processing unit or processor may be a central processing unit, a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, a transistor logic device, a hardware component, or any combination thereof. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

When implemented in software, the method steps described in the above embodiments may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, cause the processes or functions described in accordance with the embodiments of the application to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, from one website site, computer, server, or data center to another website site, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that incorporates one or more of the available media. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., Solid State Disk (SSD)), among others.

Finally, it should be noted that: the above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (24)

1. A method for calculating a time delay, comprising:

the method comprises the steps that first equipment receives a first frame sent by second equipment through a second interface through a first interface;

the first device generates a first timestamp, wherein the first timestamp is a time when the first interface detects the first frame;

the first equipment analyzes the first frame to obtain a second frame, and outputs the second frame through a third interface, wherein the second frame is the same as a frame type input from a fourth interface of the second equipment, and a frame obtained by the second equipment through encapsulation according to the frame input from the fourth interface is the same as the first frame type;

the first device generates a second timestamp, wherein the second timestamp is a moment when the third interface detects a frame of the same type as the second frame;

the first device acquires timestamp information of the second device;

and determining to obtain a target time delay according to the first time stamp, the second time stamp, the time stamp information and a link time delay, wherein the target time delay represents the time delay of a frame transmitted from the fourth interface to the third interface, and the link time delay is the transmission time delay between the first device and the second device.

2. The method of claim 1, wherein the timestamp information comprises a third timestamp and a fourth timestamp, and wherein the third timestamp is a time when the fourth interface detects the frame of the same type as the second frame, and wherein the fourth timestamp is a time when the second interface detects the first frame.

3. The method of claim 2, wherein determining a target latency based on the first timestamp, the second timestamp, the timestamp information, and a link latency comprises:

and the first equipment calculates a first time difference obtained by subtracting the first time stamp from the second time stamp and a second time difference obtained by subtracting the third time stamp from the fourth time stamp, and sums the first time difference, the second time difference and the link delay to obtain a target delay.

4. The method of claim 2 or 3, wherein the first frame carries the fourth timestamp and the third timestamp; or, the first frame carries the fourth timestamp, and the frame of the same type as the second frame carries the third timestamp; or at least one frame transmitted after the first frame carries the fourth timestamp and the third timestamp.

5. The method of claim 1, wherein the timestamp information comprises a second time difference of a fourth timestamp minus a third timestamp, the third timestamp being a time when the fourth interface detected the frame of the same type as the second frame, and the fourth timestamp being a time when the second interface detected the first frame.

6. The method of claim 5, wherein determining a target latency based on the first timestamp, the second timestamp, the timestamp information, and a link latency comprises:

and the first equipment calculates a first time difference obtained by subtracting the first time stamp from the second time stamp, and sums the first time difference, the second time difference and the link delay to obtain a target delay.

7. The method according to claim 5 or 6, wherein the first frame carries the second time difference; or at least one frame transmitted after the first frame carries the second time difference.

8. The method according to any one of claims 1 to 7, wherein the first timestamp is a time when the first interface detects the first bit of the first frame, the fourth timestamp is a time when the second interface detects the first bit of the first frame, the second timestamp is a time when the third interface detects the second bit of the frame of the same type as the second frame, and the third timestamp is a time when the fourth interface detects the frame of the same type as the second frame.

9. The method of claim 8, wherein the first frame comprises a first flag indicating the position information of the first bit in the first frame, and wherein the frame of the same type as the second frame comprises a second flag indicating the position information of the second bit in the frame of the same type as the second frame.

10. The method according to any of claims 1 to 9, wherein the type of the first frame comprises an Optical Transport Unit (OTU) frame, a flexible Ethernet Flexe frame, or a Metro Transport Network (MTN) frame, and the type of the second frame comprises an Optical Transport Unit (OTU) frame, a flexible Ethernet Flexe frame, a Metro Transport Network (MTN) frame, or an Ether packet.

11. The method of any one of claims 1 to 10, wherein the first device obtaining the link latency between the first device and the second device comprises:

and the first equipment determines the link delay through a synchronous message of a 1588v2 protocol or a delay detection message of an ITU-T standard.

12. The method of claim 1, wherein before determining a target latency based on the first timestamp, the second timestamp, the timestamp information, and a link latency, the method further comprises:

the first device sends the first timestamp, the second timestamp, the timestamp information and the link delay to a controller;

determining to obtain the target delay according to the first timestamp, the second timestamp, the timestamp information, and the link delay includes:

and the controller determines to obtain the target time delay according to the first time stamp, the second time stamp, the time stamp information and the link time delay.

13. A first device, comprising:

the system comprises a processor, a memory and a transceiver, wherein the processor, the memory and the transceiver are interconnected through lines;

the transceiver receives a first frame sent by a second device through a second interface through a first interface;

the processor calls program code in the memory for performing the steps of:

generating a first timestamp, which is a time when the first interface detects the first frame;

analyzing the first frame to obtain a second frame, and outputting the second frame through a third interface, wherein the second frame is the same as a frame type input from a fourth interface of the second device, and a frame encapsulated by the second device according to the frame input from the fourth interface is the same as the first frame type;

generating a second timestamp, where the second timestamp is a time when the third interface detects a frame of the same type as the second frame;

acquiring timestamp information of the second device;

and determining to obtain a target time delay according to the first time stamp, the second time stamp, the time stamp information and a link time delay, wherein the target time delay represents the time delay of a frame transmitted from the fourth interface to the third interface, and the link time delay is the transmission time delay between the first device and the second device.

14. The first device of claim 13, wherein the timestamp information comprises a third timestamp that is a time when the fourth interface detected the frame of the same type as the second frame, and a fourth timestamp that is a time when the second interface detected the first frame.

15. The first device of claim 14, wherein the processor is specifically configured to:

and calculating a first time difference obtained by subtracting the first time stamp from the second time stamp and a second time difference obtained by subtracting the third time stamp from the fourth time stamp, and summing the first time difference, the second time difference and the link delay to obtain a target delay.

16. The first device of claim 14 or 15, wherein the first frame carries the fourth timestamp and the third timestamp; or, the first frame carries the fourth timestamp, and the frame of the same type as the second frame carries the third timestamp; or at least one frame transmitted after the first frame carries the fourth timestamp and the third timestamp.

17. The first device of claim 13, wherein the timestamp information comprises a second time difference of a fourth timestamp minus a third timestamp, the third timestamp being a time when the fourth interface detected the frame of the same type as the second frame, the fourth timestamp being a time when the second interface detected the first frame.

18. The first device of claim 17, wherein the processor is specifically configured to:

and calculating a first time difference obtained by subtracting the first time stamp from the second time stamp, and summing the first time difference, the second time difference and the link delay to obtain a target delay.

19. The first device of claim 17 or 18, wherein the first frame carries the second time difference; or at least one frame transmitted after the first frame carries the second time difference.

20. The first device according to any one of claims 13 to 19, wherein the first timestamp is a time when the first interface detects the first bit of the first frame, the fourth timestamp is a time when the second interface detects the first bit of the first frame, the second timestamp is a time when the third interface detects the second bit of the frame of the same type as the second frame, and the third timestamp is a time when the fourth interface detects the second bit of the frame of the same type as the second frame.

21. The first device of claim 20, wherein the first frame comprises a first flag indicating location information of the first bit in the first frame, wherein the frame of the same type as the second frame comprises a second flag indicating location information of the second bit in the frame of the same type as the second frame.

22. The first device according to any of claims 13 to 20, wherein the type of the first frame comprises an optical transport unit OTU frame, a flexible ethernet FlexE frame, or a metro transport network MTN frame, and the type of the second frame comprises an optical transport unit OTU frame, a flexible ethernet FlexE frame, a metro transport network MTN frame, or an ethernet packet.

23. The first device of any one of claims 13 to 22, wherein the processor is specifically configured to:

and determining the link delay through a synchronous message of a 1588v2 protocol or a delay detection message of an ITU-T standard.

24. The first device of claim 13, wherein the transceiver is further configured to:

and sending the first timestamp, the second timestamp, the timestamp information and the link delay to a controller.

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