CN112737959A - 1553B bus RT node router - Google Patents
1553B bus RT node router Download PDFInfo
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- CN112737959A CN112737959A CN202011610057.5A CN202011610057A CN112737959A CN 112737959 A CN112737959 A CN 112737959A CN 202011610057 A CN202011610057 A CN 202011610057A CN 112737959 A CN112737959 A CN 112737959A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/60—Router architectures
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/74—Address processing for routing
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Abstract
The invention discloses a 1553B bus RT node router, which comprises: a plurality of remote terminals RT with the same RT address; FPGA, including RT data fusion module, BC instruction transmission module, be connected with configuration information module and RT data transmission module on RT data fusion module, wherein: the configuration information module is used for generating configuration information, and the configuration information is used for configuring which remote terminal RT the current bit data is taken from in the RT data fusion process; the RT data fusion module is used for fusing the received single-ended signals from the RTs of different remote terminals according to the configuration of the configuration information module; the RT data transmission module is used for transmitting each fused data generated in the RT data fusion module to the bus controller in real time; and the BC instruction transmission module is used for respectively transmitting the BC instruction transmitted by the bus controller to each remote terminal RT. The invention effectively solves the problem that one BC device can not communicate with a plurality of devices with the same RT address at the same time.
Description
Technical Field
The invention relates to the field of 1553B bus communication, in particular to a 1553B bus RT node router.
Background
Because the electromechanical system adopts a distributed architecture, a single device can correspond to a plurality of systems, and thus the same device can be simultaneously and respectively placed in different areas; the existing electromechanical bus network uses a 1553B bus. According to a 1553B bus protocol, if a plurality of remote terminal devices with the same RT (remote terminal) address exist on the same bus at the same time, when a bus controller schedules the device with the RT address, a plurality of devices can transmit data on the bus at the same time, and therefore bus communication failure is caused; the prior art cannot solve the problem that one BC (bus controller) device of a 1553B bus communicates with a plurality of devices with the same RT address at the same time.
Disclosure of Invention
The invention aims to provide a 1553B bus RT node router which is used for solving the problem that one BC device cannot communicate with a plurality of devices with the same RT addresses at the same time.
In order to realize the task, the invention adopts the following technical scheme:
a 1553B bus RT node router, comprising:
the system comprises a plurality of remote terminals RT, a plurality of remote terminals RT and a plurality of remote terminals RT-;
FPGA, including RT data fusion module, BC instruction transmission module, be connected with configuration information module and RT data transmission module on RT data fusion module, wherein: the configuration information module is used for generating configuration information, and the configuration information is used for configuring which remote terminal RT the current bit data is taken from in the RT data fusion process; the RT data fusion module is used for fusing the received single-ended signals from the RTs of different remote terminals according to the configuration of the configuration information module; the RT data transmission module is used for transmitting each fused data generated in the RT data fusion module to the bus controller in real time; and the BC instruction transmission module is used for respectively transmitting the BC instruction transmitted by the bus controller to each remote terminal RT.
Further, the 1553B bus RT node router further comprises: a first interface unit;
the first interface unit includes: the first transformers are in one-to-one correspondence with the remote terminals RT and first interface chips in one-to-one correspondence with the transformers, wherein the first transformers are used for converting bus information of the remote terminals RT into bus signals which can be identified by the interface chips; the first interface chip is used for converting the bus signal from a differential signal into a single-ended signal so as to enable the single-ended signal to be matched with the level standard of the FPGA;
further, the first interface chip is further configured to send the BC instruction sent by the FPGA to the remote terminal RT through the first transformer.
Further, the 1553B bus RT node router further comprises: a second interface unit;
the second interface unit includes: the RT data transmission module is used for transmitting the fused data to the second interface chip; the second transformer is used for converting the differential signal into bus information which can be identified by the bus controller.
Furthermore, the configuration information is consistent with the data length of the data to be fused, and each bit of the configuration information specifies which remote terminal the current bit of the fused data is taken from in the data fusion process; when data fusion is carried out, for the current bit of the fusion data, the corresponding bit in the configuration information is read, the data sent by which remote terminal is specified by the corresponding bit is inquired as the current bit, the data in the bit in the single-ended signal of the remote terminal is taken out after the determination and is used as the current bit of the fusion data, and the fused current bit data is transmitted to the bus controller through the RT data transmission module in real time.
Furthermore, the RT node router transmits 1553B bus information sent by the bus controller to the interior of the FPGA through a second transformer and a second interface chip, and the FPGA transmits the received bus data to a plurality of remote terminals with the same RT addresses in real time through a first interface chip and a first transformer; after receiving the data sent by the bus controller, all the remote terminals start to send respective data to the 1553B bus through the RT node router, and in the process, the RT node router fuses the data sent by the two RTs.
Furthermore, after the FPGA is electrified, a bus controller BC instruction is waited in real time, after the BC instruction is found to arrive, the received bus information is simultaneously transmitted to two RT terminals, and the RT returns a state word and a data word after receiving an effective instruction; and for the current transmission bit, the FPGA determines the RT data to be transmitted according to the configuration information.
Further, after all the data is transmitted, the next bus information is continuously waited for.
Compared with the prior art, the invention has the following technical characteristics:
the scheme designs an RT node router which can transmit a bus command sent by the BC to two devices with the same RT address in real time, then switches data returned by the two RT devices in real time according to bits, respectively obtains effective bits of corresponding systems, and transmits the effective bits to a BC device end through an upper-layer 1553B bus. For the BC device side, it is equivalent to that data corresponding to the RT address is received after the command is issued. The invention effectively solves the problem that the BC equipment can not communicate with a plurality of pieces of equipment with the same RT address at the same time, and can realize the fusion of data sent by different remote terminal equipment with the same RT address, thereby avoiding the problem of low efficiency caused by the fusion after the data are respectively received by the traditional method.
Drawings
FIG. 1 is a schematic diagram of an overall structure of a 1553B bus RT node router in the invention;
FIG. 2 is a FPGA work flow diagram;
fig. 3 is a working connection diagram of the RT node router.
Detailed Description
Referring to fig. 1, the present invention discloses a 1553B bus RT node router, which comprises:
the system comprises a plurality of remote terminals RT, a plurality of remote terminals RT and a plurality of remote terminals RT-;
the first transformers correspond to the remote terminals RT one by one and are used for converting bus information of the remote terminals RT into bus signals which can be identified by the interface chip;
the first interface chips are in one-to-one correspondence with the transformers and are used for converting bus signals from differential signals into single-ended signals so as to enable the bus signals to be matched with the level standard of the FPGA; the first interface chip is also used for sending the BC instruction sent by the FPGA to a remote terminal RT through a first transformer;
the FPGA is a core processing module of the RT node router and mainly completes BC instruction real-time distribution and route switching of two RT return data; the working flow of the FPGA is shown in fig. 2. FPGA includes RT data fusion module, BC instruction transmission module, is connected with configuration information module and RT data transmission module on RT data fusion module, wherein: the configuration information module is used for generating configuration information, and the configuration information is used for configuring which remote terminal RT the current bit data is taken from in the RT data fusion process; the RT data fusion module is used for fusing the single-ended signals of the RT of different remote terminals transmitted by the interface chip according to the configuration of the configuration information module; the RT data transmission module is used for transmitting each fused data generated in the RT data fusion module to the bus controller in real time through the second interface chip and the second transformer; and the BC instruction transmission module is used for transmitting the BC instruction transmitted by the bus controller through the second transformer and the second interface chip to each remote terminal RT through each first interface chip and the first transformer.
The configuration information is configured according to needs, the length of the configuration information is consistent with that of data needing to be fused, and each bit of the configuration information specifies which remote terminal the current bit of the fused data is taken from in the data fusion process; for example, there are two RTs: the system comprises an RTA and an RTB, wherein the RTA and the RTB are sent to a single-ended signal needing to be fused of an RT data fusion module through a transformer and an interface chip and are marked as a signal A and a signal B, and the length of the signal A and the length of the signal B are consistent with that of the configuration information, for example, the signal A and the signal B are 16 bits; when data fusion is carried out, for the current bit of the fusion data, the corresponding bit in the configuration information is read, the data of which the corresponding bit specifies RTA or RTB is inquired as the current bit, for example, the specified RTA is specified, the data in the bit in the single-ended signal of the RTA is taken out as the current bit of the fusion data, and the fused current bit data is transmitted to the bus controller through the RT data transmission module in real time.
The second interface chip is used for converting the fused data transmitted by the RT data transmission module from a single-ended signal to a differential signal and transmitting the differential signal to the second transformer;
the second transformer is used for converting the differential signal into bus information which can be identified by the bus controller.
In fig. 1, the working process of the router of the present invention is illustrated by taking two remote terminals RT as an example:
the RT node router transmits 1553B bus information sent by the bus controller to the FPGA through a second transformer and a second interface chip, and the FPGA transmits the received bus data to two remote terminals RTA and RTB with the same RT address in real time through a first interface chip and a first transformer; after receiving the data sent by the bus controller, the RTA and the RTB start to send respective data to a 1553B bus through the RT node router, and in the process, the RT node router fuses the data sent by the two RTs, and the principle is as follows: the FPGA switches and transmits data sent by the two RTs in real time according to bits, and the configuration information determines which RT terminal the current transmission bit is taken from.
After the FPGA is electrified, a bus controller BC instruction is waited in real time, after the BC instruction is found to arrive, the received bus information (bit information) is simultaneously transmitted to two RT terminals, and the RT returns a state word and a data word after receiving an effective instruction; and for the current transmission bit, the FPGA determines RT data to be transmitted according to the configuration information, transmits the bit information corresponding to the RTA when the configuration information is 1, and transmits the bit information corresponding to the RTB when the configuration information is 0. And after all the data are transmitted, continuing waiting for the arrival of the next bus information.
Example (b):
in this embodiment, according to the scheme provided by the present invention, two routers of the RT node are designed, and a 1553B bus network is formed by the two routers, the BC device and the two RT devices, and the connection relationship is shown in fig. 3.
The FPGA adopts an EP4CE15E22C8N chip of ALTERA company, 63KB is embedded in the FPGA for storage, and 15000 logic units can meet the design requirements of the system. Because the airborne 1553B bus network adopts a coupler connection mode, the transformer adopts DB2725 and a 1:1.79 transformation ratio connection mode is selected. The interface chip adopts HI-1573 with 3.3V level standard and can be matched with the interface level of FPGA
The BC device sends an instruction word 0X3421 meaning that one byte of data with an RT address of 6 is to be received. The RTA device simulates a remote terminal with an RT address of 6 and sends a data word of 0X5555, the RTB device simulates a remote terminal with an RT address of 6 and sends a data word of 0XAAAA, the configuration information of the RT node router is set to be 0XFF00, and the data received by the BC end is 0X55 AA.
The RT node router transmits 1553B bus information (0X3421) sent by the bus controller to the interior of the FPGA through a transformer and an interface chip. And the FPGA transmits the received bus data to two remote terminal devices with the same RT addresses in real time through an interface chip and a transformer. The two remote end devices will output their respective data onto the 1553B bus. The FPGA switches and transmits data sent by the two RTs in real time according to configuration information (0XFF00) in a bit-by-bit manner, and the RT information received by the BC equipment is actually measured to be 0X55AA, so that the design requirement is met.
The bus protocol specifies that the response time of RT to BC is not more than 12 mus; in a general transmission mode, a response is sent from the BC to the RT, and about 6 mu s is needed; by adopting the framework provided by the embodiment of the invention, the actual measurement response time is 7.6 mus on the basis of solving the problem that a plurality of devices with the same RT address communicate with BC at the same time, and the requirements of response time and real-time transmission are met.
The above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equally replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application, and are intended to be included within the scope of the present application.
Claims (8)
1. A 1553B bus RT node router, comprising:
the system comprises a plurality of remote terminals RT, a plurality of remote terminals RT and a plurality of remote terminals RT-;
FPGA, including RT data fusion module, BC instruction transmission module, be connected with configuration information module and RT data transmission module on RT data fusion module, wherein: the configuration information module is used for generating configuration information, and the configuration information is used for configuring which remote terminal RT the current bit data is taken from in the RT data fusion process; the RT data fusion module is used for fusing the received single-ended signals from the RTs of different remote terminals according to the configuration of the configuration information module; the RT data transmission module is used for transmitting each fused data generated in the RT data fusion module to the bus controller in real time; and the BC instruction transmission module is used for respectively transmitting the BC instruction transmitted by the bus controller to each remote terminal RT.
2. The 1553B bus RT node router of claim 1, wherein the 1553B bus RT node router further comprises: a first interface unit;
the first interface unit includes: the first transformers are in one-to-one correspondence with the remote terminals RT and first interface chips in one-to-one correspondence with the transformers, wherein the first transformers are used for converting bus information of the remote terminals RT into bus signals which can be identified by the interface chips; the first interface chip is used for converting the bus signals from differential signals into single-ended signals so as to enable the bus signals to be matched with the level standard of the FPGA.
3. The 1553B bus RT node router of claim 2, wherein the first interface chip is further configured to send the BC command sent by the FPGA to the remote terminal RT through the first transformer.
4. The 1553B bus RT node router of claim 2, wherein the 1553B bus RT node router further comprises: a second interface unit;
the second interface unit includes: the RT data transmission module is used for transmitting the fused data to the second interface chip; the second transformer is used for converting the differential signal into bus information which can be identified by the bus controller.
5. The 1553B bus RT node router of claim 1, wherein the configuration information is consistent with the data length of the data to be fused, and each bit of the configuration information specifies from which remote terminal the current bit of the fused data is taken during the data fusion process; when data fusion is carried out, for the current bit of the fusion data, the corresponding bit in the configuration information is read, the data sent by which remote terminal is specified by the corresponding bit is inquired as the current bit, the data in the bit in the single-ended signal of the remote terminal is taken out after the determination and is used as the current bit of the fusion data, and the fused current bit data is transmitted to the bus controller through the RT data transmission module in real time.
6. The 1553B bus RT node router of claim 4, wherein the RT node router transmits 1553B bus information sent by the bus controller to the interior of the FPGA through a second transformer and a second interface chip, and the FPGA transmits the received bus data to a plurality of remote terminals with the same RT address in real time through a first interface chip and a first transformer; after receiving the data sent by the bus controller, all the remote terminals start to send respective data to the 1553B bus through the RT node router, and in the process, the RT node router fuses the data sent by the two RTs.
7. The 1553B bus RT node router of claim 1, wherein after the FPGA is powered on, the FPGA waits for a bus controller BC instruction in real time, when the BC instruction arrives, the received bus information is transmitted to two RT terminals at the same time, and the RT returns a status word and a data word after receiving a valid instruction; and for the current transmission bit, the FPGA determines the RT data to be transmitted according to the configuration information.
8. The 1553B bus RT node router of claim 7, wherein after all data is transmitted, it continues to wait for the next bus message to arrive.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113609052A (en) * | 2021-07-30 | 2021-11-05 | 上海创景信息科技有限公司 | Chip simulation system based on FPGA and microprocessor and implementation method |
| CN114356830A (en) * | 2022-03-15 | 2022-04-15 | 北京国科天迅科技有限公司 | Bus terminal control method, device, computer equipment and storage medium |
Citations (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070160075A1 (en) * | 2005-10-10 | 2007-07-12 | Yehoshua Carpassi | Device, system and method of communicating between a bus controller and one or more remote terminals |
| CN102411553A (en) * | 2011-08-01 | 2012-04-11 | 北京航空航天大学 | Compact peripheral components interconnect (CPCI)-bus-based 1553B protocol data communication and serial loading module |
| CN102938713A (en) * | 2011-08-15 | 2013-02-20 | 中国航空工业集团公司西安飞机设计研究所 | 1553B data bus testing simulation system |
| CN103067205A (en) * | 2012-12-27 | 2013-04-24 | 中国航空工业集团公司第六三一研究所 | Switchover method of receiver-transmitter (RT) and back-up RT using same address under same host management |
| CN103077143A (en) * | 2012-12-27 | 2013-05-01 | 中国航空工业集团公司第六三一研究所 | Method for refreshing data from remote terminal (RT) |
| CN103237016A (en) * | 2013-03-29 | 2013-08-07 | 北京航天自动控制研究所 | 1553B multi-remote-terminal simulation equivalence device |
| US20150089099A1 (en) * | 2013-09-23 | 2015-03-26 | Raytheon Company | Military standard (mil-std-1760) interface bridge |
| US20160056906A1 (en) * | 2014-08-21 | 2016-02-25 | Ge Aviation Systems Llc | Method and system to add and communicate with remote terminal addresses beyond a standard bus protocol |
| CN105530155A (en) * | 2015-12-11 | 2016-04-27 | 中国航空工业集团公司西安航空计算技术研究所 | 1553B bus universe message triggering control method |
| CN106790104A (en) * | 2016-12-26 | 2017-05-31 | 中国科学院空间应用工程与技术中心 | IP communications and the communication means of FC AE 1553 between multi-protocols emerging system, node |
| US20180285309A1 (en) * | 2017-03-30 | 2018-10-04 | Government Of The United States, As Represented By The Secretary Of The Air Force | Data bus message filter |
| CN109491950A (en) * | 2018-09-26 | 2019-03-19 | 北京时代民芯科技有限公司 | A kind of simplified system interface 1553B remote terminal circuit |
| CN110704355A (en) * | 2019-09-23 | 2020-01-17 | 天津津航计算技术研究所 | Method for receiving and processing 1553B bus data by using dual-port RAM |
| CN111130966A (en) * | 2019-12-24 | 2020-05-08 | 中国航空工业集团公司西安飞机设计研究所 | 1553B bus real-time filtering device and filtering transmission method |
| US20200336420A1 (en) * | 2018-01-05 | 2020-10-22 | Telefonaktiebolaget Lm Ericsson (Publ) | Data center failure management in an sdn deployment using border gateway node control |
| CN112118165A (en) * | 2020-09-09 | 2020-12-22 | 天津津航计算技术研究所 | 1553B bus message channel switching control method |
-
2020
- 2020-12-29 CN CN202011610057.5A patent/CN112737959B/en active Active
Patent Citations (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070160075A1 (en) * | 2005-10-10 | 2007-07-12 | Yehoshua Carpassi | Device, system and method of communicating between a bus controller and one or more remote terminals |
| CN102411553A (en) * | 2011-08-01 | 2012-04-11 | 北京航空航天大学 | Compact peripheral components interconnect (CPCI)-bus-based 1553B protocol data communication and serial loading module |
| CN102938713A (en) * | 2011-08-15 | 2013-02-20 | 中国航空工业集团公司西安飞机设计研究所 | 1553B data bus testing simulation system |
| CN103067205A (en) * | 2012-12-27 | 2013-04-24 | 中国航空工业集团公司第六三一研究所 | Switchover method of receiver-transmitter (RT) and back-up RT using same address under same host management |
| CN103077143A (en) * | 2012-12-27 | 2013-05-01 | 中国航空工业集团公司第六三一研究所 | Method for refreshing data from remote terminal (RT) |
| CN103237016A (en) * | 2013-03-29 | 2013-08-07 | 北京航天自动控制研究所 | 1553B multi-remote-terminal simulation equivalence device |
| US20150089099A1 (en) * | 2013-09-23 | 2015-03-26 | Raytheon Company | Military standard (mil-std-1760) interface bridge |
| US20160056906A1 (en) * | 2014-08-21 | 2016-02-25 | Ge Aviation Systems Llc | Method and system to add and communicate with remote terminal addresses beyond a standard bus protocol |
| CN105530155A (en) * | 2015-12-11 | 2016-04-27 | 中国航空工业集团公司西安航空计算技术研究所 | 1553B bus universe message triggering control method |
| CN106790104A (en) * | 2016-12-26 | 2017-05-31 | 中国科学院空间应用工程与技术中心 | IP communications and the communication means of FC AE 1553 between multi-protocols emerging system, node |
| US20180285309A1 (en) * | 2017-03-30 | 2018-10-04 | Government Of The United States, As Represented By The Secretary Of The Air Force | Data bus message filter |
| US20200336420A1 (en) * | 2018-01-05 | 2020-10-22 | Telefonaktiebolaget Lm Ericsson (Publ) | Data center failure management in an sdn deployment using border gateway node control |
| CN109491950A (en) * | 2018-09-26 | 2019-03-19 | 北京时代民芯科技有限公司 | A kind of simplified system interface 1553B remote terminal circuit |
| CN110704355A (en) * | 2019-09-23 | 2020-01-17 | 天津津航计算技术研究所 | Method for receiving and processing 1553B bus data by using dual-port RAM |
| CN111130966A (en) * | 2019-12-24 | 2020-05-08 | 中国航空工业集团公司西安飞机设计研究所 | 1553B bus real-time filtering device and filtering transmission method |
| CN112118165A (en) * | 2020-09-09 | 2020-12-22 | 天津津航计算技术研究所 | 1553B bus message channel switching control method |
Non-Patent Citations (2)
| Title |
|---|
| SHONA J KAPPAN等: ""Avionic Data acquisition system using MIL STD 1553B controller with IRIG-B timecode decoder"", 《2014 INTERNATIONAL CONFERENCE ON CIRCUITS, POWER AND COMPUTING TECHNOLOGIES [ICCPCT-2014]》, 5 March 2015 (2015-03-05) * |
| 张书滨等: ""1553B总线大块数据传输的解决方法"", 《工业控制计算机》, 31 May 2010 (2010-05-31) * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113609052A (en) * | 2021-07-30 | 2021-11-05 | 上海创景信息科技有限公司 | Chip simulation system based on FPGA and microprocessor and implementation method |
| CN114356830A (en) * | 2022-03-15 | 2022-04-15 | 北京国科天迅科技有限公司 | Bus terminal control method, device, computer equipment and storage medium |
| CN114356830B (en) * | 2022-03-15 | 2022-06-21 | 北京国科天迅科技有限公司 | Bus terminal control method, device, computer equipment and storage medium |
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