CN112737545B - Numerical control attenuator controlled by ADC - Google Patents
Numerical control attenuator controlled by ADC Download PDFInfo
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- CN112737545B CN112737545B CN202011554500.1A CN202011554500A CN112737545B CN 112737545 B CN112737545 B CN 112737545B CN 202011554500 A CN202011554500 A CN 202011554500A CN 112737545 B CN112737545 B CN 112737545B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/0054—Attenuators
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H11/00—Networks using active elements
- H03H11/02—Multiple-port networks
- H03H11/24—Frequency-independent attenuators
- H03H11/245—Frequency-independent attenuators using field-effect transistor
Abstract
The invention provides a numerical control attenuator controlled by an ADC (analog to digital converter), which comprises an ADC unit and a numerical control attenuator unit; analog voltage is input into an analog input end of the ADC unit, and an output end of the ADC unit is respectively connected with a control input end of the numerical control attenuator unit; and the radio frequency signal is input into the numerical control attenuator unit and is output after attenuation control. Compared with the design of the traditional numerical control attenuator, the numerical control attenuator changes the control mode of the attenuator by adding the ADC unit, realizes the continuous analog voltage control attenuator, simultaneously integrates the driver in the ADC unit, reduces the control ports, realizes the parallel control attenuator, and improves the wave control speed and the circuit integration level.
Description
Technical Field
The application belongs to the technical field of numerical control attenuators, and particularly relates to a numerical control attenuator which is manufactured by adopting a GaAs pHEMT (pseudo-mismatched high electron mobility field effect transistor) process and is controlled by an ADC (Analog-to-Digital Converter).
Background
The digital control attenuator and the voltage control attenuator are both typical microwave control circuits, are widely applied in modern radio communication and space communication, particularly phased array radar, are indispensable rings, and have the function of regulating and controlling microwave gain through external signals according to system requirements so as to realize the function of radar electric scanning, so that the research on the digital control attenuator controlled by the ADC has great academic value and practical significance.
A depletion transistor (D tube) is provided by a switch control device of a classical numerical control attenuator designed based on a GaAs process, common attenuator structures comprise a T type for small attenuation, a bridge T type and a pi type for large attenuation and the like, and a proper topological structure is selected according to requirements in practical application. The numerical control attenuator is generally controlled by high and low levels, the total attenuation amount of the numerical control attenuator is the weighted sum of each attenuation module, each attenuation bit also needs two complementary control levels, and therefore a plurality of control bits are needed to control different attenuation modules respectively.
Disclosure of Invention
In order to solve the technical problems, the invention provides the numerical control attenuator controlled by the ADC, the control part of the traditional attenuator is changed, the integrated ADC is equivalent to the integrated monolithic driver, the control ports are reduced, and the analog voltage control attenuator is realized.
The invention relates to a numerical control attenuator controlled by an ADC (analog to digital converter), which comprises an ADC unit and a numerical control attenuator unit which are sequentially connected, wherein the analog input end of the ADC unit is connected with an analog voltage, and the output end of the ADC unit is respectively and correspondingly connected with the control input end of the numerical control attenuator unit;
the ADC unit receives a signal input by an analog voltage, converts the signal into a digital binary code, and transmits the digital binary code to the numerical control attenuator unit;
after the input end of the numerical control attenuator unit receives the radio frequency signal, the ADC unit controls the data attenuator unit so as to regulate and control the gain amplitude of the radio frequency signal, and the radio frequency signal is output after attenuation control.
Further, the ADC unit comprises a positive reference voltage end V REF Positive and negative reference voltage terminal V REF An analog voltage input IN, resistors R0-R7 connected IN series IN sequence, and resistors connected IN parallel IN sequenceThe ADC unit further comprises AND gates AND1-AND3, NAND gates NAND1-NAND2, inverters N1 AND N2 AND OR gates OR1-OR3 which are connected in an interactive mode;
wherein, one end of the resistor R0 is connected with the negative reference voltage end V REF The other end of the resistor R1 is connected with the reference input end of the comparator C1; the other end of the resistor R1 is connected with the reference input end of the resistor R2 and the reference input end of the comparator C2; the other end of the resistor R2 is connected with a reference input end of the resistor R3 and a reference input end of the comparator C3; the other end of the resistor R3 is connected with a reference input end of the resistor R4 and a reference input end of the comparator C4; the other end of the resistor R4 is connected with the reference input end of the resistor R5 and the comparator C5; the other end of the resistor R5 is connected with a reference input end of the resistor R6 and a reference input end of the comparator C6; the other end of the resistor R6 is connected with the resistor R7 and the reference input end of the comparator C7; the other end of the resistor R7 is connected with a positive reference voltage end V REF +; the voltage input ends of the comparators C1-C7 are connected with an analog voltage input end IN; the output ends of the comparators C1 to C7 are respectively connected with the voltage input ends of the latches L1 to L7; the clock control ends of the latches L1 to L7 are all connected with a negative clock signal CLKN;
the output end of the latch L1 is connected with the positive input end of the AND gate AND 1; the output end of the latch L2 is connected with the negative input end of the AND gate AND1 AND the positive input end of the NAND gate NAND 1; the output end of the latch L3 is connected with the positive input end of the AND gate AND 2; the output end of the latch L4 is connected with the negative input end of the AND gate AND2, the negative input end of the NAND gate NAND1 AND the input end of the inverter N1; the output end of the latch L5 is connected with the positive input end of the AND gate AND 3; the output end of the latch L6 is connected with the negative input end of the AND gate AND3 AND the negative input end of the NAND gate NAND 2; the output end of the latch L7 is connected with one input end of the OR gate OR 1; the other input end of the OR gate OR1 is connected with the output end of the AND gate AND 3; the output end of the NAND gate NAND1 is connected with the positive input end of the NAND gate NAND 2; the output end of the AND gate AND1 is connected with one input end of the AND gate OR3; the output end of the AND gate AND2 is connected with the other input end of the AND gate OR3; the output end of the AND gate AND3 is connected with the other input end of the OR gate OR 1; the output end of the inverter N1 is connected with the input end of the inverter N2; the output end of the OR gate OR1 is connected with one input end of the OR gate OR 2; the output end of the AND gate OR3 is connected with the other input end of the OR gate OR 2; the output end of the phase inverter N2 is extracted as the highest data output bit2; the output end of the OR gate OR2 is extracted as the lowest bit data output bit0; the output end of the NAND gate NAND2 is extracted to be the medium data output bit1.
Further, the comparison latch comprises resistors R8-R12, transistors Q1-Q9, diodes D1, D2 and D3;
wherein, one end of the resistor R8 is connected with the resistor R9 and the resistor R10, the other end of the resistor R9 is connected with the collector of the transistor Q1, the collector of the transistor Q6 and the base of the transistor Q8, the other end of the resistor R10 is connected with the collector of the transistor Q2, the collector of the transistor Q7 and the base of the transistor Q9, the base of the transistor Q1 is connected with the analog input voltage IN, the base of the transistor Q2 is connected with the reference voltage V generated by the resistor chain REF The emitter electrodes of the transistor Q1 and the transistor Q2 are connected with the collector electrode of the transistor Q3, the emitter electrodes of the transistor Q6 and the transistor Q7 are connected with the collector electrode of the transistor Q4, the base electrode of the transistor Q3 is connected with a positive clock signal CLK, the base electrode of the transistor Q4 is connected with a negative clock signal CLKN, the emitter electrodes of the transistor Q3 and the transistor Q4 are connected with the collector electrode of the transistor Q5, the base electrode of the transistor Q5 is connected with a bias voltage VB, the emitter electrode of the transistor Q9 is connected with the anode electrode of the diode D1, the cathode electrode of the diode D1 is connected with the anode electrode of the diode D2, the cathode electrode of the diode D2 is connected with the anode electrode of the diode D3, the cathode electrode of the diode D3 is connected with a resistor R12 and then connected with the base electrode of the transistor Q6, and then extracted as a positive output OUT;
the emitter of the transistor Q8 is connected with the anode of the diode D4, the cathode of the diode D4 is connected with the anode of the diode D5, the cathode of the diode D5 is connected with the anode of the diode D6, the cathode of the diode D6 is connected with the resistor R11 and then connected to the base of the transistor Q7, then the negative output OUTN is extracted, the other end of the resistor R8 is connected with the collectors of the transistor Q8 and the transistor Q9 and then connected with the analog ground GND, and the other ends of the resistor R11 and the resistor R12 are connected and then connected to the emitter of the transistor Q5 and then connected to the negative power supply VEE.
Furthermore, the numerical control attenuator unit comprises a first attenuation module, a second attenuation module, a third attenuation module and a digital control attenuator unit, wherein the first attenuation module, the second attenuation module and the third attenuation module are sequentially connected;
the first attenuation module comprises resistors R13, R14 and R15 and a transistor Q10; one end of the resistor R13 is connected with a radio frequency input end RFIN1, the other end of the resistor R13 is connected with the resistor R14 and the collector of the transistor Q10, the other end of the resistor R14 outputs radio frequency output RFOUT1, the base electrode of the transistor Q10 is connected with a lowest bit data output end bit0 from the ADC, the emitter electrode of the transistor Q10 is connected with the resistor R15, and the other end of the resistor R15 is connected with a radio frequency ground RFGND;
the second attenuation module and the third attenuation module have the same structure and respectively comprise resistors R16, R17 and R18 and transistors Q11 and Q12; one end of the resistor R16 is connected with the radio frequency input end, the radio frequency output end RFOUT1 of the previous-stage attenuation module and the collector of the transistor Q11, the other end of the resistor R16 is connected with the resistor R17 and the collector of the transistor Q12, and the other end of the resistor R17 is connected with the emitter of the transistor Q11 and then outputs radio frequency output RFOUT2; the base electrode of the transistor Q12 is connected with the medium data output end bit1 from the ADC, the base electrode of the transistor Q11 is connected with the inverted phase of the medium data output end bit1 from the ADC, the emitting electrode of the transistor Q12 is connected with the resistor R18, and the other end of the resistor R18 is connected with the radio frequency ground RFGND.
Furthermore, each transistor forming the attenuator circuit adopts an E/D pHEMT field effect transistor.
The invention has the beneficial effects that:
1. according to the numerical control attenuator controlled by the ADC, the wave control speed of the attenuator is increased;
2. the digital control attenuator controlled by the ADC provided by the invention realizes the analog voltage control attenuator on the premise of not changing the function of the digital control attenuator.
Drawings
In order that the present invention may be more readily and clearly understood, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments that are illustrated in the appended drawings.
FIG. 1 is a block diagram of a conventional digitally controlled attenuator.
Fig. 2 is a general block diagram of the present invention.
Fig. 3 is an overall block diagram of an integrated 3-bit ADC.
Fig. 4 is a schematic circuit diagram of the ADC unit comparison latch.
Fig. 5 is a schematic circuit diagram of the first attenuation module.
Fig. 6 is a schematic circuit diagram of the second and third attenuation modules.
FIG. 7 is a truth table of the control logic of the ADC digital controlled attenuator of the present invention.
Detailed Description
FIG. 1 is a schematic diagram of a conventional digital controlled attenuator, which employs a parallel or serial-parallel unit to control the digital controlled attenuator; the invention provides a digital control attenuator controlled by an ADC (analog to digital converter) by changing a control unit of the attenuator on the basis of the traditional digital control attenuator as shown in figure 2. The digital control attenuator controlled by the ADC comprises an ADC unit and a digital control attenuator unit which are sequentially connected. The analog voltage is input into the ADC unit, the analog voltage is converted into digital codes by the ADC unit, the output digital codes are cascaded to a transistor switch base of the numerical control attenuator to complete numerical control steps, and the radio frequency signal passes through the numerical control attenuator controlled by the ADC unit to obtain gain amplitude controlled by the analog voltage.
The following is described in detail with reference to a specific embodiment, in which the ADC is a 3-bit Flash structure, and the digital controlled attenuator uses T-type and bridge T-type topologies, and implements 3-bit attenuations of 1dB, 2dB, and 4 dB.
For the digital control attenuator, the control signal is often discrete and discontinuous high and low level, so that an additional driver is needed in practical application. A specific 3-bit FlashADC circuit implementation block diagram is shown in FIG. 3, AND the unit circuit comprises a resistor chain 301, seven parallel comparison latch chains 302 consisting of comparators AND latches, AND an encoding circuit 303 consisting of AND gates AND1-AND3, NAND gates NAND1-NAND2, inverters N1 AND N2, OR gates OR1-OR 3.
The resistor chain 301 is used to generate the reference voltage required by the comparison latch; the seven comparison latches are used for comparing the input analog voltage with the reference voltage and latching the obtained result; the coding circuit is used for coding thermometer codes output by the seven comparison latches into 3-bit binary codes for controlling the attenuator.
One of the core circuits of the present invention, which is used for the ADC comparison latch, has a circuit structure block diagram as shown in fig. 4, in which the input of a transistor Q1 is an analog voltage, and a differential comparison pair transistor is formed by the transistor with the input of a reference voltage generated by a resistor chain 301; the transistor Q3 and the transistor Q4 form a clock input differential pair transistor, the transistor Q6 and the transistor Q7 form an output latch differential pair transistor, the base of the transistor Q5 is added with bias voltage to form a tail current source, and the transistor M8 and the transistor M9 are input transistors of an emitter follower. When the input clock CLK is logic 'high' and CLKN is logic 'low', the analog voltage IN is input from the base of Q1, the reference voltage is input from the base of Q2, the comparison result, namely tracking input, is obtained after comparison, the bases of feedback incident electrode followers Q8 and Q9 are extracted from the collector of the transistor, the diodes D1-D3 and D4-D6 provide level shift, the direct ratio comparison result OUT is output from D3, and the negative comparison result OUTN is output from D6. When the input clock CLK is logic "low" and CLKN is logic "high", the circuit operates in a latch mode, the transistors Q1 and Q2 stop tracking the input, and the bases of the transistors Q6 and Q7 are connected to the output signals OUT and OUTN, respectively, to complete latching of the signals. Seven comparison latches output seven thermometer codes, binary codes are output after encoding, and the low order to the high order are bit0, bit1 and bit2 respectively. In this embodiment, transistors Q1-Q9 are all E-mode pHEMT logic transistors.
The specific circuit design of the attenuation unit is as shown in fig. 5 and 6, and the attenuation unit is a 3-bit attenuator (1 dB, 2dB and 4 dB) with 1dB stepping, and adopts a classic T-type and bridge T-type structure, and comprises first attenuation modules consisting of resistors R13-R15 and a transistor Q10, and second and third attenuation modules consisting of resistors R16-R18 and transistors Q11 and Q12; one end of the resistor R13 is connected with a radio frequency input end RFIN1, the other end of the resistor R13 is connected with a resistor R14 and a collector of the transistor Q10, the other end of the resistor R14 outputs radio frequency output RFOUT1, the base electrode of the transistor Q10 is connected with a lowest data output end bit0 from the ADC, the emitter of the transistor Q10 is connected with a resistor R15, and the other end of the resistor R15 is connected with a radio frequency ground RFGND; when bit0 is at a high level, Q10 is turned on, attenuation is involved, and the device works in an attenuation state to complete 1dB attenuation; when bit0 is at low level, Q10 is closed, attenuation is closed, and the circuit works in a reference state to complete 0 attenuation.
One end of the resistor R16 is connected with the radio frequency input end, the radio frequency output end RFOUT1 of the previous-stage attenuation module and the collector of the transistor Q11, the other end of the resistor R16 is connected with the resistor R17 and the collector of the transistor Q12, and the other end of the resistor R17 is connected with the emitter of the transistor Q11 and then outputs radio frequency output RFOUT2; the base electrode of the transistor Q12 is connected with the medium and high bit data output ends bit1 and bit2 of the ADC, the base electrode of the transistor Q11 is connected with the inverted phases of the medium and high bit data output ends bit1 and bit2 of the ADC, the emitter electrode of the transistor Q12 is connected with the resistor R18, and the other end of the resistor R18 is connected with the radio frequency ground RFGND; and adjusting the resistance value according to the requirements of each attenuation module to realize different attenuation controls. When bit1 or bit2 is at high level, Q12 is turned on, Q11 is turned off, attenuation is introduced, and the device works in an attenuation state to complete 2dB and 4dB attenuation; when bit1 or bit2 is at low level, Q11 is turned on, Q12 is turned off, attenuation is turned off, and the device works in a reference state to complete 0 attenuation. Transistors Q10, Q11, and Q12 are all D-mode pHEMT logic transistors in this embodiment.
As an example, FIG. 7 is a truth table of the control logic of the ADC digital controlled attenuator, and it can be seen that as the input analog voltage is changed from V REF -to V REF The increase of + is followed by the bit of ADC output, and the attenuator switch transistor controlled by it also switches between "on" and "off" states, and the total attenuation is equal to the weighted sum of each attenuation module and its control bit.
To sum up, the numerical control attenuator by ADC control of this application has changed the control unit on traditional numerical control attenuator's basis, through ADC control numerical control attenuator, can be with analog voltage conversion binary code to reach control attenuator's purpose, integrated ADC unit, the driver module has been integrated to the transform phase, has reduced attenuator control voltage's port figure to a certain extent. Compared with the traditional attenuator only controlled by digital level, the attenuator realizes the control of the attenuator by analog voltage, improves the monolithic integration level and expands the application range of the attenuator.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention further, and all equivalent variations made by using the contents of the present specification and the drawings are within the scope of the present invention.
Claims (4)
1. A numerical control attenuator controlled by an ADC (analog to digital converter) is characterized by comprising an ADC unit and a numerical control attenuator unit which are sequentially connected, wherein the analog input end of the ADC unit is connected with an analog voltage, and the output end of the ADC unit is respectively and correspondingly connected with the control input end of the numerical control attenuator unit;
the ADC unit receives a signal input by an analog voltage, converts the signal into a digital binary code and transmits the digital binary code to the numerical control attenuator unit;
after the input end of the numerical control attenuator unit receives the radio frequency signal, the ADC unit controls the data attenuator unit so as to regulate and control the gain amplitude of the radio frequency signal, and the radio frequency signal is output after attenuation control;
the ADC unit comprises a positive reference voltage end V REF Positive and negative reference voltage terminal V REF The ADC unit comprises an analog voltage input end IN, resistors R0-R7 which are sequentially connected IN series, comparators C1-C7 which are sequentially connected IN parallel AND latches L1-L7, wherein each comparator AND latch are cascaded to form a comparison latch, AND the ADC unit further comprises AND gates AND1-AND3, NAND gates NAND1-NAND2, inverters N1 AND N2 AND OR gates OR1-OR3 which are connected IN an alternating manner;
wherein, one end of the resistor R0 is connected with the negative reference voltage end V REF The other end of the resistor R1 is connected with the reference input end of the comparator C1; the other end of the resistor R1 is connected with a reference input end of the resistor R2 and a reference input end of the comparator C2; the other end of the resistor R2 is connected with a reference input end of the resistor R3 and a reference input end of the comparator C3; the other end of the resistor R3 is connected with the resistor R4 and the reference input end of the comparator C4; the other end of the resistor R4 is connected with the reference input end of the resistor R5 and the comparator C5; the other end of the resistor R5 is connected with a reference input end of the resistor R6 and a reference input end of the comparator C6; the other end of the resistor R6 is connected with the resistor R7 and the reference input end of the comparator C7; the other end of the resistor R7 is connected with a positive reference voltage end V REF +; the voltage input ends of the comparators C1 to C7 are connected with an analog voltage input end IN; the output ends of the comparators C1 to C7 are respectively connected with the voltage input ends of the latches L1 to L7; the clock control ends of the latches L1 to L7 are all connected with a negative clock signal CLKN;
the output end of the latch L1 is connected with the positive input end of the AND gate AND 1; the output end of the latch L2 is connected with the negative input end of the AND gate AND1 AND the positive input end of the NAND gate NAND 1; the output end of the latch L3 is connected with the positive input end of the AND gate AND 2; the output end of the latch L4 is connected with the negative input end of the AND gate AND2, the negative input end of the NAND gate NAND1 AND the input end of the inverter N1; the output end of the latch L5 is connected with the positive input end of the AND gate AND 3; the output end of the latch L6 is connected with the negative input end of the AND gate AND3 AND the negative input end of the NAND gate NAND 2; the output end of the latch L7 is connected with one input end of the OR gate OR 1; the other input end of the OR gate OR1 is connected with the output end of the AND gate AND 3; the output end of the NAND gate NAND1 is connected with the positive input end of the NAND gate NAND 2; the output end of the AND gate AND1 is connected with one input end of the OR gate OR3; the output end of the AND gate AND2 is connected with the other input end of the OR gate OR3; the output end of the AND gate AND3 is connected with the other input end of the OR gate OR 1; the output end of the inverter N1 is connected with the input end of the inverter N2; the output end of the OR gate OR1 is connected with one input end of the OR gate OR 2; the output end of the OR gate OR3 is connected with the other input end of the OR gate OR 2; the output end of the phase inverter N2 is extracted as the highest data output bit2; the output end of the OR gate OR2 is extracted as the lowest bit data output bit0; the output end of the NAND gate NAND2 is extracted to be the medium data output bit1.
2. The digitally controlled attenuator of claim 1, wherein the comparison latch comprises resistors R8-R12, transistors Q1-Q9, diodes D1-D6;
wherein, one end of the resistor R8 is connected with the resistor R9 and the resistor R10, the other end of the resistor R9 is connected with the collector of the transistor Q1, the collector of the transistor Q6 and the base of the transistor Q8, the other end of the resistor R10 is connected with the collector of the transistor Q2, the collector of the transistor Q7 and the base of the transistor Q9, the base of the transistor Q1 is connected with the analog input voltage IN, the base of the transistor Q2 is connected with the reference voltage V generated by the resistor chain REF The emitters of transistors Q1 and Q2 are connected to the collector of transistor Q3, the emitters of transistors Q6 and Q7 are connected to the collector of transistor Q4, the base of transistor Q3 is connected to the positive clock signal CLK, the base of transistor Q4 is connected to the negative clock signal CLKN, the emitters of transistors Q3 and Q4 are connected to the collector of transistor Q5, and the base of transistor Q5 is connected to the bias voltageVB, the emitter of the transistor Q9 is connected with the anode of the diode D1, the cathode of the diode D1 is connected with the anode of the diode D2, the cathode of the diode D2 is connected with the anode of the diode D3, the cathode of the diode D3 is connected with the upper end of the resistor R12 and is extracted as a positive output OUT, and the positive output OUT is fed back to the base electrode of the transistor Q6;
the emitter of the transistor Q8 is connected with the anode of the diode D4, the cathode of the diode D4 is connected with the anode of the diode D5, the cathode of the diode D5 is connected with the anode of the diode D6, the cathode of the diode D6 is connected with the upper end of the resistor R11 and is extracted to be a negative output OUTN, the negative output OUTN is fed back to the base of the transistor Q7, the other end of the resistor R8 is connected with the collectors of the transistor Q8 and the transistor Q9 and then is connected with the analog ground GND, and the other ends of the resistor R11 and the resistor R12 are connected and then are connected to the emitter of the transistor Q5 and then are connected to the negative power supply VEE.
3. The digital controlled attenuator of claim 1, wherein the digital controlled attenuator unit comprises a first attenuation module, a second attenuation module, a third attenuation module and a digital control unit, wherein the first attenuation module, the second attenuation module and the digital control unit are connected in sequence;
the first attenuation module comprises resistors R13, R14 and R15 and a transistor Q10; one end of the resistor R13 is connected with a radio frequency input end RFIN1, the other end of the resistor R13 is connected with a resistor R14 and a collector of the transistor Q10, the other end of the resistor R14 outputs radio frequency output RFOUT1, the base electrode of the transistor Q10 is connected with a lowest bit data output end bit0 from the ADC unit, the emitter electrode of the transistor Q10 is connected with the resistor R15, and the other end of the resistor R15 is connected with a radio frequency ground RFGND;
the second attenuation module and the third attenuation module have the same structure and respectively comprise resistors R16, R17 and R18 and transistors Q11 and Q12; one end of the resistor R16 is connected with a radio frequency output end RFOUT1 of the previous-stage attenuation module and a collector of the transistor Q11, the other end of the resistor R16 is connected with a resistor R17 and a collector of the transistor Q12, and the other end of the resistor R17 is connected with an emitter of the transistor Q11 and then outputs radio frequency output RFOUT2; the base electrode of the transistor Q12 is connected with the medium data output end bit1 from the ADC unit, the base electrode of the transistor Q11 is connected with the inverted phase of the medium data output end bit1 from the ADC unit, the emitting electrode of the transistor Q12 is connected with the resistor R18, and the other end of the resistor R18 is connected with the radio frequency ground RFGND.
4. An ADC controlled digital controlled attenuator according to any one of claims 1 to 3, wherein each transistor constituting the attenuator circuit is an E/D pHEMT field effect transistor.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106656100A (en) * | 2016-12-29 | 2017-05-10 | 福建利利普光电科技有限公司 | Single-end to double-end differential analog circuit |
| CN109714020A (en) * | 2019-02-22 | 2019-05-03 | 南京国博电子有限公司 | For controlling the circuit of numerical-control attenuator overshoot |
| CN110855266A (en) * | 2019-11-27 | 2020-02-28 | 西安博瑞集信电子科技有限公司 | Single-voltage positive-voltage driven single-chip numerical control attenuator chip |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106656100A (en) * | 2016-12-29 | 2017-05-10 | 福建利利普光电科技有限公司 | Single-end to double-end differential analog circuit |
| CN109714020A (en) * | 2019-02-22 | 2019-05-03 | 南京国博电子有限公司 | For controlling the circuit of numerical-control attenuator overshoot |
| CN110855266A (en) * | 2019-11-27 | 2020-02-28 | 西安博瑞集信电子科技有限公司 | Single-voltage positive-voltage driven single-chip numerical control attenuator chip |
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